Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

49776

1

T1

107

T4

102

T5

31

full_word

24371

1

T1

17

T2

8

T4

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	73827	1			T1	124		T2	8		T4	112
auto[TlIntgErrCmd]	111	1			T27	5		T55	2		T56	6
auto[TlIntgErrData]	100	1			T27	4		T55	3		T56	8
auto[TlIntgErrBoth]	109	1			T27	1		T55	5		T56	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25991

1

T1

124

T2

8

T4

112

auto[1]

48156

1

T17

10880

T18

14584

T27

3

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18745	1			T1	107		T4	102		T5	31
auto[TlIntgErrNone]	partial	auto[1]	30746	1			T17	7520		T18	9580		T54	84
auto[TlIntgErrNone]	full_word	auto[0]	7104	1			T1	17		T2	8		T4	10
auto[TlIntgErrNone]	full_word	auto[1]	17232	1			T17	3360		T18	5004		T54	58
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T27	5		T55	1		T58	3
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T55	1		T56	6		T58	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T130	1		T125	1		T127	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T129	2		T130	1		T131	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T27	1		T56	3		T58	5
auto[TlIntgErrData]	partial	auto[1]	40	1			T27	3		T55	2		T56	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T132	1		T131	2		T128	1
auto[TlIntgErrData]	full_word	auto[1]	12	1			T55	1		T56	2		T58	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T27	1		T55	3		T56	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T55	1		T56	2		T58	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T133	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T55	1		T56	2		T58	1