Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg
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Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
rom_ctrl_kmac_cg 100.00 1 100 1 64 64




Group Instance : rom_ctrl_kmac_cg
Comment: KMAC interface behaviors
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rom_ctrl_kmac_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00


Variables for Group Instance rom_ctrl_kmac_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_kmac_done 3 0 3 100.00 100 1 1 0
cp_kmac_ready 4 0 4 100.00 100 1 1 0


Summary for Variable cp_kmac_done

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_kmac_done

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
kmac_first 299 1 T2 3 T11 2 T25 1
same_cycle 6 1 T7 1 T50 1 T51 1
rom_first 1087 1 T1 3 T2 13 T3 2



Summary for Variable cp_kmac_ready

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_kmac_ready

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
stall_repeat 3540744 1 T1 6193 T2 619178 T4 37507
stall_long 231555 1 T2 74298 T4 4513 T26 4424
stall_1 3267514 1 T1 12306 T2 12271 T4 733
zero_delay_5 5602346 1 T1 1575 T2 11 T3 16360

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