Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 14644 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 23523 1 T1 5 T2 3 T4 4



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 21313 1 T1 59 T2 3 T4 78
values[0x0] 8249 1 T16 4388 T27 138 T28 13
values[0x1] 8605 1 T16 4653 T27 135 T28 15



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 6569 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 31598 1 T1 31 T2 3 T4 44



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 85 1 T15 1 T62 1 T122 1
valid_sources[0x01] 106 1 T139 3 T140 2 T141 1
valid_sources[0x02] 72 1 T142 2 T143 4 T144 2
valid_sources[0x03] 78 1 T6 1 T123 1 T18 3
valid_sources[0x04] 99 1 T13 1 T123 3 T143 1
valid_sources[0x05] 103 1 T61 24 T123 2 T140 1
valid_sources[0x06] 72 1 T4 2 T123 5 T86 4
valid_sources[0x07] 254 1 T61 110 T143 9 T145 4
valid_sources[0x08] 100 1 T1 1 T87 36 T141 1
valid_sources[0x09] 203 1 T9 1 T13 1 T123 1
valid_sources[0x0a] 92 1 T123 3 T143 3 T145 1
valid_sources[0x0b] 445 1 T1 1 T123 3 T86 1
valid_sources[0x0c] 90 1 T9 3 T123 2 T140 1
valid_sources[0x0d] 79 1 T4 7 T6 1 T123 1
valid_sources[0x0e] 101 1 T4 2 T13 1 T122 3
valid_sources[0x0f] 370 1 T13 2 T62 1 T123 3
valid_sources[0x10] 79 1 T13 1 T123 2 T139 4
valid_sources[0x11] 109 1 T4 1 T9 3 T18 1
valid_sources[0x12] 465 1 T144 1 T146 1 T114 47
valid_sources[0x13] 197 1 T62 1 T123 3 T143 1
valid_sources[0x14] 58 1 T18 1 T144 1 T141 1
valid_sources[0x15] 295 1 T9 1 T13 2 T62 1
valid_sources[0x16] 115 1 T123 2 T143 3 T140 2
valid_sources[0x17] 130 1 T123 1 T147 1 T144 1
valid_sources[0x18] 153 1 T1 1 T62 1 T123 1
valid_sources[0x19] 318 1 T13 1 T122 1 T123 2
valid_sources[0x1a] 236 1 T1 1 T9 1 T20 1
valid_sources[0x1b] 286 1 T9 1 T123 3 T147 1
valid_sources[0x1c] 128 1 T13 1 T123 3 T143 2
valid_sources[0x1d] 93 1 T123 2 T86 3 T143 5
valid_sources[0x1e] 155 1 T123 1 T144 2 T141 1
valid_sources[0x1f] 119 1 T9 4 T123 1 T148 1
valid_sources[0x20] 146 1 T1 1 T14 1 T123 1
valid_sources[0x21] 97 1 T1 1 T6 5 T13 1
valid_sources[0x22] 400 1 T13 1 T62 1 T123 2
valid_sources[0x23] 302 1 T9 3 T13 2 T123 1
valid_sources[0x24] 95 1 T9 1 T14 1 T140 1
valid_sources[0x25] 91 1 T143 3 T140 4 T147 4
valid_sources[0x26] 117 1 T62 1 T19 1 T140 3
valid_sources[0x27] 91 1 T123 2 T143 3 T140 2
valid_sources[0x28] 435 1 T1 1 T143 2 T140 1
valid_sources[0x29] 84 1 T143 8 T139 11 T140 1
valid_sources[0x2a] 81 1 T123 2 T143 2 T139 1
valid_sources[0x2b] 224 1 T123 3 T143 1 T140 3
valid_sources[0x2c] 68 1 T4 16 T123 2 T139 6
valid_sources[0x2d] 66 1 T9 2 T62 1 T123 2
valid_sources[0x2e] 82 1 T1 1 T14 1 T140 4
valid_sources[0x2f] 90 1 T9 1 T13 1 T123 4
valid_sources[0x30] 106 1 T1 2 T6 3 T123 2
valid_sources[0x31] 99 1 T20 1 T123 2 T143 3
valid_sources[0x32] 69 1 T9 1 T13 1 T123 1
valid_sources[0x33] 745 1 T9 1 T140 5 T144 2
valid_sources[0x34] 238 1 T1 2 T123 4 T143 4
valid_sources[0x35] 127 1 T1 1 T13 1 T123 1
valid_sources[0x36] 90 1 T6 6 T14 1 T123 2
valid_sources[0x37] 77 1 T143 3 T140 2 T144 2
valid_sources[0x38] 79 1 T143 1 T144 2 T149 1
valid_sources[0x39] 133 1 T140 2 T148 3 T141 1
valid_sources[0x3a] 61 1 T123 1 T18 8 T143 1
valid_sources[0x3b] 98 1 T123 1 T143 2 T140 2
valid_sources[0x3c] 78 1 T1 1 T6 2 T123 1
valid_sources[0x3d] 106 1 T123 2 T86 4 T143 14
valid_sources[0x3e] 142 1 T123 1 T18 1 T143 4
valid_sources[0x3f] 97 1 T9 2 T13 1 T123 1
valid_sources[0x40] 92 1 T123 3 T140 1 T147 1
valid_sources[0x41] 129 1 T9 1 T140 1 T144 3
valid_sources[0x42] 89 1 T13 1 T123 2 T143 7
valid_sources[0x43] 211 1 T1 1 T61 44 T123 5
valid_sources[0x44] 112 1 T1 1 T62 1 T123 2
valid_sources[0x45] 64 1 T1 1 T13 1 T123 1
valid_sources[0x46] 122 1 T4 2 T123 2 T145 8
valid_sources[0x47] 67 1 T13 1 T123 3 T19 6
valid_sources[0x48] 130 1 T1 1 T140 2 T148 3
valid_sources[0x49] 318 1 T1 1 T147 4 T148 6
valid_sources[0x4a] 65 1 T123 2 T139 1 T140 1
valid_sources[0x4b] 94 1 T9 1 T13 1 T123 3
valid_sources[0x4c] 84 1 T13 2 T123 3 T86 7
valid_sources[0x4d] 105 1 T1 1 T13 1 T123 3
valid_sources[0x4e] 120 1 T9 3 T123 1 T86 4
valid_sources[0x4f] 67 1 T123 2 T140 1 T147 1
valid_sources[0x50] 96 1 T13 1 T123 2 T143 7
valid_sources[0x51] 118 1 T123 2 T86 2 T143 1
valid_sources[0x52] 122 1 T1 1 T125 13 T143 3
valid_sources[0x53] 135 1 T123 2 T18 1 T19 1
valid_sources[0x54] 98 1 T123 2 T143 1 T140 1
valid_sources[0x55] 91 1 T122 1 T19 1 T143 1
valid_sources[0x56] 65 1 T123 1 T140 1 T150 6
valid_sources[0x57] 321 1 T88 35 T140 2 T141 1
valid_sources[0x58] 82 1 T13 2 T123 1 T143 4
valid_sources[0x59] 97 1 T14 1 T143 1 T140 1
valid_sources[0x5a] 101 1 T9 1 T13 1 T123 2
valid_sources[0x5b] 106 1 T2 1 T62 2 T123 1
valid_sources[0x5c] 160 1 T17 1 T13 1 T20 1
valid_sources[0x5d] 51 1 T1 1 T9 1 T62 1
valid_sources[0x5e] 84 1 T123 1 T143 2 T140 3
valid_sources[0x5f] 76 1 T9 1 T18 1 T19 2
valid_sources[0x60] 109 1 T123 3 T125 24 T143 3
valid_sources[0x61] 402 1 T4 2 T13 2 T123 1
valid_sources[0x62] 75 1 T62 1 T123 1 T87 18
valid_sources[0x63] 84 1 T9 1 T62 1 T123 1
valid_sources[0x64] 120 1 T143 1 T145 12 T147 4
valid_sources[0x65] 104 1 T1 1 T6 3 T123 1
valid_sources[0x66] 98 1 T1 1 T123 2 T143 1
valid_sources[0x67] 115 1 T123 3 T18 1 T140 5
valid_sources[0x68] 83 1 T1 1 T13 1 T122 2
valid_sources[0x69] 91 1 T123 1 T143 4 T140 1
valid_sources[0x6a] 121 1 T122 4 T123 2 T140 1
valid_sources[0x6b] 56 1 T123 5 T150 2 T106 3
valid_sources[0x6c] 105 1 T123 1 T19 4 T139 1
valid_sources[0x6d] 485 1 T123 1 T63 33 T142 1
valid_sources[0x6e] 400 1 T1 1 T9 1 T123 2
valid_sources[0x6f] 84 1 T1 1 T13 1 T123 1
valid_sources[0x70] 116 1 T9 1 T123 1 T143 1
valid_sources[0x71] 88 1 T123 1 T19 2 T142 2
valid_sources[0x72] 125 1 T123 2 T18 1 T19 1
valid_sources[0x73] 134 1 T62 1 T123 1 T143 4
valid_sources[0x74] 122 1 T1 1 T13 1 T123 2
valid_sources[0x75] 161 1 T143 4 T144 1 T141 1
valid_sources[0x76] 69 1 T123 1 T140 2 T150 5
valid_sources[0x77] 128 1 T1 1 T62 1 T123 2
valid_sources[0x78] 762 1 T6 2 T41 2 T86 5
valid_sources[0x79] 168 1 T4 2 T9 3 T61 48
valid_sources[0x7a] 146 1 T9 1 T123 2 T142 1
valid_sources[0x7b] 102 1 T9 3 T13 1 T123 1
valid_sources[0x7c] 66 1 T4 2 T9 1 T123 5
valid_sources[0x7d] 115 1 T9 1 T13 1 T142 2
valid_sources[0x7e] 322 1 T1 1 T6 1 T13 1
valid_sources[0x7f] 105 1 T4 2 T123 1 T140 1
valid_sources[0x80] 105 1 T123 1 T140 2 T148 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7255 1 T1 5 T2 3 T4 4
values[0x0] all_enables biggest_size 8129 1 T16 4331 T27 136 T28 12
values[0x1] all_enables biggest_size 8139 1 T16 4418 T27 128 T28 12


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 7855 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 34558 1 T2 30 T4 18 T5 7



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 12949 1 T2 49 T4 32 T5 21
values[0x0] 14205 1 T8 11 T25 4 T26 2
values[0x1] 15259 1 T3 1 T8 8 T25 7



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5481 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 36932 1 T2 31 T4 20 T5 8



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 160 1 T151 1 T152 1 T153 2
valid_sources[0x01] 171 1 T8 1 T13 1 T71 1
valid_sources[0x02] 253 1 T108 1 T16 44 T154 1
valid_sources[0x03] 137 1 T14 1 T62 1 T89 1
valid_sources[0x04] 295 1 T13 1 T124 1 T89 1
valid_sources[0x05] 136 1 T63 1 T151 1 T34 1
valid_sources[0x06] 164 1 T155 2 T156 1 T157 1
valid_sources[0x07] 138 1 T8 1 T20 1 T71 2
valid_sources[0x08] 228 1 T88 1 T91 3 T158 1
valid_sources[0x09] 165 1 T5 1 T8 1 T20 1
valid_sources[0x0a] 159 1 T136 1 T152 2 T159 1
valid_sources[0x0b] 170 1 T160 2 T159 1 T161 1
valid_sources[0x0c] 137 1 T63 1 T108 1 T162 1
valid_sources[0x0d] 166 1 T5 1 T15 5 T163 4
valid_sources[0x0e] 114 1 T15 3 T16 40 T154 1
valid_sources[0x0f] 142 1 T14 1 T124 1 T88 5
valid_sources[0x10] 156 1 T20 1 T164 1 T14 1
valid_sources[0x11] 119 1 T136 1 T165 1 T40 1
valid_sources[0x12] 160 1 T108 1 T166 1 T157 2
valid_sources[0x13] 170 1 T6 3 T62 1 T63 3
valid_sources[0x14] 166 1 T136 1 T167 2 T16 43
valid_sources[0x15] 164 1 T8 1 T71 1 T148 1
valid_sources[0x16] 146 1 T15 2 T14 1 T88 1
valid_sources[0x17] 193 1 T5 1 T124 2 T168 1
valid_sources[0x18] 168 1 T14 1 T160 1 T33 1
valid_sources[0x19] 130 1 T13 1 T18 1 T40 1
valid_sources[0x1a] 144 1 T8 1 T13 1 T88 1
valid_sources[0x1b] 150 1 T169 5 T91 7 T166 1
valid_sources[0x1c] 143 1 T107 1 T159 1 T170 1
valid_sources[0x1d] 112 1 T171 2 T172 1 T173 1
valid_sources[0x1e] 155 1 T63 1 T110 2 T174 1
valid_sources[0x1f] 143 1 T68 1 T165 1 T160 1
valid_sources[0x20] 212 1 T4 2 T13 1 T165 1
valid_sources[0x21] 235 1 T108 1 T152 1 T31 1
valid_sources[0x22] 113 1 T40 1 T152 1 T16 46
valid_sources[0x23] 168 1 T63 1 T136 1 T166 1
valid_sources[0x24] 224 1 T148 1 T151 2 T138 2
valid_sources[0x25] 424 1 T69 1 T73 1 T148 1
valid_sources[0x26] 142 1 T5 1 T151 1 T16 40
valid_sources[0x27] 152 1 T87 1 T175 1 T16 43
valid_sources[0x28] 144 1 T18 2 T176 3 T163 2
valid_sources[0x29] 190 1 T8 2 T124 11 T177 1
valid_sources[0x2a] 153 1 T8 1 T124 1 T71 1
valid_sources[0x2b] 138 1 T4 2 T12 1 T63 1
valid_sources[0x2c] 185 1 T63 1 T69 1 T178 1
valid_sources[0x2d] 199 1 T13 1 T63 1 T165 1
valid_sources[0x2e] 125 1 T11 1 T18 2 T110 3
valid_sources[0x2f] 136 1 T4 1 T6 6 T165 1
valid_sources[0x30] 174 1 T13 1 T136 1 T73 1
valid_sources[0x31] 127 1 T4 1 T11 1 T62 1
valid_sources[0x32] 117 1 T160 1 T174 2 T34 1
valid_sources[0x33] 166 1 T25 11 T14 1 T63 1
valid_sources[0x34] 151 1 T13 1 T18 8 T148 1
valid_sources[0x35] 147 1 T5 1 T148 4 T16 40
valid_sources[0x36] 257 1 T13 1 T165 2 T178 1
valid_sources[0x37] 205 1 T20 1 T87 6 T165 2
valid_sources[0x38] 125 1 T163 3 T152 1 T16 41
valid_sources[0x39] 152 1 T11 1 T88 1 T90 16
valid_sources[0x3a] 137 1 T11 1 T68 1 T88 2
valid_sources[0x3b] 121 1 T14 1 T63 1 T148 1
valid_sources[0x3c] 126 1 T14 1 T63 1 T148 1
valid_sources[0x3d] 173 1 T63 1 T124 1 T71 1
valid_sources[0x3e] 106 1 T13 3 T179 1 T174 1
valid_sources[0x3f] 145 1 T8 1 T180 1 T181 1
valid_sources[0x40] 157 1 T89 2 T182 1 T183 1
valid_sources[0x41] 162 1 T8 1 T20 1 T184 1
valid_sources[0x42] 196 1 T5 1 T13 1 T170 3
valid_sources[0x43] 185 1 T62 1 T136 1 T163 1
valid_sources[0x44] 162 1 T4 5 T14 1 T41 10
valid_sources[0x45] 134 1 T185 6 T174 1 T175 1
valid_sources[0x46] 141 1 T4 1 T63 1 T18 4
valid_sources[0x47] 197 1 T13 1 T136 2 T110 3
valid_sources[0x48] 122 1 T4 2 T20 1 T15 4
valid_sources[0x49] 211 1 T11 3 T22 20 T186 2
valid_sources[0x4a] 123 1 T187 1 T160 1 T183 1
valid_sources[0x4b] 129 1 T5 1 T63 2 T184 1
valid_sources[0x4c] 171 1 T5 2 T8 1 T186 2
valid_sources[0x4d] 183 1 T13 1 T14 1 T73 1
valid_sources[0x4e] 126 1 T188 1 T156 1 T16 45
valid_sources[0x4f] 134 1 T148 1 T160 1 T159 2
valid_sources[0x50] 190 1 T165 1 T158 2 T162 1
valid_sources[0x51] 113 1 T11 2 T71 1 T108 1
valid_sources[0x52] 102 1 T63 1 T148 1 T33 1
valid_sources[0x53] 209 1 T87 1 T88 1 T148 1
valid_sources[0x54] 164 1 T148 1 T151 3 T189 1
valid_sources[0x55] 312 1 T165 1 T40 1 T166 1
valid_sources[0x56] 129 1 T148 1 T152 1 T178 1
valid_sources[0x57] 116 1 T14 1 T110 1 T174 1
valid_sources[0x58] 131 1 T88 1 T73 1 T165 1
valid_sources[0x59] 170 1 T108 1 T113 12 T158 2
valid_sources[0x5a] 143 1 T88 1 T190 1 T40 2
valid_sources[0x5b] 174 1 T71 1 T136 1 T40 1
valid_sources[0x5c] 141 1 T8 1 T109 2 T40 1
valid_sources[0x5d] 136 1 T11 4 T13 1 T108 1
valid_sources[0x5e] 180 1 T88 1 T165 1 T163 1
valid_sources[0x5f] 168 1 T5 1 T14 1 T151 1
valid_sources[0x60] 137 1 T88 2 T174 2 T40 1
valid_sources[0x61] 120 1 T26 2 T166 1 T170 1
valid_sources[0x62] 153 1 T136 1 T151 2 T16 39
valid_sources[0x63] 174 1 T88 1 T137 38 T110 1
valid_sources[0x64] 172 1 T160 1 T163 1 T191 1
valid_sources[0x65] 164 1 T165 1 T192 8 T183 1
valid_sources[0x66] 136 1 T14 1 T63 1 T108 1
valid_sources[0x67] 122 1 T18 1 T160 1 T34 1
valid_sources[0x68] 116 1 T4 3 T10 1 T169 5
valid_sources[0x69] 271 1 T62 1 T165 1 T152 1
valid_sources[0x6a] 130 1 T63 3 T71 1 T163 1
valid_sources[0x6b] 126 1 T185 6 T160 1 T163 2
valid_sources[0x6c] 229 1 T41 10 T152 1 T16 49
valid_sources[0x6d] 158 1 T160 2 T34 1 T166 1
valid_sources[0x6e] 182 1 T13 1 T174 5 T186 1
valid_sources[0x6f] 144 1 T5 1 T142 16 T193 2
valid_sources[0x70] 143 1 T13 1 T194 1 T162 2
valid_sources[0x71] 161 1 T14 1 T63 1 T16 39
valid_sources[0x72] 136 1 T13 1 T63 1 T165 1
valid_sources[0x73] 122 1 T14 1 T43 1 T148 1
valid_sources[0x74] 123 1 T8 1 T14 1 T88 1
valid_sources[0x75] 252 1 T14 1 T87 4 T160 1
valid_sources[0x76] 136 1 T3 1 T11 1 T87 1
valid_sources[0x77] 284 1 T14 1 T62 1 T195 1
valid_sources[0x78] 163 1 T62 1 T148 1 T159 2
valid_sources[0x79] 207 1 T15 1 T18 1 T148 1
valid_sources[0x7a] 168 1 T4 1 T177 1 T152 1
valid_sources[0x7b] 119 1 T14 1 T26 1 T158 5
valid_sources[0x7c] 190 1 T8 1 T11 1 T26 2
valid_sources[0x7d] 169 1 T124 2 T148 1 T191 1
valid_sources[0x7e] 132 1 T124 1 T88 3 T196 6
valid_sources[0x7f] 137 1 T11 3 T162 1 T155 1
valid_sources[0x80] 159 1 T5 1 T63 1 T175 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 8048 1 T2 30 T4 18 T5 7
values[0x0] all_enables biggest_size 13336 1 T8 2 T25 1 T70 4
values[0x1] all_enables biggest_size 13174 1 T8 1 T26 1 T69 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%