Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

53825

1

T1

54

T4

74

T6

38

full_word

26979

1

T1

5

T2

2

T4

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	80484	1			T1	59		T2	2		T4	78
auto[TlIntgErrCmd]	94	1			T46	5		T48	1		T50	7
auto[TlIntgErrData]	113	1			T46	12		T48	5		T50	7
auto[TlIntgErrBoth]	113	1			T46	3		T48	4		T50	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25568

1

T1

59

T2

2

T4

78

auto[1]

55236

1

T16

30951

T27

831

T28

91

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17727	1			T1	54		T4	74		T6	38
auto[TlIntgErrNone]	partial	auto[1]	35805	1			T16	20541		T27	506		T28	59
auto[TlIntgErrNone]	full_word	auto[0]	7689	1			T1	5		T2	2		T4	4
auto[TlIntgErrNone]	full_word	auto[1]	19263	1			T16	10410		T27	325		T28	32
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T46	2		T50	2		T47	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T46	3		T48	1		T50	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T50	1		T130	1		T129	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T131	1		T132	1		T133	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T46	4		T48	2		T50	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T46	7		T48	2		T50	5
auto[TlIntgErrData]	full_word	auto[0]	3	1			T46	1		T48	1		T47	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T76	1		T130	1		T133	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T46	1		T48	2		T50	3
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T46	2		T48	2		T50	3
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T74	1		T130	2		T134	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T47	1		T128	1		T135	1