Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35086	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

319958

1

T1

24

T2

4913

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	110871	1			T1	230		T2	1418		T3	46
values[0x0]	120012	1			T2	1818		T8	419		T11	5426
values[0x1]	124161	1			T2	1943		T8	411		T11	5688

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16478	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

338566

1

T1

130

T2

5047

T3

29

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1162	1			T2	4		T8	13		T18	4
valid_sources[0x01]	1282	1			T1	1		T8	7		T18	3
valid_sources[0x02]	1861	1			T1	2		T2	15		T8	1
valid_sources[0x03]	1446	1			T2	2		T8	11		T18	1
valid_sources[0x04]	1334	1			T1	1		T8	12		T18	2
valid_sources[0x05]	1791	1			T1	4		T8	3		T18	1
valid_sources[0x06]	1215	1			T1	2		T2	17		T8	19
valid_sources[0x07]	1337	1			T1	2		T8	1		T18	2
valid_sources[0x08]	1241	1			T1	6		T8	4		T18	3
valid_sources[0x09]	1164	1			T1	2		T8	2		T11	90
valid_sources[0x0a]	1543	1			T8	1		T18	3		T19	1
valid_sources[0x0b]	1577	1			T1	1		T4	16		T8	12
valid_sources[0x0c]	1392	1			T8	4		T11	116		T12	10
valid_sources[0x0d]	1296	1			T2	2		T8	7		T19	20
valid_sources[0x0e]	1248	1			T1	3		T3	6		T8	2
valid_sources[0x0f]	1260	1			T8	9		T11	2		T12	14
valid_sources[0x10]	1938	1			T2	712		T8	17		T11	86
valid_sources[0x11]	1506	1			T2	11		T8	4		T18	1
valid_sources[0x12]	1467	1			T1	3		T2	307		T8	1
valid_sources[0x13]	1389	1			T1	1		T18	2		T25	2
valid_sources[0x14]	1627	1			T8	1		T11	38		T70	4
valid_sources[0x15]	1177	1			T8	1		T10	2		T18	3
valid_sources[0x16]	1134	1			T1	2		T8	4		T18	1
valid_sources[0x17]	1501	1			T8	4		T18	1		T51	3
valid_sources[0x18]	1627	1			T3	3		T8	3		T18	2
valid_sources[0x19]	1286	1			T1	1		T8	7		T11	114
valid_sources[0x1a]	1117	1			T1	1		T8	3		T18	1
valid_sources[0x1b]	1439	1			T2	176		T18	3		T11	71
valid_sources[0x1c]	1081	1			T1	1		T8	2		T18	1
valid_sources[0x1d]	1113	1			T1	4		T8	3		T18	1
valid_sources[0x1e]	1752	1			T8	4		T18	1		T12	96
valid_sources[0x1f]	1150	1			T1	1		T8	5		T18	1
valid_sources[0x20]	1399	1			T1	1		T8	11		T18	1
valid_sources[0x21]	1217	1			T1	1		T18	6		T15	1
valid_sources[0x22]	1389	1			T2	379		T11	42		T52	13
valid_sources[0x23]	1167	1			T1	3		T8	5		T18	2
valid_sources[0x24]	1285	1			T1	1		T8	1		T18	3
valid_sources[0x25]	1175	1			T1	1		T8	7		T18	5
valid_sources[0x26]	1191	1			T8	1		T18	1		T11	10
valid_sources[0x27]	1127	1			T2	3		T8	7		T12	29
valid_sources[0x28]	1100	1			T8	2		T18	2		T12	26
valid_sources[0x29]	1858	1			T2	478		T8	6		T18	3
valid_sources[0x2a]	1328	1			T8	4		T18	3		T11	103
valid_sources[0x2b]	1240	1			T8	3		T18	1		T11	1
valid_sources[0x2c]	2255	1			T2	138		T3	4		T18	1
valid_sources[0x2d]	1649	1			T2	411		T8	2		T18	2
valid_sources[0x2e]	1420	1			T1	1		T8	1		T18	2
valid_sources[0x2f]	2296	1			T1	3		T8	3		T18	2
valid_sources[0x30]	2195	1			T2	4		T8	2		T18	1
valid_sources[0x31]	1479	1			T1	1		T2	38		T8	1
valid_sources[0x32]	2134	1			T2	179		T8	5		T18	1
valid_sources[0x33]	1509	1			T8	1		T18	2		T51	3
valid_sources[0x34]	1339	1			T1	2		T8	1		T18	1
valid_sources[0x35]	1189	1			T1	1		T18	1		T11	94
valid_sources[0x36]	1006	1			T1	1		T8	1		T18	2
valid_sources[0x37]	1149	1			T1	4		T8	1		T11	102
valid_sources[0x38]	1150	1			T1	1		T8	4		T18	2
valid_sources[0x39]	1291	1			T1	1		T8	10		T18	2
valid_sources[0x3a]	1316	1			T2	10		T8	6		T18	3
valid_sources[0x3b]	1421	1			T1	2		T2	28		T18	3
valid_sources[0x3c]	1497	1			T8	2		T18	2		T11	52
valid_sources[0x3d]	1392	1			T8	7		T11	140		T12	10
valid_sources[0x3e]	1271	1			T1	1		T8	4		T18	1
valid_sources[0x3f]	1070	1			T8	6		T18	2		T11	14
valid_sources[0x40]	1253	1			T1	3		T2	27		T8	7
valid_sources[0x41]	1359	1			T8	8		T18	1		T11	162
valid_sources[0x42]	1143	1			T2	12		T3	2		T8	8
valid_sources[0x43]	1212	1			T2	229		T8	2		T18	2
valid_sources[0x44]	2239	1			T18	3		T11	238		T12	2
valid_sources[0x45]	1310	1			T8	1		T11	52		T12	158
valid_sources[0x46]	1508	1			T2	11		T8	4		T18	1
valid_sources[0x47]	1111	1			T8	12		T18	2		T15	1
valid_sources[0x48]	1213	1			T1	1		T8	2		T18	2
valid_sources[0x49]	1175	1			T1	1		T8	6		T18	1
valid_sources[0x4a]	1251	1			T2	11		T8	1		T18	1
valid_sources[0x4b]	1204	1			T1	2		T8	7		T18	5
valid_sources[0x4c]	1549	1			T2	2		T10	12		T18	1
valid_sources[0x4d]	1818	1			T2	275		T3	3		T8	4
valid_sources[0x4e]	1284	1			T2	17		T8	2		T18	2
valid_sources[0x4f]	1397	1			T1	1		T8	2		T18	4
valid_sources[0x50]	2068	1			T18	1		T19	4		T11	2
valid_sources[0x51]	1518	1			T8	14		T18	1		T11	33
valid_sources[0x52]	1041	1			T1	2		T2	10		T8	3
valid_sources[0x53]	1341	1			T2	29		T8	3		T15	2
valid_sources[0x54]	1445	1			T8	4		T18	3		T19	13
valid_sources[0x55]	1262	1			T1	2		T2	1		T8	2
valid_sources[0x56]	1414	1			T1	1		T8	5		T18	1
valid_sources[0x57]	1225	1			T1	2		T8	3		T18	1
valid_sources[0x58]	1248	1			T8	15		T15	1		T11	17
valid_sources[0x59]	2054	1			T1	1		T11	14		T12	41
valid_sources[0x5a]	1354	1			T2	22		T8	11		T18	2
valid_sources[0x5b]	1750	1			T1	3		T8	1		T18	1
valid_sources[0x5c]	1330	1			T19	30		T11	16		T52	24
valid_sources[0x5d]	1256	1			T1	2		T8	7		T18	2
valid_sources[0x5e]	1108	1			T1	1		T8	4		T51	3
valid_sources[0x5f]	1813	1			T1	3		T18	4		T11	189
valid_sources[0x60]	1471	1			T1	1		T8	5		T18	1
valid_sources[0x61]	1082	1			T1	5		T8	6		T18	4
valid_sources[0x62]	1143	1			T1	3		T8	4		T18	3
valid_sources[0x63]	1199	1			T1	4		T8	3		T87	1
valid_sources[0x64]	1413	1			T1	1		T3	5		T8	12
valid_sources[0x65]	1642	1			T8	2		T18	2		T19	8
valid_sources[0x66]	1161	1			T8	3		T18	1		T11	34
valid_sources[0x67]	1752	1			T1	2		T8	2		T18	4
valid_sources[0x68]	1136	1			T2	10		T8	2		T18	3
valid_sources[0x69]	1467	1			T1	1		T3	2		T8	5
valid_sources[0x6a]	1480	1			T1	1		T8	5		T18	2
valid_sources[0x6b]	1510	1			T8	30		T18	2		T11	41
valid_sources[0x6c]	1691	1			T2	53		T8	7		T18	2
valid_sources[0x6d]	1246	1			T1	1		T8	5		T18	3
valid_sources[0x6e]	1517	1			T8	8		T87	1		T13	66
valid_sources[0x6f]	1770	1			T8	7		T18	4		T11	128
valid_sources[0x70]	1247	1			T1	1		T8	10		T18	2
valid_sources[0x71]	1386	1			T18	1		T12	15		T87	2
valid_sources[0x72]	1162	1			T1	2		T18	1		T11	47
valid_sources[0x73]	1298	1			T8	2		T10	5		T18	5
valid_sources[0x74]	1279	1			T1	1		T8	14		T18	4
valid_sources[0x75]	1689	1			T2	224		T6	1		T8	1
valid_sources[0x76]	1420	1			T3	10		T8	4		T18	1
valid_sources[0x77]	1110	1			T1	1		T18	2		T15	1
valid_sources[0x78]	1326	1			T1	1		T8	5		T18	3
valid_sources[0x79]	1442	1			T8	1		T18	1		T11	62
valid_sources[0x7a]	2824	1			T1	1		T8	5		T18	1
valid_sources[0x7b]	1454	1			T2	30		T8	12		T18	1
valid_sources[0x7c]	1111	1			T8	15		T18	1		T11	3
valid_sources[0x7d]	1172	1			T8	4		T10	1		T15	6
valid_sources[0x7e]	1218	1			T1	3		T8	3		T10	5
valid_sources[0x7f]	1249	1			T18	1		T11	21		T12	43
valid_sources[0x80]	1593	1			T1	1		T8	8		T18	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

82226

1

T1

24

T2

1246

T3

4

values[0x0]

all_enables

biggest_size

119013

1

T2

1802

T8

412

T11

5382

values[0x1]

all_enables

biggest_size

118719

1

T2

1865

T8

387

T11

5470

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31909	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

265285

1

T2

4147

T3

10

T4

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	80450	1			T2	1171		T3	16		T4	16
values[0x0]	100795	1			T2	1558		T8	472		T33	2
values[0x1]	115949	1			T2	1754		T8	563		T33	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16743	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

280451

1

T2

4324

T3

11

T4

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1202	1			T2	11		T8	5		T10	1
valid_sources[0x01]	1469	1			T2	22		T8	2		T11	28
valid_sources[0x02]	987	1			T2	16		T8	5		T11	46
valid_sources[0x03]	1119	1			T2	16		T8	9		T11	54
valid_sources[0x04]	1032	1			T2	21		T8	2		T11	59
valid_sources[0x05]	1165	1			T2	19		T8	2		T51	1
valid_sources[0x06]	1034	1			T2	11		T8	2		T25	3
valid_sources[0x07]	841	1			T2	15		T8	4		T33	2
valid_sources[0x08]	953	1			T2	16		T8	1		T11	57
valid_sources[0x09]	1081	1			T2	19		T8	5		T25	1
valid_sources[0x0a]	1017	1			T2	19		T8	2		T11	41
valid_sources[0x0b]	1075	1			T2	12		T8	10		T11	43
valid_sources[0x0c]	1002	1			T2	18		T8	2		T11	37
valid_sources[0x0d]	879	1			T2	20		T8	5		T11	59
valid_sources[0x0e]	1613	1			T2	15		T8	4		T15	3
valid_sources[0x0f]	1837	1			T2	21		T8	10		T11	64
valid_sources[0x10]	1266	1			T2	17		T8	9		T25	3
valid_sources[0x11]	1134	1			T2	19		T8	7		T11	54
valid_sources[0x12]	1432	1			T2	17		T8	5		T34	1
valid_sources[0x13]	1287	1			T2	20		T8	8		T11	50
valid_sources[0x14]	1219	1			T2	18		T8	5		T11	43
valid_sources[0x15]	1216	1			T2	19		T8	4		T17	1
valid_sources[0x16]	1293	1			T2	14		T8	11		T25	2
valid_sources[0x17]	1257	1			T2	17		T8	4		T11	19
valid_sources[0x18]	1485	1			T2	13		T11	64		T12	4
valid_sources[0x19]	1278	1			T2	21		T8	6		T11	43
valid_sources[0x1a]	1213	1			T2	11		T8	2		T11	63
valid_sources[0x1b]	1070	1			T2	10		T8	5		T11	46
valid_sources[0x1c]	813	1			T2	13		T8	6		T11	59
valid_sources[0x1d]	1705	1			T2	17		T11	58		T12	3
valid_sources[0x1e]	879	1			T2	19		T8	9		T17	1
valid_sources[0x1f]	1182	1			T2	17		T8	4		T11	20
valid_sources[0x20]	1261	1			T2	16		T8	6		T11	52
valid_sources[0x21]	1238	1			T2	15		T8	4		T11	40
valid_sources[0x22]	1288	1			T2	20		T8	2		T17	1
valid_sources[0x23]	1200	1			T2	23		T8	11		T11	72
valid_sources[0x24]	1087	1			T2	18		T8	7		T11	59
valid_sources[0x25]	1033	1			T2	22		T8	7		T11	34
valid_sources[0x26]	1440	1			T2	16		T8	10		T11	60
valid_sources[0x27]	1168	1			T2	14		T8	8		T11	51
valid_sources[0x28]	1164	1			T2	20		T8	5		T11	67
valid_sources[0x29]	1297	1			T2	22		T8	1		T51	1
valid_sources[0x2a]	1003	1			T2	22		T8	7		T15	1
valid_sources[0x2b]	900	1			T2	18		T8	6		T11	36
valid_sources[0x2c]	1029	1			T2	26		T8	7		T17	1
valid_sources[0x2d]	1043	1			T2	24		T8	4		T51	1
valid_sources[0x2e]	1459	1			T2	20		T8	3		T11	69
valid_sources[0x2f]	1158	1			T2	13		T8	8		T17	1
valid_sources[0x30]	1123	1			T2	24		T8	3		T11	49
valid_sources[0x31]	1101	1			T2	24		T8	6		T11	36
valid_sources[0x32]	1028	1			T2	18		T8	13		T10	1
valid_sources[0x33]	1747	1			T2	14		T8	4		T11	39
valid_sources[0x34]	1223	1			T2	21		T8	2		T10	1
valid_sources[0x35]	1103	1			T2	25		T8	4		T15	2
valid_sources[0x36]	1265	1			T2	20		T3	1		T8	4
valid_sources[0x37]	1389	1			T2	14		T8	1		T10	1
valid_sources[0x38]	1291	1			T2	21		T8	8		T11	61
valid_sources[0x39]	1084	1			T2	29		T8	4		T11	37
valid_sources[0x3a]	1104	1			T2	19		T8	9		T11	30
valid_sources[0x3b]	933	1			T2	21		T8	7		T11	56
valid_sources[0x3c]	1533	1			T2	14		T8	3		T10	1
valid_sources[0x3d]	1001	1			T2	27		T8	6		T11	39
valid_sources[0x3e]	1093	1			T2	15		T11	58		T12	2
valid_sources[0x3f]	1039	1			T2	26		T8	8		T11	38
valid_sources[0x40]	779	1			T2	17		T8	11		T11	43
valid_sources[0x41]	858	1			T2	18		T8	8		T11	39
valid_sources[0x42]	855	1			T2	17		T8	6		T15	2
valid_sources[0x43]	959	1			T2	14		T8	4		T11	40
valid_sources[0x44]	1318	1			T2	19		T8	6		T10	2
valid_sources[0x45]	1050	1			T2	16		T8	5		T11	54
valid_sources[0x46]	1106	1			T2	25		T4	11		T8	4
valid_sources[0x47]	1735	1			T2	17		T8	1		T11	79
valid_sources[0x48]	977	1			T2	24		T8	3		T11	35
valid_sources[0x49]	1042	1			T2	12		T4	2		T8	2
valid_sources[0x4a]	1058	1			T2	17		T8	6		T10	1
valid_sources[0x4b]	971	1			T2	16		T8	3		T11	41
valid_sources[0x4c]	1016	1			T2	12		T8	1		T51	1
valid_sources[0x4d]	1373	1			T2	17		T8	11		T10	1
valid_sources[0x4e]	880	1			T2	24		T8	3		T10	1
valid_sources[0x4f]	1483	1			T2	12		T8	5		T11	51
valid_sources[0x50]	908	1			T2	18		T8	3		T10	1
valid_sources[0x51]	1006	1			T2	13		T11	50		T12	4
valid_sources[0x52]	1175	1			T2	13		T3	1		T8	8
valid_sources[0x53]	975	1			T2	24		T8	7		T11	45
valid_sources[0x54]	1265	1			T2	15		T8	8		T11	55
valid_sources[0x55]	1586	1			T2	19		T8	5		T11	65
valid_sources[0x56]	913	1			T2	20		T8	4		T11	40
valid_sources[0x57]	1186	1			T2	13		T8	5		T11	46
valid_sources[0x58]	962	1			T2	21		T8	4		T10	2
valid_sources[0x59]	881	1			T2	15		T8	2		T11	59
valid_sources[0x5a]	947	1			T2	19		T8	4		T11	39
valid_sources[0x5b]	882	1			T2	21		T8	4		T17	1
valid_sources[0x5c]	920	1			T2	18		T8	9		T11	45
valid_sources[0x5d]	830	1			T2	13		T8	1		T48	1
valid_sources[0x5e]	1192	1			T2	22		T3	1		T8	8
valid_sources[0x5f]	1422	1			T2	20		T8	9		T51	2
valid_sources[0x60]	883	1			T2	18		T8	14		T51	1
valid_sources[0x61]	1381	1			T2	18		T8	3		T11	68
valid_sources[0x62]	1810	1			T2	25		T8	11		T15	1
valid_sources[0x63]	2290	1			T2	11		T8	11		T11	42
valid_sources[0x64]	1285	1			T2	20		T8	5		T11	36
valid_sources[0x65]	1024	1			T2	11		T10	1		T11	56
valid_sources[0x66]	1560	1			T2	20		T8	1		T51	1
valid_sources[0x67]	1161	1			T2	42		T8	9		T10	1
valid_sources[0x68]	1100	1			T2	15		T8	2		T15	1
valid_sources[0x69]	1354	1			T2	17		T8	2		T11	62
valid_sources[0x6a]	911	1			T2	13		T8	6		T17	1
valid_sources[0x6b]	1051	1			T2	9		T8	12		T11	42
valid_sources[0x6c]	1184	1			T2	6		T8	8		T11	61
valid_sources[0x6d]	1174	1			T2	13		T8	6		T11	54
valid_sources[0x6e]	1156	1			T2	18		T8	1		T11	48
valid_sources[0x6f]	1067	1			T2	13		T3	1		T8	11
valid_sources[0x70]	917	1			T2	9		T8	6		T11	56
valid_sources[0x71]	1363	1			T2	18		T3	3		T8	5
valid_sources[0x72]	967	1			T2	23		T8	6		T11	56
valid_sources[0x73]	921	1			T2	19		T8	5		T11	36
valid_sources[0x74]	1326	1			T2	18		T8	7		T11	33
valid_sources[0x75]	1548	1			T2	18		T8	7		T11	41
valid_sources[0x76]	901	1			T2	17		T8	7		T17	3
valid_sources[0x77]	1284	1			T2	24		T8	2		T11	70
valid_sources[0x78]	887	1			T2	13		T3	1		T8	4
valid_sources[0x79]	1051	1			T2	15		T8	5		T11	62
valid_sources[0x7a]	966	1			T2	17		T8	7		T11	46
valid_sources[0x7b]	884	1			T2	18		T8	6		T11	41
valid_sources[0x7c]	1394	1			T2	16		T8	7		T11	42
valid_sources[0x7d]	1021	1			T2	22		T8	7		T11	43
valid_sources[0x7e]	1352	1			T2	25		T8	7		T11	40
valid_sources[0x7f]	1287	1			T2	18		T8	7		T11	34
valid_sources[0x80]	1471	1			T2	13		T8	2		T15	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68437

1

T2

1089

T3

10

T4

9

values[0x0]

all_enables

biggest_size

98366

1

T2

1534

T8

460

T34

1

values[0x1]

all_enables

biggest_size

98482

1

T2

1524

T8

478

T11

4228