Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

590415

1

T1

206

T2

9307

T3

42

full_word

371191

1

T1

24

T2

5700

T3

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	961276	1			T1	230		T2	15007		T3	46
auto[TlIntgErrCmd]	124	1			T54	11		T55	8		T56	3
auto[TlIntgErrData]	100	1			T54	2		T55	7		T56	1
auto[TlIntgErrBoth]	106	1			T54	7		T55	5		T56	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173021

1

T1

230

T2

2402

T3

46

auto[1]

788585

1

T2

12605

T8

3211

T11

35225

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	83354	1			T1	206		T2	1042		T3	42
auto[TlIntgErrNone]	partial	auto[1]	506761	1			T2	8265		T8	2232		T11	22393
auto[TlIntgErrNone]	full_word	auto[0]	89520	1			T1	24		T2	1360		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	281641	1			T2	4340		T8	979		T11	12832
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T54	4		T55	4		T56	1
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T54	6		T55	3		T56	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T90	1		T93	2		T97	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T54	1		T55	1		T98	2
auto[TlIntgErrData]	partial	auto[0]	48	1			T55	3		T90	3		T93	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T54	2		T55	3		T56	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T93	1		T99	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T55	1		T92	1		T100	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T54	1		T56	1		T90	3
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T54	6		T55	4		T56	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T93	1		T101	2		T102	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T55	1		T56	1		T93	1