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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.53 96.89 92.56 97.67 100.00 98.62 97.90 99.06


Total test records in report: 456
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T296 /workspace/coverage/default/41.rom_ctrl_stress_all.4037583394 Aug 16 06:15:31 PM PDT 24 Aug 16 06:15:50 PM PDT 24 1057016410 ps
T297 /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.257419351 Aug 16 06:14:55 PM PDT 24 Aug 16 06:16:25 PM PDT 24 4320122405 ps
T298 /workspace/coverage/default/43.rom_ctrl_alert_test.1492443823 Aug 16 06:15:43 PM PDT 24 Aug 16 06:15:48 PM PDT 24 87354529 ps
T299 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.490404036 Aug 16 06:15:41 PM PDT 24 Aug 16 06:15:51 PM PDT 24 522040912 ps
T300 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.375836477 Aug 16 06:15:12 PM PDT 24 Aug 16 06:17:40 PM PDT 24 4731011710 ps
T301 /workspace/coverage/default/43.rom_ctrl_stress_all.1792883175 Aug 16 06:15:45 PM PDT 24 Aug 16 06:15:57 PM PDT 24 568271107 ps
T302 /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3167962623 Aug 16 06:15:34 PM PDT 24 Aug 16 06:18:11 PM PDT 24 16587603010 ps
T303 /workspace/coverage/default/1.rom_ctrl_alert_test.2280153575 Aug 16 06:14:40 PM PDT 24 Aug 16 06:14:45 PM PDT 24 1241326705 ps
T304 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1245423828 Aug 16 06:15:38 PM PDT 24 Aug 16 06:15:46 PM PDT 24 522358508 ps
T305 /workspace/coverage/default/2.rom_ctrl_alert_test.2704087970 Aug 16 06:14:34 PM PDT 24 Aug 16 06:14:39 PM PDT 24 173890653 ps
T306 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.320030097 Aug 16 06:14:32 PM PDT 24 Aug 16 06:14:41 PM PDT 24 350145714 ps
T307 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.684016780 Aug 16 06:15:24 PM PDT 24 Aug 16 06:15:33 PM PDT 24 169022680 ps
T308 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4210786262 Aug 16 06:15:32 PM PDT 24 Aug 16 06:15:38 PM PDT 24 488942900 ps
T309 /workspace/coverage/default/31.rom_ctrl_stress_all.2618107560 Aug 16 06:15:28 PM PDT 24 Aug 16 06:15:45 PM PDT 24 585864528 ps
T310 /workspace/coverage/default/47.rom_ctrl_alert_test.1904733253 Aug 16 06:15:44 PM PDT 24 Aug 16 06:15:48 PM PDT 24 96758361 ps
T311 /workspace/coverage/default/36.rom_ctrl_alert_test.2734677273 Aug 16 06:15:34 PM PDT 24 Aug 16 06:15:38 PM PDT 24 1186331648 ps
T312 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3042650263 Aug 16 06:14:55 PM PDT 24 Aug 16 06:15:06 PM PDT 24 259141094 ps
T313 /workspace/coverage/default/3.rom_ctrl_smoke.18591229 Aug 16 06:14:33 PM PDT 24 Aug 16 06:14:39 PM PDT 24 143591867 ps
T314 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4293453583 Aug 16 06:15:48 PM PDT 24 Aug 16 06:15:59 PM PDT 24 996999443 ps
T315 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2165201135 Aug 16 06:15:33 PM PDT 24 Aug 16 06:15:39 PM PDT 24 540713857 ps
T316 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3254285731 Aug 16 06:15:42 PM PDT 24 Aug 16 06:17:14 PM PDT 24 3587000795 ps
T317 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1727007719 Aug 16 06:15:22 PM PDT 24 Aug 16 06:15:31 PM PDT 24 172196667 ps
T318 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1543905738 Aug 16 06:15:22 PM PDT 24 Aug 16 06:15:33 PM PDT 24 531150963 ps
T319 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3485216939 Aug 16 06:15:26 PM PDT 24 Aug 16 06:16:24 PM PDT 24 4793511101 ps
T320 /workspace/coverage/default/15.rom_ctrl_stress_all.3041401358 Aug 16 06:14:59 PM PDT 24 Aug 16 06:15:16 PM PDT 24 1881777129 ps
T321 /workspace/coverage/default/19.rom_ctrl_alert_test.2895962136 Aug 16 06:15:04 PM PDT 24 Aug 16 06:15:08 PM PDT 24 85940624 ps
T322 /workspace/coverage/default/39.rom_ctrl_stress_all.2248384069 Aug 16 06:15:33 PM PDT 24 Aug 16 06:15:54 PM PDT 24 435080319 ps
T323 /workspace/coverage/default/4.rom_ctrl_stress_all.2465854936 Aug 16 06:14:43 PM PDT 24 Aug 16 06:14:50 PM PDT 24 89438710 ps
T324 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3897717188 Aug 16 06:14:48 PM PDT 24 Aug 16 06:14:59 PM PDT 24 261718640 ps
T325 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3752667935 Aug 16 06:15:26 PM PDT 24 Aug 16 06:16:47 PM PDT 24 8827949428 ps
T326 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3767329248 Aug 16 06:15:24 PM PDT 24 Aug 16 06:15:30 PM PDT 24 143894147 ps
T327 /workspace/coverage/default/15.rom_ctrl_alert_test.2475681216 Aug 16 06:14:54 PM PDT 24 Aug 16 06:14:58 PM PDT 24 333430881 ps
T328 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2273712291 Aug 16 06:15:42 PM PDT 24 Aug 16 06:15:48 PM PDT 24 139427799 ps
T329 /workspace/coverage/default/35.rom_ctrl_stress_all.2961706037 Aug 16 06:15:32 PM PDT 24 Aug 16 06:15:47 PM PDT 24 1309491268 ps
T330 /workspace/coverage/default/11.rom_ctrl_stress_all.929247001 Aug 16 06:14:48 PM PDT 24 Aug 16 06:15:10 PM PDT 24 1667820884 ps
T331 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1543532192 Aug 16 06:15:26 PM PDT 24 Aug 16 06:15:32 PM PDT 24 399263205 ps
T332 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1598134107 Aug 16 06:15:42 PM PDT 24 Aug 16 06:18:22 PM PDT 24 8333255007 ps
T333 /workspace/coverage/default/31.rom_ctrl_alert_test.3785927961 Aug 16 06:15:27 PM PDT 24 Aug 16 06:15:31 PM PDT 24 168654078 ps
T334 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2837386194 Aug 16 06:14:54 PM PDT 24 Aug 16 06:15:04 PM PDT 24 462304058 ps
T335 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.406237702 Aug 16 06:15:26 PM PDT 24 Aug 16 06:15:32 PM PDT 24 570425574 ps
T336 /workspace/coverage/default/10.rom_ctrl_alert_test.551039227 Aug 16 06:14:50 PM PDT 24 Aug 16 06:14:56 PM PDT 24 2042872593 ps
T337 /workspace/coverage/default/21.rom_ctrl_stress_all.3333844311 Aug 16 06:15:13 PM PDT 24 Aug 16 06:15:31 PM PDT 24 2110904989 ps
T17 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.225119201 Aug 16 06:15:22 PM PDT 24 Aug 16 06:17:49 PM PDT 24 14944359893 ps
T338 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1601195674 Aug 16 06:15:21 PM PDT 24 Aug 16 06:16:32 PM PDT 24 3569972956 ps
T339 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2004038924 Aug 16 06:14:40 PM PDT 24 Aug 16 06:14:49 PM PDT 24 178916807 ps
T340 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3185498176 Aug 16 06:15:34 PM PDT 24 Aug 16 06:15:40 PM PDT 24 563328193 ps
T341 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4218286872 Aug 16 06:15:16 PM PDT 24 Aug 16 06:16:48 PM PDT 24 10730704846 ps
T342 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3827629235 Aug 16 06:14:47 PM PDT 24 Aug 16 06:14:56 PM PDT 24 696610664 ps
T343 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2209288574 Aug 16 06:15:13 PM PDT 24 Aug 16 06:16:56 PM PDT 24 5669760496 ps
T344 /workspace/coverage/default/27.rom_ctrl_alert_test.1332250514 Aug 16 06:15:22 PM PDT 24 Aug 16 06:15:29 PM PDT 24 2337784905 ps
T345 /workspace/coverage/default/22.rom_ctrl_alert_test.2080217927 Aug 16 06:15:12 PM PDT 24 Aug 16 06:15:19 PM PDT 24 1973505969 ps
T346 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1145801016 Aug 16 06:15:24 PM PDT 24 Aug 16 06:17:46 PM PDT 24 39344275368 ps
T347 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3261537917 Aug 16 06:15:31 PM PDT 24 Aug 16 06:15:37 PM PDT 24 193383796 ps
T28 /workspace/coverage/default/4.rom_ctrl_sec_cm.3879126840 Aug 16 06:14:39 PM PDT 24 Aug 16 06:16:15 PM PDT 24 3697954769 ps
T18 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2581250564 Aug 16 06:15:34 PM PDT 24 Aug 16 06:17:11 PM PDT 24 4289964195 ps
T348 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1138056442 Aug 16 06:15:17 PM PDT 24 Aug 16 06:17:26 PM PDT 24 2672620228 ps
T349 /workspace/coverage/default/24.rom_ctrl_stress_all.1871137782 Aug 16 06:15:25 PM PDT 24 Aug 16 06:15:41 PM PDT 24 300426424 ps
T350 /workspace/coverage/default/25.rom_ctrl_alert_test.4171271424 Aug 16 06:15:22 PM PDT 24 Aug 16 06:15:26 PM PDT 24 347704909 ps
T351 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1166166692 Aug 16 06:15:33 PM PDT 24 Aug 16 06:15:43 PM PDT 24 521806778 ps
T352 /workspace/coverage/default/33.rom_ctrl_stress_all.1999190992 Aug 16 06:15:27 PM PDT 24 Aug 16 06:15:38 PM PDT 24 1079787693 ps
T353 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1746294657 Aug 16 06:15:07 PM PDT 24 Aug 16 06:15:13 PM PDT 24 550681155 ps
T354 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3563325709 Aug 16 06:15:14 PM PDT 24 Aug 16 06:17:15 PM PDT 24 13907451235 ps
T355 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3042930870 Aug 16 06:15:32 PM PDT 24 Aug 16 06:18:33 PM PDT 24 3654445935 ps
T58 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4037178972 Aug 16 04:34:03 PM PDT 24 Aug 16 04:34:11 PM PDT 24 160577641 ps
T59 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2640688224 Aug 16 04:34:10 PM PDT 24 Aug 16 04:34:14 PM PDT 24 516795659 ps
T55 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1976877899 Aug 16 04:34:14 PM PDT 24 Aug 16 04:34:51 PM PDT 24 1574852345 ps
T356 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3923022264 Aug 16 04:34:08 PM PDT 24 Aug 16 04:34:13 PM PDT 24 363514297 ps
T88 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1156021610 Aug 16 04:34:04 PM PDT 24 Aug 16 04:34:09 PM PDT 24 87930619 ps
T89 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1420962444 Aug 16 04:34:09 PM PDT 24 Aug 16 04:34:14 PM PDT 24 130781946 ps
T60 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4207658156 Aug 16 04:33:52 PM PDT 24 Aug 16 04:33:57 PM PDT 24 85964717 ps
T90 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2411587981 Aug 16 04:34:03 PM PDT 24 Aug 16 04:34:08 PM PDT 24 332681188 ps
T61 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3815686317 Aug 16 04:34:28 PM PDT 24 Aug 16 04:34:49 PM PDT 24 553685695 ps
T62 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4195866541 Aug 16 04:34:12 PM PDT 24 Aug 16 04:34:17 PM PDT 24 656280701 ps
T56 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2457146273 Aug 16 04:34:04 PM PDT 24 Aug 16 04:35:13 PM PDT 24 217990579 ps
T357 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1618013249 Aug 16 04:34:04 PM PDT 24 Aug 16 04:34:10 PM PDT 24 531461748 ps
T358 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4059392084 Aug 16 04:33:57 PM PDT 24 Aug 16 04:34:01 PM PDT 24 132072034 ps
T84 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.515874142 Aug 16 04:33:48 PM PDT 24 Aug 16 04:33:55 PM PDT 24 132087972 ps
T85 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.6848321 Aug 16 04:34:15 PM PDT 24 Aug 16 04:34:20 PM PDT 24 252431678 ps
T57 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2223925296 Aug 16 04:34:10 PM PDT 24 Aug 16 04:34:47 PM PDT 24 208149130 ps
T359 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2671950155 Aug 16 04:34:02 PM PDT 24 Aug 16 04:34:06 PM PDT 24 89163318 ps
T360 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3626117561 Aug 16 04:34:05 PM PDT 24 Aug 16 04:34:10 PM PDT 24 500133730 ps
T63 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.647687802 Aug 16 04:34:03 PM PDT 24 Aug 16 04:34:34 PM PDT 24 3134741175 ps
T361 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3123650046 Aug 16 04:33:57 PM PDT 24 Aug 16 04:34:02 PM PDT 24 832825110 ps
T94 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3689210082 Aug 16 04:34:30 PM PDT 24 Aug 16 04:35:38 PM PDT 24 924729266 ps
T86 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1876788216 Aug 16 04:34:05 PM PDT 24 Aug 16 04:34:09 PM PDT 24 335677092 ps
T362 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.399966535 Aug 16 04:33:49 PM PDT 24 Aug 16 04:33:55 PM PDT 24 128922802 ps
T64 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4167165672 Aug 16 04:33:47 PM PDT 24 Aug 16 04:33:52 PM PDT 24 126674447 ps
T95 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3351452061 Aug 16 04:34:05 PM PDT 24 Aug 16 04:35:13 PM PDT 24 395650872 ps
T363 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3088608689 Aug 16 04:34:04 PM PDT 24 Aug 16 04:34:13 PM PDT 24 129669650 ps
T364 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2645224237 Aug 16 04:33:56 PM PDT 24 Aug 16 04:34:02 PM PDT 24 754018667 ps
T96 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1377090712 Aug 16 04:34:08 PM PDT 24 Aug 16 04:35:17 PM PDT 24 290549566 ps
T65 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2784453135 Aug 16 04:33:58 PM PDT 24 Aug 16 04:34:02 PM PDT 24 171945035 ps
T66 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1660530355 Aug 16 04:34:08 PM PDT 24 Aug 16 04:34:39 PM PDT 24 3285251054 ps
T365 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3824515813 Aug 16 04:33:49 PM PDT 24 Aug 16 04:33:53 PM PDT 24 922667119 ps
T100 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2855154640 Aug 16 04:34:19 PM PDT 24 Aug 16 04:35:03 PM PDT 24 300234744 ps
T366 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1934429697 Aug 16 04:33:59 PM PDT 24 Aug 16 04:34:06 PM PDT 24 206091506 ps
T99 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3778055069 Aug 16 04:34:06 PM PDT 24 Aug 16 04:34:42 PM PDT 24 656478683 ps
T97 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3250203294 Aug 16 04:34:14 PM PDT 24 Aug 16 04:35:23 PM PDT 24 225762748 ps
T367 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1149318781 Aug 16 04:34:09 PM PDT 24 Aug 16 04:34:14 PM PDT 24 127239493 ps
T368 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2147860194 Aug 16 04:34:14 PM PDT 24 Aug 16 04:34:21 PM PDT 24 276594590 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2016302600 Aug 16 04:33:49 PM PDT 24 Aug 16 04:33:54 PM PDT 24 253589462 ps
T67 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3525265618 Aug 16 04:34:18 PM PDT 24 Aug 16 04:34:48 PM PDT 24 1509397710 ps
T370 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.245677662 Aug 16 04:34:17 PM PDT 24 Aug 16 04:34:22 PM PDT 24 508962711 ps
T101 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.539614058 Aug 16 04:34:07 PM PDT 24 Aug 16 04:34:44 PM PDT 24 209710117 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.890373221 Aug 16 04:33:49 PM PDT 24 Aug 16 04:33:54 PM PDT 24 131922952 ps
T372 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3080630327 Aug 16 04:34:10 PM PDT 24 Aug 16 04:34:16 PM PDT 24 1575525573 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.811147862 Aug 16 04:34:11 PM PDT 24 Aug 16 04:34:16 PM PDT 24 828344416 ps
T68 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1326016304 Aug 16 04:33:57 PM PDT 24 Aug 16 04:34:28 PM PDT 24 1698994362 ps
T102 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2255040087 Aug 16 04:33:55 PM PDT 24 Aug 16 04:34:35 PM PDT 24 300830500 ps
T73 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2127543002 Aug 16 04:34:13 PM PDT 24 Aug 16 04:34:43 PM PDT 24 4603086268 ps
T74 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.151596862 Aug 16 04:34:10 PM PDT 24 Aug 16 04:34:41 PM PDT 24 1630532761 ps
T374 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1814731171 Aug 16 04:34:05 PM PDT 24 Aug 16 04:34:10 PM PDT 24 127472527 ps
T87 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1641591453 Aug 16 04:34:13 PM PDT 24 Aug 16 04:34:21 PM PDT 24 141251862 ps
T375 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2669369895 Aug 16 04:33:59 PM PDT 24 Aug 16 04:34:04 PM PDT 24 504124565 ps
T376 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.326569593 Aug 16 04:34:13 PM PDT 24 Aug 16 04:34:20 PM PDT 24 534853864 ps
T377 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3405366571 Aug 16 04:34:12 PM PDT 24 Aug 16 04:34:17 PM PDT 24 133462734 ps
T378 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2484223136 Aug 16 04:34:15 PM PDT 24 Aug 16 04:34:19 PM PDT 24 351568440 ps
T75 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2014325819 Aug 16 04:34:13 PM PDT 24 Aug 16 04:34:31 PM PDT 24 1486469605 ps
T379 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2660727944 Aug 16 04:34:14 PM PDT 24 Aug 16 04:34:19 PM PDT 24 339310334 ps
T380 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1238979886 Aug 16 04:34:07 PM PDT 24 Aug 16 04:34:12 PM PDT 24 132865166 ps
T381 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1036691820 Aug 16 04:34:20 PM PDT 24 Aug 16 04:34:26 PM PDT 24 1013993905 ps
T382 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3985697236 Aug 16 04:34:13 PM PDT 24 Aug 16 04:34:20 PM PDT 24 236257155 ps
T80 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3260023092 Aug 16 04:34:05 PM PDT 24 Aug 16 04:34:36 PM PDT 24 3264872300 ps
T383 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2792650775 Aug 16 04:34:11 PM PDT 24 Aug 16 04:34:17 PM PDT 24 138758700 ps
T98 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3144388882 Aug 16 04:34:11 PM PDT 24 Aug 16 04:35:21 PM PDT 24 236678801 ps
T384 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1400474742 Aug 16 04:34:02 PM PDT 24 Aug 16 04:34:07 PM PDT 24 139877156 ps
T385 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.851268115 Aug 16 04:34:16 PM PDT 24 Aug 16 04:34:21 PM PDT 24 336475679 ps
T386 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4049406956 Aug 16 04:33:52 PM PDT 24 Aug 16 04:33:59 PM PDT 24 134199337 ps
T387 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1709056398 Aug 16 04:33:46 PM PDT 24 Aug 16 04:33:52 PM PDT 24 533607823 ps
T388 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3797334449 Aug 16 04:33:59 PM PDT 24 Aug 16 04:34:04 PM PDT 24 88147184 ps
T389 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2991924969 Aug 16 04:34:20 PM PDT 24 Aug 16 04:34:26 PM PDT 24 365895835 ps
T390 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1853135299 Aug 16 04:34:10 PM PDT 24 Aug 16 04:34:14 PM PDT 24 271107890 ps
T391 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3181369277 Aug 16 04:34:06 PM PDT 24 Aug 16 04:34:10 PM PDT 24 919523951 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.493893526 Aug 16 04:33:59 PM PDT 24 Aug 16 04:34:20 PM PDT 24 533954607 ps
T393 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2687264898 Aug 16 04:34:12 PM PDT 24 Aug 16 04:34:17 PM PDT 24 172705351 ps
T394 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.906280897 Aug 16 04:34:17 PM PDT 24 Aug 16 04:34:22 PM PDT 24 126150652 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3465502055 Aug 16 04:33:59 PM PDT 24 Aug 16 04:34:04 PM PDT 24 126602956 ps
T396 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.687469832 Aug 16 04:34:18 PM PDT 24 Aug 16 04:34:27 PM PDT 24 1029766530 ps
T397 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3299717435 Aug 16 04:34:15 PM PDT 24 Aug 16 04:35:22 PM PDT 24 521367490 ps
T398 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.378178193 Aug 16 04:34:11 PM PDT 24 Aug 16 04:34:20 PM PDT 24 258696931 ps
T107 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1539342207 Aug 16 04:34:10 PM PDT 24 Aug 16 04:34:41 PM PDT 24 790566765 ps
T399 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.817159796 Aug 16 04:33:50 PM PDT 24 Aug 16 04:34:26 PM PDT 24 680423193 ps
T400 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3896217342 Aug 16 04:34:20 PM PDT 24 Aug 16 04:34:29 PM PDT 24 588213415 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.722965457 Aug 16 04:33:45 PM PDT 24 Aug 16 04:34:23 PM PDT 24 846983992 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2528921551 Aug 16 04:34:03 PM PDT 24 Aug 16 04:34:07 PM PDT 24 288821249 ps
T403 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.518240264 Aug 16 04:33:58 PM PDT 24 Aug 16 04:34:02 PM PDT 24 273714626 ps
T79 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.215882910 Aug 16 04:34:13 PM PDT 24 Aug 16 04:34:17 PM PDT 24 1180093432 ps
T82 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1372023619 Aug 16 04:33:56 PM PDT 24 Aug 16 04:34:03 PM PDT 24 688010543 ps
T404 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1823962522 Aug 16 04:34:09 PM PDT 24 Aug 16 04:34:18 PM PDT 24 569832902 ps
T405 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1839366322 Aug 16 04:34:19 PM PDT 24 Aug 16 04:34:56 PM PDT 24 167762832 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3980238838 Aug 16 04:34:11 PM PDT 24 Aug 16 04:34:29 PM PDT 24 373365507 ps
T407 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.731559067 Aug 16 04:34:03 PM PDT 24 Aug 16 04:34:10 PM PDT 24 498079434 ps
T408 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1261989402 Aug 16 04:33:57 PM PDT 24 Aug 16 04:34:06 PM PDT 24 171190242 ps
T409 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.634224403 Aug 16 04:34:17 PM PDT 24 Aug 16 04:34:21 PM PDT 24 171309750 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3707520020 Aug 16 04:33:45 PM PDT 24 Aug 16 04:33:52 PM PDT 24 516838073 ps
T411 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1659685512 Aug 16 04:34:14 PM PDT 24 Aug 16 04:34:18 PM PDT 24 172379847 ps
T412 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3946664732 Aug 16 04:34:17 PM PDT 24 Aug 16 04:34:24 PM PDT 24 129928440 ps
T413 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1914682013 Aug 16 04:33:59 PM PDT 24 Aug 16 04:34:04 PM PDT 24 98914988 ps
T76 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3355888087 Aug 16 04:33:55 PM PDT 24 Aug 16 04:34:27 PM PDT 24 8745009474 ps
T414 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3560113183 Aug 16 04:34:04 PM PDT 24 Aug 16 04:34:37 PM PDT 24 11095191324 ps
T415 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1484935361 Aug 16 04:33:59 PM PDT 24 Aug 16 04:34:05 PM PDT 24 345654961 ps
T416 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1689278712 Aug 16 04:33:59 PM PDT 24 Aug 16 04:34:04 PM PDT 24 172041560 ps
T417 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2292411984 Aug 16 04:34:14 PM PDT 24 Aug 16 04:34:19 PM PDT 24 130684824 ps
T418 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3836086089 Aug 16 04:34:04 PM PDT 24 Aug 16 04:34:09 PM PDT 24 393960397 ps
T419 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3352065815 Aug 16 04:34:19 PM PDT 24 Aug 16 04:34:23 PM PDT 24 336840944 ps
T420 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3821941156 Aug 16 04:34:13 PM PDT 24 Aug 16 04:34:18 PM PDT 24 134544212 ps
T421 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4226973175 Aug 16 04:33:46 PM PDT 24 Aug 16 04:33:56 PM PDT 24 568246080 ps
T422 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.212740151 Aug 16 04:34:09 PM PDT 24 Aug 16 04:35:16 PM PDT 24 967171313 ps
T423 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3394337115 Aug 16 04:34:11 PM PDT 24 Aug 16 04:34:16 PM PDT 24 157551597 ps
T424 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2191269763 Aug 16 04:34:34 PM PDT 24 Aug 16 04:34:38 PM PDT 24 184864868 ps
T425 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2621072575 Aug 16 04:34:14 PM PDT 24 Aug 16 04:34:18 PM PDT 24 346743604 ps
T426 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3756504207 Aug 16 04:34:05 PM PDT 24 Aug 16 04:34:13 PM PDT 24 89053827 ps
T77 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.555570277 Aug 16 04:34:20 PM PDT 24 Aug 16 04:34:25 PM PDT 24 131530571 ps
T427 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.415512287 Aug 16 04:34:13 PM PDT 24 Aug 16 04:34:18 PM PDT 24 261352444 ps
T428 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2642296012 Aug 16 04:34:10 PM PDT 24 Aug 16 04:34:15 PM PDT 24 93048081 ps
T429 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.456165545 Aug 16 04:34:08 PM PDT 24 Aug 16 04:34:16 PM PDT 24 140088144 ps
T81 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2384180072 Aug 16 04:34:10 PM PDT 24 Aug 16 04:34:37 PM PDT 24 1132501882 ps
T430 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3444053309 Aug 16 04:34:10 PM PDT 24 Aug 16 04:34:16 PM PDT 24 538857766 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.351984705 Aug 16 04:34:06 PM PDT 24 Aug 16 04:34:12 PM PDT 24 176110193 ps
T432 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2249138417 Aug 16 04:34:12 PM PDT 24 Aug 16 04:34:17 PM PDT 24 185912448 ps
T433 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2533851820 Aug 16 04:33:57 PM PDT 24 Aug 16 04:34:03 PM PDT 24 132814508 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1407957318 Aug 16 04:34:06 PM PDT 24 Aug 16 04:34:27 PM PDT 24 4021663252 ps
T434 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.52323521 Aug 16 04:34:25 PM PDT 24 Aug 16 04:34:52 PM PDT 24 3366846658 ps
T435 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3642474563 Aug 16 04:34:09 PM PDT 24 Aug 16 04:35:28 PM PDT 24 763108762 ps
T436 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2182443127 Aug 16 04:33:58 PM PDT 24 Aug 16 04:34:03 PM PDT 24 905570388 ps
T78 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2964338759 Aug 16 04:34:08 PM PDT 24 Aug 16 04:34:34 PM PDT 24 1101482409 ps
T437 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2634902957 Aug 16 04:34:17 PM PDT 24 Aug 16 04:34:23 PM PDT 24 98254862 ps
T438 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1051015452 Aug 16 04:33:56 PM PDT 24 Aug 16 04:34:04 PM PDT 24 357882850 ps
T439 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.880689741 Aug 16 04:34:09 PM PDT 24 Aug 16 04:34:46 PM PDT 24 629140612 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1037744814 Aug 16 04:34:05 PM PDT 24 Aug 16 04:34:11 PM PDT 24 92236610 ps
T441 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1571977038 Aug 16 04:34:16 PM PDT 24 Aug 16 04:34:23 PM PDT 24 515054680 ps
T442 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1842858419 Aug 16 04:33:51 PM PDT 24 Aug 16 04:33:56 PM PDT 24 121355031 ps
T443 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2577113086 Aug 16 04:33:46 PM PDT 24 Aug 16 04:33:53 PM PDT 24 509783122 ps
T444 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.116172042 Aug 16 04:34:07 PM PDT 24 Aug 16 04:34:12 PM PDT 24 131391328 ps
T445 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4281648639 Aug 16 04:33:55 PM PDT 24 Aug 16 04:33:59 PM PDT 24 168916531 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2766644036 Aug 16 04:33:43 PM PDT 24 Aug 16 04:33:54 PM PDT 24 154306083 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.897935758 Aug 16 04:33:57 PM PDT 24 Aug 16 04:34:02 PM PDT 24 2077306923 ps
T448 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1474500136 Aug 16 04:34:12 PM PDT 24 Aug 16 04:34:43 PM PDT 24 3571223520 ps
T449 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3280484151 Aug 16 04:33:57 PM PDT 24 Aug 16 04:34:07 PM PDT 24 127401757 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2833073641 Aug 16 04:33:56 PM PDT 24 Aug 16 04:34:01 PM PDT 24 127699705 ps
T451 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3185531088 Aug 16 04:34:10 PM PDT 24 Aug 16 04:34:42 PM PDT 24 3277233690 ps
T452 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.721291515 Aug 16 04:34:26 PM PDT 24 Aug 16 04:35:06 PM PDT 24 639314601 ps
T453 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4261937517 Aug 16 04:34:00 PM PDT 24 Aug 16 04:34:08 PM PDT 24 292332744 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1619154566 Aug 16 04:33:54 PM PDT 24 Aug 16 04:33:59 PM PDT 24 567918998 ps
T455 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1599388430 Aug 16 04:34:10 PM PDT 24 Aug 16 04:34:19 PM PDT 24 603051425 ps
T456 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.842083309 Aug 16 04:34:12 PM PDT 24 Aug 16 04:34:16 PM PDT 24 253601443 ps

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.536360263
Short name T9
Test name
Test status
Simulation time 1791423906 ps
CPU time 119.06 seconds
Started Aug 16 06:15:36 PM PDT 24
Finished Aug 16 06:17:35 PM PDT 24
Peak memory 219252 kb
Host smart-e3f658ef-d21f-40bf-8513-7d3c5c945ea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536360263 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.536360263
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1789277519
Short name T20
Test name
Test status
Simulation time 7910217555 ps
CPU time 106.33 seconds
Started Aug 16 06:15:32 PM PDT 24
Finished Aug 16 06:17:18 PM PDT 24
Peak memory 233620 kb
Host smart-13914aff-ce97-4828-b4b4-9f24718c8fb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789277519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1789277519
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1014453212
Short name T13
Test name
Test status
Simulation time 3226077034 ps
CPU time 133.24 seconds
Started Aug 16 06:14:45 PM PDT 24
Finished Aug 16 06:16:59 PM PDT 24
Peak memory 223884 kb
Host smart-1ad1a91b-d779-4d6e-8cd1-16b03e3f2a72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014453212 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1014453212
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1017163370
Short name T25
Test name
Test status
Simulation time 255049999 ps
CPU time 11.03 seconds
Started Aug 16 06:14:54 PM PDT 24
Finished Aug 16 06:15:05 PM PDT 24
Peak memory 211128 kb
Host smart-4d7c0ad2-c3fb-4cd1-acea-cddeb145a485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017163370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1017163370
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3351452061
Short name T95
Test name
Test status
Simulation time 395650872 ps
CPU time 67.84 seconds
Started Aug 16 04:34:05 PM PDT 24
Finished Aug 16 04:35:13 PM PDT 24
Peak memory 212984 kb
Host smart-3c8f5183-a894-45bd-87dc-d62350482d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351452061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3351452061
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3586593200
Short name T21
Test name
Test status
Simulation time 848632846 ps
CPU time 99.01 seconds
Started Aug 16 06:14:33 PM PDT 24
Finished Aug 16 06:16:12 PM PDT 24
Peak memory 236372 kb
Host smart-bef480be-6d72-4f4e-b752-08db0837dfca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586593200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3586593200
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.148116276
Short name T35
Test name
Test status
Simulation time 13523531180 ps
CPU time 100.1 seconds
Started Aug 16 06:15:05 PM PDT 24
Finished Aug 16 06:16:45 PM PDT 24
Peak memory 223184 kb
Host smart-9a71f885-c802-4065-8ec6-bf649af595a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148116276 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.148116276
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4195866541
Short name T62
Test name
Test status
Simulation time 656280701 ps
CPU time 4.78 seconds
Started Aug 16 04:34:12 PM PDT 24
Finished Aug 16 04:34:17 PM PDT 24
Peak memory 211268 kb
Host smart-23db10ef-71f9-4a7d-9731-6f34f5339a0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195866541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.4195866541
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2851946945
Short name T1
Test name
Test status
Simulation time 462164872 ps
CPU time 3.97 seconds
Started Aug 16 06:15:22 PM PDT 24
Finished Aug 16 06:15:26 PM PDT 24
Peak memory 211036 kb
Host smart-9b92e054-90cb-4cd4-a9b3-95886b55c873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851946945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2851946945
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3250203294
Short name T97
Test name
Test status
Simulation time 225762748 ps
CPU time 68.8 seconds
Started Aug 16 04:34:14 PM PDT 24
Finished Aug 16 04:35:23 PM PDT 24
Peak memory 219420 kb
Host smart-1ac7e6c6-f7c2-4fc3-ab48-cd972cf5bf4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250203294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3250203294
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2581250564
Short name T18
Test name
Test status
Simulation time 4289964195 ps
CPU time 97 seconds
Started Aug 16 06:15:34 PM PDT 24
Finished Aug 16 06:17:11 PM PDT 24
Peak memory 227660 kb
Host smart-2535b5f1-b2c2-4ea9-9032-4f8529f57b4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581250564 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2581250564
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.277702393
Short name T10
Test name
Test status
Simulation time 1658340294 ps
CPU time 80.67 seconds
Started Aug 16 06:14:48 PM PDT 24
Finished Aug 16 06:16:09 PM PDT 24
Peak memory 236428 kb
Host smart-a4141218-6314-4304-99c2-a7b1583f8aad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277702393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.277702393
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.698984263
Short name T130
Test name
Test status
Simulation time 168648281 ps
CPU time 9.01 seconds
Started Aug 16 06:14:51 PM PDT 24
Finished Aug 16 06:15:00 PM PDT 24
Peak memory 211536 kb
Host smart-e0289483-9e8a-4b37-bd13-b86aabb20dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698984263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.698984263
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.151596862
Short name T74
Test name
Test status
Simulation time 1630532761 ps
CPU time 30.65 seconds
Started Aug 16 04:34:10 PM PDT 24
Finished Aug 16 04:34:41 PM PDT 24
Peak memory 211252 kb
Host smart-a36bdfd4-a50e-4f5b-86f7-c6dca07eef31
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151596862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.151596862
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3560907058
Short name T91
Test name
Test status
Simulation time 569575297 ps
CPU time 8.26 seconds
Started Aug 16 06:15:42 PM PDT 24
Finished Aug 16 06:15:50 PM PDT 24
Peak memory 211096 kb
Host smart-3c113ce3-d074-465f-8614-dbe425da5188
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3560907058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3560907058
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2223925296
Short name T57
Test name
Test status
Simulation time 208149130 ps
CPU time 37.18 seconds
Started Aug 16 04:34:10 PM PDT 24
Finished Aug 16 04:34:47 PM PDT 24
Peak memory 211972 kb
Host smart-93921c89-d1d8-40b7-8e16-b71e7f8bdcd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223925296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2223925296
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3144388882
Short name T98
Test name
Test status
Simulation time 236678801 ps
CPU time 68.77 seconds
Started Aug 16 04:34:11 PM PDT 24
Finished Aug 16 04:35:21 PM PDT 24
Peak memory 213024 kb
Host smart-cecdcfe4-66a1-425d-bac6-3a14a98925f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144388882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3144388882
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1872963922
Short name T29
Test name
Test status
Simulation time 282797487 ps
CPU time 15.62 seconds
Started Aug 16 06:14:42 PM PDT 24
Finished Aug 16 06:14:58 PM PDT 24
Peak memory 214068 kb
Host smart-fe9c720a-d147-40c4-858e-eb9ecded59c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872963922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1872963922
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.225119201
Short name T17
Test name
Test status
Simulation time 14944359893 ps
CPU time 147.04 seconds
Started Aug 16 06:15:22 PM PDT 24
Finished Aug 16 06:17:49 PM PDT 24
Peak memory 224364 kb
Host smart-d755794b-1169-4094-ac64-d7a942d2cfcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225119201 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.225119201
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1842858419
Short name T442
Test name
Test status
Simulation time 121355031 ps
CPU time 4.03 seconds
Started Aug 16 04:33:51 PM PDT 24
Finished Aug 16 04:33:56 PM PDT 24
Peak memory 211316 kb
Host smart-faea471e-eb2a-4969-96af-d4967ba74834
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842858419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1842858419
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.399966535
Short name T362
Test name
Test status
Simulation time 128922802 ps
CPU time 5.13 seconds
Started Aug 16 04:33:49 PM PDT 24
Finished Aug 16 04:33:55 PM PDT 24
Peak memory 211288 kb
Host smart-835c06f5-3693-43c6-bbaf-25c70759d2b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399966535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.399966535
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4049406956
Short name T386
Test name
Test status
Simulation time 134199337 ps
CPU time 6.49 seconds
Started Aug 16 04:33:52 PM PDT 24
Finished Aug 16 04:33:59 PM PDT 24
Peak memory 211304 kb
Host smart-b8172a7c-b658-4857-b5a3-d92ef67f755b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049406956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4049406956
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1709056398
Short name T387
Test name
Test status
Simulation time 533607823 ps
CPU time 5.47 seconds
Started Aug 16 04:33:46 PM PDT 24
Finished Aug 16 04:33:52 PM PDT 24
Peak memory 219536 kb
Host smart-81e8be24-0414-4871-8fba-14a52c33d175
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709056398 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1709056398
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2784453135
Short name T65
Test name
Test status
Simulation time 171945035 ps
CPU time 3.93 seconds
Started Aug 16 04:33:58 PM PDT 24
Finished Aug 16 04:34:02 PM PDT 24
Peak memory 211292 kb
Host smart-3496aee9-41e7-494e-9baf-a774fd38d115
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784453135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2784453135
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2016302600
Short name T369
Test name
Test status
Simulation time 253589462 ps
CPU time 4.75 seconds
Started Aug 16 04:33:49 PM PDT 24
Finished Aug 16 04:33:54 PM PDT 24
Peak memory 211192 kb
Host smart-226bb482-da0e-412d-a7e5-b90dccb8c1ea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016302600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2016302600
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1619154566
Short name T454
Test name
Test status
Simulation time 567918998 ps
CPU time 4.7 seconds
Started Aug 16 04:33:54 PM PDT 24
Finished Aug 16 04:33:59 PM PDT 24
Peak memory 211244 kb
Host smart-64c5f576-6472-47b0-9f35-c0858f96c97f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619154566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1619154566
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.493893526
Short name T392
Test name
Test status
Simulation time 533954607 ps
CPU time 21.29 seconds
Started Aug 16 04:33:59 PM PDT 24
Finished Aug 16 04:34:20 PM PDT 24
Peak memory 211324 kb
Host smart-6eb970d3-b163-4c9b-99f7-39a8227d1935
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493893526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.493893526
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1689278712
Short name T416
Test name
Test status
Simulation time 172041560 ps
CPU time 4.26 seconds
Started Aug 16 04:33:59 PM PDT 24
Finished Aug 16 04:34:04 PM PDT 24
Peak memory 218532 kb
Host smart-5fe70cf3-7f5c-4e8b-8aac-4058d55ca689
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689278712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1689278712
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3280484151
Short name T449
Test name
Test status
Simulation time 127401757 ps
CPU time 9.57 seconds
Started Aug 16 04:33:57 PM PDT 24
Finished Aug 16 04:34:07 PM PDT 24
Peak memory 216996 kb
Host smart-ddeafa1e-d31c-4224-8c30-eabb848dfaaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280484151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3280484151
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2255040087
Short name T102
Test name
Test status
Simulation time 300830500 ps
CPU time 39.44 seconds
Started Aug 16 04:33:55 PM PDT 24
Finished Aug 16 04:34:35 PM PDT 24
Peak memory 214060 kb
Host smart-47a596e0-8d73-4800-996b-6cb2833fea21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255040087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2255040087
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1372023619
Short name T82
Test name
Test status
Simulation time 688010543 ps
CPU time 6.51 seconds
Started Aug 16 04:33:56 PM PDT 24
Finished Aug 16 04:34:03 PM PDT 24
Peak memory 217936 kb
Host smart-37aa127d-13a0-4456-9d17-e3d889feb182
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372023619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1372023619
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.890373221
Short name T371
Test name
Test status
Simulation time 131922952 ps
CPU time 5.15 seconds
Started Aug 16 04:33:49 PM PDT 24
Finished Aug 16 04:33:54 PM PDT 24
Peak memory 211284 kb
Host smart-e3271a0f-0927-41cb-ab88-20bbf38e2074
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890373221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.890373221
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4037178972
Short name T58
Test name
Test status
Simulation time 160577641 ps
CPU time 8.58 seconds
Started Aug 16 04:34:03 PM PDT 24
Finished Aug 16 04:34:11 PM PDT 24
Peak memory 211268 kb
Host smart-d8f85bec-11f9-4053-adf5-a320bf70b688
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037178972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4037178972
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1914682013
Short name T413
Test name
Test status
Simulation time 98914988 ps
CPU time 5.24 seconds
Started Aug 16 04:33:59 PM PDT 24
Finished Aug 16 04:34:04 PM PDT 24
Peak memory 216164 kb
Host smart-450bf500-7463-4795-af69-2dfd4729b54d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914682013 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1914682013
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4207658156
Short name T60
Test name
Test status
Simulation time 85964717 ps
CPU time 4.06 seconds
Started Aug 16 04:33:52 PM PDT 24
Finished Aug 16 04:33:57 PM PDT 24
Peak memory 211260 kb
Host smart-26d9490a-1c26-446c-9d67-e4dce2e2bd6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207658156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4207658156
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3352065815
Short name T419
Test name
Test status
Simulation time 336840944 ps
CPU time 3.92 seconds
Started Aug 16 04:34:19 PM PDT 24
Finished Aug 16 04:34:23 PM PDT 24
Peak memory 211216 kb
Host smart-76927886-d0a6-47c2-9eac-6a6657a61763
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352065815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3352065815
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2577113086
Short name T443
Test name
Test status
Simulation time 509783122 ps
CPU time 6.48 seconds
Started Aug 16 04:33:46 PM PDT 24
Finished Aug 16 04:33:53 PM PDT 24
Peak memory 211204 kb
Host smart-5bfb5791-f44d-4be2-8186-83f38b17d36b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577113086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2577113086
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3355888087
Short name T76
Test name
Test status
Simulation time 8745009474 ps
CPU time 31.69 seconds
Started Aug 16 04:33:55 PM PDT 24
Finished Aug 16 04:34:27 PM PDT 24
Peak memory 211412 kb
Host smart-d98bb1e9-6313-4147-800d-fd5fe5694370
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355888087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3355888087
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4167165672
Short name T64
Test name
Test status
Simulation time 126674447 ps
CPU time 4.88 seconds
Started Aug 16 04:33:47 PM PDT 24
Finished Aug 16 04:33:52 PM PDT 24
Peak memory 218640 kb
Host smart-2ce6b742-3d5a-413d-add0-b93135d5a409
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167165672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.4167165672
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2766644036
Short name T446
Test name
Test status
Simulation time 154306083 ps
CPU time 10.12 seconds
Started Aug 16 04:33:43 PM PDT 24
Finished Aug 16 04:33:54 PM PDT 24
Peak memory 216384 kb
Host smart-ee2c71a9-9ea0-40b3-8f6f-3bca9f65ef54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766644036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2766644036
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.722965457
Short name T401
Test name
Test status
Simulation time 846983992 ps
CPU time 37.47 seconds
Started Aug 16 04:33:45 PM PDT 24
Finished Aug 16 04:34:23 PM PDT 24
Peak memory 212856 kb
Host smart-b625f315-47a0-4f49-b856-aca190de56c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722965457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.722965457
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1238979886
Short name T380
Test name
Test status
Simulation time 132865166 ps
CPU time 5.08 seconds
Started Aug 16 04:34:07 PM PDT 24
Finished Aug 16 04:34:12 PM PDT 24
Peak memory 214484 kb
Host smart-db198256-ac68-419c-af4f-10b239a1e1d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238979886 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1238979886
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.555570277
Short name T77
Test name
Test status
Simulation time 131530571 ps
CPU time 5.03 seconds
Started Aug 16 04:34:20 PM PDT 24
Finished Aug 16 04:34:25 PM PDT 24
Peak memory 211300 kb
Host smart-84ecc31b-ccda-447d-95e7-b542492950ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555570277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.555570277
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1539342207
Short name T107
Test name
Test status
Simulation time 790566765 ps
CPU time 31.14 seconds
Started Aug 16 04:34:10 PM PDT 24
Finished Aug 16 04:34:41 PM PDT 24
Peak memory 211252 kb
Host smart-0c1ee302-bb41-46b8-ab9c-14341eb1590b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539342207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1539342207
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2292411984
Short name T417
Test name
Test status
Simulation time 130684824 ps
CPU time 4.85 seconds
Started Aug 16 04:34:14 PM PDT 24
Finished Aug 16 04:34:19 PM PDT 24
Peak memory 211328 kb
Host smart-f8deb6e6-f38e-4c30-9761-a0ac114f23b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292411984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2292411984
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.731559067
Short name T407
Test name
Test status
Simulation time 498079434 ps
CPU time 6.83 seconds
Started Aug 16 04:34:03 PM PDT 24
Finished Aug 16 04:34:10 PM PDT 24
Peak memory 216176 kb
Host smart-89fd2625-6940-4095-916d-ee5435baae1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731559067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.731559067
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2249138417
Short name T432
Test name
Test status
Simulation time 185912448 ps
CPU time 4.74 seconds
Started Aug 16 04:34:12 PM PDT 24
Finished Aug 16 04:34:17 PM PDT 24
Peak memory 219556 kb
Host smart-fd19fac1-49a1-4603-ae19-b7a1ad441f37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249138417 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2249138417
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3181369277
Short name T391
Test name
Test status
Simulation time 919523951 ps
CPU time 3.83 seconds
Started Aug 16 04:34:06 PM PDT 24
Finished Aug 16 04:34:10 PM PDT 24
Peak memory 219420 kb
Host smart-b9e8bc0b-cce8-4c24-bc9c-c76b457ba153
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181369277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3181369277
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3560113183
Short name T414
Test name
Test status
Simulation time 11095191324 ps
CPU time 28.18 seconds
Started Aug 16 04:34:04 PM PDT 24
Finished Aug 16 04:34:37 PM PDT 24
Peak memory 211436 kb
Host smart-531dac17-ce25-4ebc-b6f0-a88e40010e4c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560113183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3560113183
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2634902957
Short name T437
Test name
Test status
Simulation time 98254862 ps
CPU time 5.79 seconds
Started Aug 16 04:34:17 PM PDT 24
Finished Aug 16 04:34:23 PM PDT 24
Peak memory 211340 kb
Host smart-1699b64b-5bb8-4d1e-9ccd-3e2279a8adcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634902957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2634902957
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1823962522
Short name T404
Test name
Test status
Simulation time 569832902 ps
CPU time 8.74 seconds
Started Aug 16 04:34:09 PM PDT 24
Finished Aug 16 04:34:18 PM PDT 24
Peak memory 219532 kb
Host smart-bd7519d3-8061-4e62-ab84-1b780369d597
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823962522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1823962522
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2792650775
Short name T383
Test name
Test status
Simulation time 138758700 ps
CPU time 5.19 seconds
Started Aug 16 04:34:11 PM PDT 24
Finished Aug 16 04:34:17 PM PDT 24
Peak memory 214300 kb
Host smart-90d3d61a-6675-4a8d-999e-4039e35f061d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792650775 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2792650775
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2964338759
Short name T78
Test name
Test status
Simulation time 1101482409 ps
CPU time 25.87 seconds
Started Aug 16 04:34:08 PM PDT 24
Finished Aug 16 04:34:34 PM PDT 24
Peak memory 211396 kb
Host smart-0f6d33f5-fc85-4c9a-aca9-0a927b042b4c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964338759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2964338759
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1876788216
Short name T86
Test name
Test status
Simulation time 335677092 ps
CPU time 3.98 seconds
Started Aug 16 04:34:05 PM PDT 24
Finished Aug 16 04:34:09 PM PDT 24
Peak memory 218392 kb
Host smart-e2e3ea04-e331-463e-85c5-bc1c1178557f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876788216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1876788216
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3985697236
Short name T382
Test name
Test status
Simulation time 236257155 ps
CPU time 7.06 seconds
Started Aug 16 04:34:13 PM PDT 24
Finished Aug 16 04:34:20 PM PDT 24
Peak memory 216460 kb
Host smart-15b3f73c-1282-4b1b-8163-7ff0ed572d07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985697236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3985697236
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.880689741
Short name T439
Test name
Test status
Simulation time 629140612 ps
CPU time 36.25 seconds
Started Aug 16 04:34:09 PM PDT 24
Finished Aug 16 04:34:46 PM PDT 24
Peak memory 211996 kb
Host smart-9bb9e65c-f158-4410-a848-65e5b0d50b91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880689741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.880689741
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3394337115
Short name T423
Test name
Test status
Simulation time 157551597 ps
CPU time 5.66 seconds
Started Aug 16 04:34:11 PM PDT 24
Finished Aug 16 04:34:16 PM PDT 24
Peak memory 216440 kb
Host smart-39f14127-013d-4f11-b396-5ef71b27ce33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394337115 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3394337115
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1149318781
Short name T367
Test name
Test status
Simulation time 127239493 ps
CPU time 4.82 seconds
Started Aug 16 04:34:09 PM PDT 24
Finished Aug 16 04:34:14 PM PDT 24
Peak memory 211316 kb
Host smart-ef8dcd88-b8bd-45d8-99a1-943dd7be7137
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149318781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1149318781
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2384180072
Short name T81
Test name
Test status
Simulation time 1132501882 ps
CPU time 26.26 seconds
Started Aug 16 04:34:10 PM PDT 24
Finished Aug 16 04:34:37 PM PDT 24
Peak memory 211324 kb
Host smart-67f46761-93c7-49b8-ba84-6bf35100a2d4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384180072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2384180072
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2640688224
Short name T59
Test name
Test status
Simulation time 516795659 ps
CPU time 4.7 seconds
Started Aug 16 04:34:10 PM PDT 24
Finished Aug 16 04:34:14 PM PDT 24
Peak memory 218712 kb
Host smart-84c18502-4b0c-4743-a651-dd38a266d3af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640688224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2640688224
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1599388430
Short name T455
Test name
Test status
Simulation time 603051425 ps
CPU time 9.25 seconds
Started Aug 16 04:34:10 PM PDT 24
Finished Aug 16 04:34:19 PM PDT 24
Peak memory 219492 kb
Host smart-830c11f4-74b1-4427-b167-8f5c01088b30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599388430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1599388430
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2855154640
Short name T100
Test name
Test status
Simulation time 300234744 ps
CPU time 38.54 seconds
Started Aug 16 04:34:19 PM PDT 24
Finished Aug 16 04:35:03 PM PDT 24
Peak memory 213016 kb
Host smart-8607fef4-b1e9-4af7-bdf9-80f41a4bc97a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855154640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2855154640
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2991924969
Short name T389
Test name
Test status
Simulation time 365895835 ps
CPU time 4.92 seconds
Started Aug 16 04:34:20 PM PDT 24
Finished Aug 16 04:34:26 PM PDT 24
Peak memory 219616 kb
Host smart-7fd239ce-8238-47e8-81ce-d2c3146dbbd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991924969 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2991924969
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3821941156
Short name T420
Test name
Test status
Simulation time 134544212 ps
CPU time 4.79 seconds
Started Aug 16 04:34:13 PM PDT 24
Finished Aug 16 04:34:18 PM PDT 24
Peak memory 211288 kb
Host smart-0daeed2e-d1f0-45ab-9ee6-9c07c4ea5f16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821941156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3821941156
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3525265618
Short name T67
Test name
Test status
Simulation time 1509397710 ps
CPU time 29.93 seconds
Started Aug 16 04:34:18 PM PDT 24
Finished Aug 16 04:34:48 PM PDT 24
Peak memory 211260 kb
Host smart-1b1a7646-f59f-48ad-af20-7ac27844774b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525265618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3525265618
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.6848321
Short name T85
Test name
Test status
Simulation time 252431678 ps
CPU time 4.81 seconds
Started Aug 16 04:34:15 PM PDT 24
Finished Aug 16 04:34:20 PM PDT 24
Peak memory 211272 kb
Host smart-57c7077c-6b0c-46fe-80d9-44e38d85697d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6848321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctr
l_same_csr_outstanding.6848321
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.456165545
Short name T429
Test name
Test status
Simulation time 140088144 ps
CPU time 8.43 seconds
Started Aug 16 04:34:08 PM PDT 24
Finished Aug 16 04:34:16 PM PDT 24
Peak memory 216296 kb
Host smart-08478893-8b44-4537-9103-568ab076d44f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456165545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.456165545
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1571977038
Short name T441
Test name
Test status
Simulation time 515054680 ps
CPU time 6.62 seconds
Started Aug 16 04:34:16 PM PDT 24
Finished Aug 16 04:34:23 PM PDT 24
Peak memory 213252 kb
Host smart-f77e218f-d0d1-44f0-aad2-67a3af38d617
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571977038 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1571977038
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.415512287
Short name T427
Test name
Test status
Simulation time 261352444 ps
CPU time 4.77 seconds
Started Aug 16 04:34:13 PM PDT 24
Finished Aug 16 04:34:18 PM PDT 24
Peak memory 218340 kb
Host smart-8d161faa-0232-45ae-88c5-b7ecdc3f36e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415512287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.415512287
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3815686317
Short name T61
Test name
Test status
Simulation time 553685695 ps
CPU time 20.94 seconds
Started Aug 16 04:34:28 PM PDT 24
Finished Aug 16 04:34:49 PM PDT 24
Peak memory 211272 kb
Host smart-54a2c746-d18b-4d6d-ab0d-9b310635b45d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815686317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3815686317
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2660727944
Short name T379
Test name
Test status
Simulation time 339310334 ps
CPU time 5.04 seconds
Started Aug 16 04:34:14 PM PDT 24
Finished Aug 16 04:34:19 PM PDT 24
Peak memory 211300 kb
Host smart-de44b30b-5af7-4d8d-a017-68fecb87cbd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660727944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2660727944
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3689210082
Short name T94
Test name
Test status
Simulation time 924729266 ps
CPU time 67.6 seconds
Started Aug 16 04:34:30 PM PDT 24
Finished Aug 16 04:35:38 PM PDT 24
Peak memory 213904 kb
Host smart-ed37feaa-7e94-450c-86d2-1ae038e47232
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689210082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3689210082
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1036691820
Short name T381
Test name
Test status
Simulation time 1013993905 ps
CPU time 5.72 seconds
Started Aug 16 04:34:20 PM PDT 24
Finished Aug 16 04:34:26 PM PDT 24
Peak memory 219532 kb
Host smart-5a1086db-cd64-4719-9ab6-e0c6d2658969
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036691820 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1036691820
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.634224403
Short name T409
Test name
Test status
Simulation time 171309750 ps
CPU time 4 seconds
Started Aug 16 04:34:17 PM PDT 24
Finished Aug 16 04:34:21 PM PDT 24
Peak memory 211268 kb
Host smart-a6457f40-e652-40c5-a17a-7905ece49e29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634224403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.634224403
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2014325819
Short name T75
Test name
Test status
Simulation time 1486469605 ps
CPU time 17.95 seconds
Started Aug 16 04:34:13 PM PDT 24
Finished Aug 16 04:34:31 PM PDT 24
Peak memory 211248 kb
Host smart-9aba0d08-1326-47f2-b486-a5e94598dde2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014325819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2014325819
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.851268115
Short name T385
Test name
Test status
Simulation time 336475679 ps
CPU time 4.16 seconds
Started Aug 16 04:34:16 PM PDT 24
Finished Aug 16 04:34:21 PM PDT 24
Peak memory 211328 kb
Host smart-c743cc7d-6a07-4174-a292-96ad4b3ac367
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851268115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.851268115
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3946664732
Short name T412
Test name
Test status
Simulation time 129928440 ps
CPU time 7.1 seconds
Started Aug 16 04:34:17 PM PDT 24
Finished Aug 16 04:34:24 PM PDT 24
Peak memory 219464 kb
Host smart-4c99daf0-6f2c-40d4-94cf-9427a1c7b643
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946664732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3946664732
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1839366322
Short name T405
Test name
Test status
Simulation time 167762832 ps
CPU time 36.81 seconds
Started Aug 16 04:34:19 PM PDT 24
Finished Aug 16 04:34:56 PM PDT 24
Peak memory 212572 kb
Host smart-a12f8d5c-fbf6-401b-9a36-41f2ffecfd14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839366322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1839366322
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.245677662
Short name T370
Test name
Test status
Simulation time 508962711 ps
CPU time 5.15 seconds
Started Aug 16 04:34:17 PM PDT 24
Finished Aug 16 04:34:22 PM PDT 24
Peak memory 215160 kb
Host smart-c793bb1c-65df-4494-9d20-32026d189fa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245677662 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.245677662
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2621072575
Short name T425
Test name
Test status
Simulation time 346743604 ps
CPU time 3.94 seconds
Started Aug 16 04:34:14 PM PDT 24
Finished Aug 16 04:34:18 PM PDT 24
Peak memory 218368 kb
Host smart-f813bf07-4fd9-420a-b1d6-1edb96fcab33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621072575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2621072575
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3185531088
Short name T451
Test name
Test status
Simulation time 3277233690 ps
CPU time 31.66 seconds
Started Aug 16 04:34:10 PM PDT 24
Finished Aug 16 04:34:42 PM PDT 24
Peak memory 211672 kb
Host smart-4591fe2c-b5f7-4982-ab25-c8ff0b41441c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185531088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3185531088
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1641591453
Short name T87
Test name
Test status
Simulation time 141251862 ps
CPU time 6.72 seconds
Started Aug 16 04:34:13 PM PDT 24
Finished Aug 16 04:34:21 PM PDT 24
Peak memory 211340 kb
Host smart-fa4c5072-15cc-4845-a40f-9059a82ff211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641591453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1641591453
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.378178193
Short name T398
Test name
Test status
Simulation time 258696931 ps
CPU time 8.7 seconds
Started Aug 16 04:34:11 PM PDT 24
Finished Aug 16 04:34:20 PM PDT 24
Peak memory 215440 kb
Host smart-21cb1e25-818b-4ec5-a9ee-8006fb2cbea6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378178193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.378178193
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1976877899
Short name T55
Test name
Test status
Simulation time 1574852345 ps
CPU time 36.52 seconds
Started Aug 16 04:34:14 PM PDT 24
Finished Aug 16 04:34:51 PM PDT 24
Peak memory 212900 kb
Host smart-aafc40d4-0e0e-4fbe-850e-f9b3c2d60c97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976877899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1976877899
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2191269763
Short name T424
Test name
Test status
Simulation time 184864868 ps
CPU time 4.22 seconds
Started Aug 16 04:34:34 PM PDT 24
Finished Aug 16 04:34:38 PM PDT 24
Peak memory 219464 kb
Host smart-cf83a1fe-6c78-4882-ac4c-68fa0e978c60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191269763 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2191269763
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.842083309
Short name T456
Test name
Test status
Simulation time 253601443 ps
CPU time 4 seconds
Started Aug 16 04:34:12 PM PDT 24
Finished Aug 16 04:34:16 PM PDT 24
Peak memory 211308 kb
Host smart-62e75217-4d3a-489d-8d01-9888824449b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842083309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.842083309
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.52323521
Short name T434
Test name
Test status
Simulation time 3366846658 ps
CPU time 26.1 seconds
Started Aug 16 04:34:25 PM PDT 24
Finished Aug 16 04:34:52 PM PDT 24
Peak memory 212440 kb
Host smart-2a4f9ac4-9add-4f8b-afca-2809d44b83b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52323521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pas
sthru_mem_tl_intg_err.52323521
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2484223136
Short name T378
Test name
Test status
Simulation time 351568440 ps
CPU time 4.1 seconds
Started Aug 16 04:34:15 PM PDT 24
Finished Aug 16 04:34:19 PM PDT 24
Peak memory 211308 kb
Host smart-c2ea61f5-8b92-4624-86ec-389adaf66a79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484223136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2484223136
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3896217342
Short name T400
Test name
Test status
Simulation time 588213415 ps
CPU time 8.74 seconds
Started Aug 16 04:34:20 PM PDT 24
Finished Aug 16 04:34:29 PM PDT 24
Peak memory 216420 kb
Host smart-52f8cdf6-dd53-403a-be12-43fc9477203e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896217342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3896217342
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.721291515
Short name T452
Test name
Test status
Simulation time 639314601 ps
CPU time 39.33 seconds
Started Aug 16 04:34:26 PM PDT 24
Finished Aug 16 04:35:06 PM PDT 24
Peak memory 211792 kb
Host smart-1e60fdd0-08d0-474b-a88c-1e4bc7f06fcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721291515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.721291515
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2642296012
Short name T428
Test name
Test status
Simulation time 93048081 ps
CPU time 4.61 seconds
Started Aug 16 04:34:10 PM PDT 24
Finished Aug 16 04:34:15 PM PDT 24
Peak memory 213388 kb
Host smart-b855c602-3e4f-479e-83af-524b7ed11186
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642296012 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2642296012
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.906280897
Short name T394
Test name
Test status
Simulation time 126150652 ps
CPU time 4.92 seconds
Started Aug 16 04:34:17 PM PDT 24
Finished Aug 16 04:34:22 PM PDT 24
Peak memory 211244 kb
Host smart-192be825-b992-4b86-9c1a-3a7f26df0533
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906280897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.906280897
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3405366571
Short name T377
Test name
Test status
Simulation time 133462734 ps
CPU time 4.86 seconds
Started Aug 16 04:34:12 PM PDT 24
Finished Aug 16 04:34:17 PM PDT 24
Peak memory 211320 kb
Host smart-f7e0f225-d7c4-4c7c-b53e-3313f9580350
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405366571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3405366571
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.687469832
Short name T396
Test name
Test status
Simulation time 1029766530 ps
CPU time 8.6 seconds
Started Aug 16 04:34:18 PM PDT 24
Finished Aug 16 04:34:27 PM PDT 24
Peak memory 216512 kb
Host smart-225ddf53-ed74-41bd-9cd4-a97abcb6f693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687469832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.687469832
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1814731171
Short name T374
Test name
Test status
Simulation time 127472527 ps
CPU time 4.92 seconds
Started Aug 16 04:34:05 PM PDT 24
Finished Aug 16 04:34:10 PM PDT 24
Peak memory 211268 kb
Host smart-78767469-b87d-45ce-98be-fda52b3a75b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814731171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1814731171
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.518240264
Short name T403
Test name
Test status
Simulation time 273714626 ps
CPU time 4.82 seconds
Started Aug 16 04:33:58 PM PDT 24
Finished Aug 16 04:34:02 PM PDT 24
Peak memory 217764 kb
Host smart-fff59d4c-f102-46e0-8550-4cdd5ae7b9fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518240264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.518240264
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2533851820
Short name T433
Test name
Test status
Simulation time 132814508 ps
CPU time 6.43 seconds
Started Aug 16 04:33:57 PM PDT 24
Finished Aug 16 04:34:03 PM PDT 24
Peak memory 211272 kb
Host smart-cc4b0097-03f8-4a69-b3ad-3dc1dd49a850
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533851820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2533851820
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2182443127
Short name T436
Test name
Test status
Simulation time 905570388 ps
CPU time 4.5 seconds
Started Aug 16 04:33:58 PM PDT 24
Finished Aug 16 04:34:03 PM PDT 24
Peak memory 219464 kb
Host smart-f45c7238-3fa3-4312-a045-97f751dc38eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182443127 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2182443127
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3824515813
Short name T365
Test name
Test status
Simulation time 922667119 ps
CPU time 4.05 seconds
Started Aug 16 04:33:49 PM PDT 24
Finished Aug 16 04:33:53 PM PDT 24
Peak memory 218288 kb
Host smart-e02f093e-a834-43c8-933f-460cccb08199
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824515813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3824515813
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1853135299
Short name T390
Test name
Test status
Simulation time 271107890 ps
CPU time 3.99 seconds
Started Aug 16 04:34:10 PM PDT 24
Finished Aug 16 04:34:14 PM PDT 24
Peak memory 211204 kb
Host smart-85a2da57-607b-4c9f-938d-9165280ddda6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853135299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1853135299
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4059392084
Short name T358
Test name
Test status
Simulation time 132072034 ps
CPU time 4.68 seconds
Started Aug 16 04:33:57 PM PDT 24
Finished Aug 16 04:34:01 PM PDT 24
Peak memory 211212 kb
Host smart-d7b83c11-69b6-4241-93c2-38ebfa654d54
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059392084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4059392084
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3980238838
Short name T406
Test name
Test status
Simulation time 373365507 ps
CPU time 17.9 seconds
Started Aug 16 04:34:11 PM PDT 24
Finished Aug 16 04:34:29 PM PDT 24
Peak memory 211224 kb
Host smart-658ab400-499d-4059-bbf3-911c54cad3e6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980238838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3980238838
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3465502055
Short name T395
Test name
Test status
Simulation time 126602956 ps
CPU time 5 seconds
Started Aug 16 04:33:59 PM PDT 24
Finished Aug 16 04:34:04 PM PDT 24
Peak memory 211288 kb
Host smart-a9bac08b-ab49-42ae-9317-e6df611c11ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465502055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3465502055
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3088608689
Short name T363
Test name
Test status
Simulation time 129669650 ps
CPU time 9.28 seconds
Started Aug 16 04:34:04 PM PDT 24
Finished Aug 16 04:34:13 PM PDT 24
Peak memory 216588 kb
Host smart-8fb8b9ef-5fd7-438e-b41a-c61351ec5c55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088608689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3088608689
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3778055069
Short name T99
Test name
Test status
Simulation time 656478683 ps
CPU time 36.07 seconds
Started Aug 16 04:34:06 PM PDT 24
Finished Aug 16 04:34:42 PM PDT 24
Peak memory 219516 kb
Host smart-d2bbc48a-d61c-42f9-a5e8-be52e0d9c64d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778055069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3778055069
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1156021610
Short name T88
Test name
Test status
Simulation time 87930619 ps
CPU time 4.02 seconds
Started Aug 16 04:34:04 PM PDT 24
Finished Aug 16 04:34:09 PM PDT 24
Peak memory 219436 kb
Host smart-2efa3bf1-a3be-4c91-9e4b-5ccad56286d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156021610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1156021610
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3123650046
Short name T361
Test name
Test status
Simulation time 832825110 ps
CPU time 4.8 seconds
Started Aug 16 04:33:57 PM PDT 24
Finished Aug 16 04:34:02 PM PDT 24
Peak memory 218304 kb
Host smart-0a190af1-f354-4abd-9f13-dbb2c3832ae7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123650046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3123650046
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1051015452
Short name T438
Test name
Test status
Simulation time 357882850 ps
CPU time 7.17 seconds
Started Aug 16 04:33:56 PM PDT 24
Finished Aug 16 04:34:04 PM PDT 24
Peak memory 211272 kb
Host smart-1c862ce7-8b3b-46dc-aafb-c0034d97c707
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051015452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1051015452
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1934429697
Short name T366
Test name
Test status
Simulation time 206091506 ps
CPU time 6.13 seconds
Started Aug 16 04:33:59 PM PDT 24
Finished Aug 16 04:34:06 PM PDT 24
Peak memory 219500 kb
Host smart-814aa211-88cc-4d8a-b9ac-6eb38c8ed423
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934429697 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1934429697
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2528921551
Short name T402
Test name
Test status
Simulation time 288821249 ps
CPU time 4.08 seconds
Started Aug 16 04:34:03 PM PDT 24
Finished Aug 16 04:34:07 PM PDT 24
Peak memory 211312 kb
Host smart-7b5b2910-8fe3-4629-b150-ec2c4795c576
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528921551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2528921551
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.897935758
Short name T447
Test name
Test status
Simulation time 2077306923 ps
CPU time 4.7 seconds
Started Aug 16 04:33:57 PM PDT 24
Finished Aug 16 04:34:02 PM PDT 24
Peak memory 211252 kb
Host smart-53357329-f30b-41e5-9618-3ab6e6629039
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897935758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.897935758
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2833073641
Short name T450
Test name
Test status
Simulation time 127699705 ps
CPU time 4.95 seconds
Started Aug 16 04:33:56 PM PDT 24
Finished Aug 16 04:34:01 PM PDT 24
Peak memory 211244 kb
Host smart-fa411424-2f34-44ca-ac3d-9bad7f1f5cbd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833073641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2833073641
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1407957318
Short name T83
Test name
Test status
Simulation time 4021663252 ps
CPU time 21.07 seconds
Started Aug 16 04:34:06 PM PDT 24
Finished Aug 16 04:34:27 PM PDT 24
Peak memory 211440 kb
Host smart-a92d02dd-f08c-4243-a372-1d37525342da
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407957318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1407957318
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1484935361
Short name T415
Test name
Test status
Simulation time 345654961 ps
CPU time 5.72 seconds
Started Aug 16 04:33:59 PM PDT 24
Finished Aug 16 04:34:05 PM PDT 24
Peak memory 211584 kb
Host smart-629a3569-b123-41ab-8f4c-86b8319a9c86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484935361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1484935361
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3707520020
Short name T410
Test name
Test status
Simulation time 516838073 ps
CPU time 7.41 seconds
Started Aug 16 04:33:45 PM PDT 24
Finished Aug 16 04:33:52 PM PDT 24
Peak memory 219488 kb
Host smart-f0b408cc-de29-473e-857f-4d601414829c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707520020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3707520020
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.212740151
Short name T422
Test name
Test status
Simulation time 967171313 ps
CPU time 66.88 seconds
Started Aug 16 04:34:09 PM PDT 24
Finished Aug 16 04:35:16 PM PDT 24
Peak memory 213044 kb
Host smart-4f4929b4-7cb8-49a4-9134-1ebaa856804e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212740151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.212740151
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2687264898
Short name T393
Test name
Test status
Simulation time 172705351 ps
CPU time 4.01 seconds
Started Aug 16 04:34:12 PM PDT 24
Finished Aug 16 04:34:17 PM PDT 24
Peak memory 211288 kb
Host smart-783d69b2-a10e-4b04-a903-c70fe505ae16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687264898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2687264898
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.811147862
Short name T373
Test name
Test status
Simulation time 828344416 ps
CPU time 4.86 seconds
Started Aug 16 04:34:11 PM PDT 24
Finished Aug 16 04:34:16 PM PDT 24
Peak memory 211256 kb
Host smart-ad9e28a8-eca8-4f85-9772-13ef74d4216e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811147862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.811147862
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1037744814
Short name T440
Test name
Test status
Simulation time 92236610 ps
CPU time 5.61 seconds
Started Aug 16 04:34:05 PM PDT 24
Finished Aug 16 04:34:11 PM PDT 24
Peak memory 219448 kb
Host smart-8d9d6151-8e63-4784-8beb-c3ea9840a6fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037744814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1037744814
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1400474742
Short name T384
Test name
Test status
Simulation time 139877156 ps
CPU time 5.25 seconds
Started Aug 16 04:34:02 PM PDT 24
Finished Aug 16 04:34:07 PM PDT 24
Peak memory 215404 kb
Host smart-86dc140c-d474-4025-a20f-0238f86b4342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400474742 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1400474742
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3923022264
Short name T356
Test name
Test status
Simulation time 363514297 ps
CPU time 4.22 seconds
Started Aug 16 04:34:08 PM PDT 24
Finished Aug 16 04:34:13 PM PDT 24
Peak memory 219416 kb
Host smart-fbe83553-6202-462e-9a2c-29a9a4646b01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923022264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3923022264
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2671950155
Short name T359
Test name
Test status
Simulation time 89163318 ps
CPU time 4.05 seconds
Started Aug 16 04:34:02 PM PDT 24
Finished Aug 16 04:34:06 PM PDT 24
Peak memory 211168 kb
Host smart-31c69f33-fee5-4c51-9c5c-4e66a5a70cc2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671950155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2671950155
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3797334449
Short name T388
Test name
Test status
Simulation time 88147184 ps
CPU time 4.08 seconds
Started Aug 16 04:33:59 PM PDT 24
Finished Aug 16 04:34:04 PM PDT 24
Peak memory 211280 kb
Host smart-40b8f5d5-2043-4073-bdf3-b219be34a794
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797334449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3797334449
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1326016304
Short name T68
Test name
Test status
Simulation time 1698994362 ps
CPU time 30.9 seconds
Started Aug 16 04:33:57 PM PDT 24
Finished Aug 16 04:34:28 PM PDT 24
Peak memory 211296 kb
Host smart-99c63b86-e756-4774-97d3-b0d4a201fa9e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326016304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1326016304
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.351984705
Short name T431
Test name
Test status
Simulation time 176110193 ps
CPU time 5.63 seconds
Started Aug 16 04:34:06 PM PDT 24
Finished Aug 16 04:34:12 PM PDT 24
Peak memory 211740 kb
Host smart-e36f534a-b12f-43c6-9ae1-544485090fad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351984705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.351984705
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4226973175
Short name T421
Test name
Test status
Simulation time 568246080 ps
CPU time 9.66 seconds
Started Aug 16 04:33:46 PM PDT 24
Finished Aug 16 04:33:56 PM PDT 24
Peak memory 216380 kb
Host smart-60aa306f-be3d-4845-9b3f-30ef5421facc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226973175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.4226973175
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.539614058
Short name T101
Test name
Test status
Simulation time 209710117 ps
CPU time 37 seconds
Started Aug 16 04:34:07 PM PDT 24
Finished Aug 16 04:34:44 PM PDT 24
Peak memory 219384 kb
Host smart-7524eae0-5fd2-43d1-a0f6-bc2650c011f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539614058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.539614058
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2669369895
Short name T375
Test name
Test status
Simulation time 504124565 ps
CPU time 4.37 seconds
Started Aug 16 04:33:59 PM PDT 24
Finished Aug 16 04:34:04 PM PDT 24
Peak memory 215596 kb
Host smart-195ac89c-716e-49e2-9fb9-c33204ed97de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669369895 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2669369895
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2411587981
Short name T90
Test name
Test status
Simulation time 332681188 ps
CPU time 3.99 seconds
Started Aug 16 04:34:03 PM PDT 24
Finished Aug 16 04:34:08 PM PDT 24
Peak memory 211272 kb
Host smart-cbba5733-9d5a-43e3-9d9f-592f1ac64560
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411587981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2411587981
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1474500136
Short name T448
Test name
Test status
Simulation time 3571223520 ps
CPU time 29.92 seconds
Started Aug 16 04:34:12 PM PDT 24
Finished Aug 16 04:34:43 PM PDT 24
Peak memory 211800 kb
Host smart-45652534-1804-458a-b88e-3eca89f2d3f1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474500136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1474500136
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.515874142
Short name T84
Test name
Test status
Simulation time 132087972 ps
CPU time 6.65 seconds
Started Aug 16 04:33:48 PM PDT 24
Finished Aug 16 04:33:55 PM PDT 24
Peak memory 211392 kb
Host smart-e64727f3-cac4-4b8e-9f37-7300fdddb1c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515874142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.515874142
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2645224237
Short name T364
Test name
Test status
Simulation time 754018667 ps
CPU time 6.41 seconds
Started Aug 16 04:33:56 PM PDT 24
Finished Aug 16 04:34:02 PM PDT 24
Peak memory 216292 kb
Host smart-76c55e6b-61bf-460a-86a0-8f8e07126fde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645224237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2645224237
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.817159796
Short name T399
Test name
Test status
Simulation time 680423193 ps
CPU time 36.48 seconds
Started Aug 16 04:33:50 PM PDT 24
Finished Aug 16 04:34:26 PM PDT 24
Peak memory 219432 kb
Host smart-43f630b3-3efe-47cb-b1eb-d3021b6933da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817159796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.817159796
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3080630327
Short name T372
Test name
Test status
Simulation time 1575525573 ps
CPU time 5.42 seconds
Started Aug 16 04:34:10 PM PDT 24
Finished Aug 16 04:34:16 PM PDT 24
Peak memory 219516 kb
Host smart-2f4334a0-fa65-4ac7-b092-24697b79e89d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080630327 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3080630327
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3626117561
Short name T360
Test name
Test status
Simulation time 500133730 ps
CPU time 4.86 seconds
Started Aug 16 04:34:05 PM PDT 24
Finished Aug 16 04:34:10 PM PDT 24
Peak memory 211300 kb
Host smart-5f95a9c2-0766-4775-a05c-a2e8af368e5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626117561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3626117561
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.647687802
Short name T63
Test name
Test status
Simulation time 3134741175 ps
CPU time 30.81 seconds
Started Aug 16 04:34:03 PM PDT 24
Finished Aug 16 04:34:34 PM PDT 24
Peak memory 211428 kb
Host smart-57443917-c389-49b0-b5d0-36922328519a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647687802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.647687802
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.116172042
Short name T444
Test name
Test status
Simulation time 131391328 ps
CPU time 5.05 seconds
Started Aug 16 04:34:07 PM PDT 24
Finished Aug 16 04:34:12 PM PDT 24
Peak memory 211248 kb
Host smart-3d010c89-a6c6-4400-bd9b-5c4067993b80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116172042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.116172042
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1261989402
Short name T408
Test name
Test status
Simulation time 171190242 ps
CPU time 8.3 seconds
Started Aug 16 04:33:57 PM PDT 24
Finished Aug 16 04:34:06 PM PDT 24
Peak memory 216524 kb
Host smart-d0a72cc8-cd3d-42c9-8435-ad5612f68c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261989402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1261989402
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2457146273
Short name T56
Test name
Test status
Simulation time 217990579 ps
CPU time 68.54 seconds
Started Aug 16 04:34:04 PM PDT 24
Finished Aug 16 04:35:13 PM PDT 24
Peak memory 219540 kb
Host smart-bc9c4946-eb03-420f-8cf7-1e264be4430b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457146273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2457146273
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1618013249
Short name T357
Test name
Test status
Simulation time 531461748 ps
CPU time 5.08 seconds
Started Aug 16 04:34:04 PM PDT 24
Finished Aug 16 04:34:10 PM PDT 24
Peak memory 214864 kb
Host smart-79461ea3-eff5-4194-a2d4-348765ada48d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618013249 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1618013249
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1420962444
Short name T89
Test name
Test status
Simulation time 130781946 ps
CPU time 4.85 seconds
Started Aug 16 04:34:09 PM PDT 24
Finished Aug 16 04:34:14 PM PDT 24
Peak memory 211256 kb
Host smart-53d7cd94-1160-4821-be93-d72561e4ce66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420962444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1420962444
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3260023092
Short name T80
Test name
Test status
Simulation time 3264872300 ps
CPU time 31.23 seconds
Started Aug 16 04:34:05 PM PDT 24
Finished Aug 16 04:34:36 PM PDT 24
Peak memory 211672 kb
Host smart-99ec4d54-e4bc-45bf-b686-e736ca1a88cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260023092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3260023092
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.326569593
Short name T376
Test name
Test status
Simulation time 534853864 ps
CPU time 6.71 seconds
Started Aug 16 04:34:13 PM PDT 24
Finished Aug 16 04:34:20 PM PDT 24
Peak memory 218732 kb
Host smart-85146bab-5703-4dab-8180-ec8bf6d30c79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326569593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.326569593
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3756504207
Short name T426
Test name
Test status
Simulation time 89053827 ps
CPU time 7.54 seconds
Started Aug 16 04:34:05 PM PDT 24
Finished Aug 16 04:34:13 PM PDT 24
Peak memory 216356 kb
Host smart-681d6efc-9481-4f16-8f43-267a18db45b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756504207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3756504207
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3642474563
Short name T435
Test name
Test status
Simulation time 763108762 ps
CPU time 78.98 seconds
Started Aug 16 04:34:09 PM PDT 24
Finished Aug 16 04:35:28 PM PDT 24
Peak memory 219460 kb
Host smart-e3be960c-55ab-41f8-b83e-208fbbe2d7dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642474563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3642474563
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2147860194
Short name T368
Test name
Test status
Simulation time 276594590 ps
CPU time 6.1 seconds
Started Aug 16 04:34:14 PM PDT 24
Finished Aug 16 04:34:21 PM PDT 24
Peak memory 216680 kb
Host smart-7cb9fe60-d48f-4725-ac1b-ea8664dd0993
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147860194 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2147860194
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4281648639
Short name T445
Test name
Test status
Simulation time 168916531 ps
CPU time 4.11 seconds
Started Aug 16 04:33:55 PM PDT 24
Finished Aug 16 04:33:59 PM PDT 24
Peak memory 219392 kb
Host smart-cb85778c-5376-4f2c-a6e2-b88d97c20f99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281648639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4281648639
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2127543002
Short name T73
Test name
Test status
Simulation time 4603086268 ps
CPU time 29.79 seconds
Started Aug 16 04:34:13 PM PDT 24
Finished Aug 16 04:34:43 PM PDT 24
Peak memory 211396 kb
Host smart-0196b758-3bef-4d71-9a69-07361d84daba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127543002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2127543002
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3836086089
Short name T418
Test name
Test status
Simulation time 393960397 ps
CPU time 5.69 seconds
Started Aug 16 04:34:04 PM PDT 24
Finished Aug 16 04:34:09 PM PDT 24
Peak memory 219428 kb
Host smart-207969f5-2422-4cd9-995b-74a08dddf3c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836086089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3836086089
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1377090712
Short name T96
Test name
Test status
Simulation time 290549566 ps
CPU time 68.67 seconds
Started Aug 16 04:34:08 PM PDT 24
Finished Aug 16 04:35:17 PM PDT 24
Peak memory 219444 kb
Host smart-1a6ba998-24e1-44ea-bd00-2372021b959b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377090712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1377090712
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3444053309
Short name T430
Test name
Test status
Simulation time 538857766 ps
CPU time 5.05 seconds
Started Aug 16 04:34:10 PM PDT 24
Finished Aug 16 04:34:16 PM PDT 24
Peak memory 219516 kb
Host smart-c220ffa4-9f99-4052-982c-a60dc4b32ff7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444053309 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3444053309
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.215882910
Short name T79
Test name
Test status
Simulation time 1180093432 ps
CPU time 4.02 seconds
Started Aug 16 04:34:13 PM PDT 24
Finished Aug 16 04:34:17 PM PDT 24
Peak memory 211296 kb
Host smart-4b5b9bfb-f93d-4648-9d91-7c660a941b9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215882910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.215882910
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1660530355
Short name T66
Test name
Test status
Simulation time 3285251054 ps
CPU time 30.57 seconds
Started Aug 16 04:34:08 PM PDT 24
Finished Aug 16 04:34:39 PM PDT 24
Peak memory 211380 kb
Host smart-f0e1abc1-c05b-4c73-b7c6-5a5060820458
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660530355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1660530355
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1659685512
Short name T411
Test name
Test status
Simulation time 172379847 ps
CPU time 3.98 seconds
Started Aug 16 04:34:14 PM PDT 24
Finished Aug 16 04:34:18 PM PDT 24
Peak memory 219452 kb
Host smart-46638dcf-e20c-4209-9cee-1c5a13ff8122
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659685512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1659685512
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4261937517
Short name T453
Test name
Test status
Simulation time 292332744 ps
CPU time 7.38 seconds
Started Aug 16 04:34:00 PM PDT 24
Finished Aug 16 04:34:08 PM PDT 24
Peak memory 216268 kb
Host smart-1342715a-7e25-4d5b-934d-c46dca0df59d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261937517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.4261937517
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3299717435
Short name T397
Test name
Test status
Simulation time 521367490 ps
CPU time 66.47 seconds
Started Aug 16 04:34:15 PM PDT 24
Finished Aug 16 04:35:22 PM PDT 24
Peak memory 212980 kb
Host smart-cfbd020e-7b59-42df-aaeb-da3beb03a8b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299717435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3299717435
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1595042024
Short name T250
Test name
Test status
Simulation time 250519658 ps
CPU time 4.85 seconds
Started Aug 16 06:14:33 PM PDT 24
Finished Aug 16 06:14:38 PM PDT 24
Peak memory 211128 kb
Host smart-a0b8b805-0fd4-4c08-bd0a-fd1e005530bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595042024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1595042024
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1175317439
Short name T224
Test name
Test status
Simulation time 14765688075 ps
CPU time 124.72 seconds
Started Aug 16 06:14:23 PM PDT 24
Finished Aug 16 06:16:28 PM PDT 24
Peak memory 212432 kb
Host smart-928be765-35a7-4b08-818c-55b3a91c7600
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175317439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1175317439
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3895785733
Short name T272
Test name
Test status
Simulation time 251412897 ps
CPU time 10.47 seconds
Started Aug 16 06:14:22 PM PDT 24
Finished Aug 16 06:14:33 PM PDT 24
Peak memory 211564 kb
Host smart-b394b85e-3493-4da5-9571-a20e3802be6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895785733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3895785733
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.347748865
Short name T139
Test name
Test status
Simulation time 404845353 ps
CPU time 5.34 seconds
Started Aug 16 06:14:21 PM PDT 24
Finished Aug 16 06:14:27 PM PDT 24
Peak memory 211032 kb
Host smart-ddb721b6-26c2-4916-b3a1-9e83d855c670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=347748865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.347748865
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2287475607
Short name T27
Test name
Test status
Simulation time 203981237 ps
CPU time 51.62 seconds
Started Aug 16 06:14:24 PM PDT 24
Finished Aug 16 06:15:16 PM PDT 24
Peak memory 234912 kb
Host smart-b6183f7f-22fe-48b0-a598-0c349e1c5739
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287475607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2287475607
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3577776703
Short name T12
Test name
Test status
Simulation time 140680305 ps
CPU time 6.37 seconds
Started Aug 16 06:14:26 PM PDT 24
Finished Aug 16 06:14:32 PM PDT 24
Peak memory 211240 kb
Host smart-05209ffe-e7a7-49ca-83f7-d60ee55ca5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577776703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3577776703
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.58778423
Short name T36
Test name
Test status
Simulation time 825422829 ps
CPU time 11.89 seconds
Started Aug 16 06:14:24 PM PDT 24
Finished Aug 16 06:14:36 PM PDT 24
Peak memory 213544 kb
Host smart-436748d5-564c-446e-8ec6-c60263b5234f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58778423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.rom_ctrl_stress_all.58778423
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.324913115
Short name T138
Test name
Test status
Simulation time 17527353628 ps
CPU time 271.21 seconds
Started Aug 16 06:14:22 PM PDT 24
Finished Aug 16 06:18:54 PM PDT 24
Peak memory 232208 kb
Host smart-be882b8e-c177-47d5-8450-55a108de3739
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324913115 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.324913115
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2280153575
Short name T303
Test name
Test status
Simulation time 1241326705 ps
CPU time 4.63 seconds
Started Aug 16 06:14:40 PM PDT 24
Finished Aug 16 06:14:45 PM PDT 24
Peak memory 210992 kb
Host smart-6d89bb4c-4dfe-4e19-88b6-bdaba7ed40d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280153575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2280153575
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.94465173
Short name T197
Test name
Test status
Simulation time 8286933809 ps
CPU time 134.14 seconds
Started Aug 16 06:14:33 PM PDT 24
Finished Aug 16 06:16:47 PM PDT 24
Peak memory 236584 kb
Host smart-70f08a9f-79dd-45f3-b577-3e74bb6987b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94465173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_cor
rupt_sig_fatal_chk.94465173
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.149468414
Short name T284
Test name
Test status
Simulation time 1084504966 ps
CPU time 10.68 seconds
Started Aug 16 06:14:31 PM PDT 24
Finished Aug 16 06:14:42 PM PDT 24
Peak memory 211076 kb
Host smart-a972a1e6-81f1-4055-a2ac-85290ffb5f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149468414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.149468414
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2073642807
Short name T4
Test name
Test status
Simulation time 481787281 ps
CPU time 5.24 seconds
Started Aug 16 06:14:33 PM PDT 24
Finished Aug 16 06:14:38 PM PDT 24
Peak memory 211144 kb
Host smart-cf84aac6-fcb6-490f-9b3e-182438fe5233
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2073642807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2073642807
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2774749499
Short name T265
Test name
Test status
Simulation time 100044188 ps
CPU time 5.57 seconds
Started Aug 16 06:14:34 PM PDT 24
Finished Aug 16 06:14:40 PM PDT 24
Peak memory 211568 kb
Host smart-bdc8b5ec-72cf-4a29-be0a-01c83476aaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774749499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2774749499
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1280651839
Short name T253
Test name
Test status
Simulation time 117967030 ps
CPU time 10.17 seconds
Started Aug 16 06:14:34 PM PDT 24
Finished Aug 16 06:14:44 PM PDT 24
Peak memory 210932 kb
Host smart-67dca16b-9d70-4b1b-b744-f46d71fe257e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280651839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1280651839
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3178125329
Short name T54
Test name
Test status
Simulation time 7511333480 ps
CPU time 131.47 seconds
Started Aug 16 06:14:40 PM PDT 24
Finished Aug 16 06:16:51 PM PDT 24
Peak memory 222316 kb
Host smart-2c589fda-28a4-47f9-bd2c-0ad6247f74d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178125329 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3178125329
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.551039227
Short name T336
Test name
Test status
Simulation time 2042872593 ps
CPU time 6.65 seconds
Started Aug 16 06:14:50 PM PDT 24
Finished Aug 16 06:14:56 PM PDT 24
Peak memory 211132 kb
Host smart-5ff07ef4-8405-4663-91f2-699d5512a915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551039227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.551039227
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2178754004
Short name T180
Test name
Test status
Simulation time 13407543329 ps
CPU time 195.97 seconds
Started Aug 16 06:14:50 PM PDT 24
Finished Aug 16 06:18:06 PM PDT 24
Peak memory 212484 kb
Host smart-56d4586e-a34e-491a-b951-2ee61b44bfb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178754004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2178754004
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3827629235
Short name T342
Test name
Test status
Simulation time 696610664 ps
CPU time 8.97 seconds
Started Aug 16 06:14:47 PM PDT 24
Finished Aug 16 06:14:56 PM PDT 24
Peak memory 211396 kb
Host smart-ae1924ef-65f8-4815-9ae7-f9efd74f661a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827629235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3827629235
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.249573958
Short name T278
Test name
Test status
Simulation time 279043766 ps
CPU time 6.23 seconds
Started Aug 16 06:14:49 PM PDT 24
Finished Aug 16 06:14:55 PM PDT 24
Peak memory 211100 kb
Host smart-e7858e7f-4390-4d83-b2d6-cac96caab144
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=249573958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.249573958
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1411921260
Short name T179
Test name
Test status
Simulation time 434352224 ps
CPU time 20.45 seconds
Started Aug 16 06:14:49 PM PDT 24
Finished Aug 16 06:15:09 PM PDT 24
Peak memory 214396 kb
Host smart-fb5e7835-3766-42b4-accd-46b1e34c0913
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411921260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1411921260
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3333152304
Short name T200
Test name
Test status
Simulation time 5153863765 ps
CPU time 64.15 seconds
Started Aug 16 06:14:50 PM PDT 24
Finished Aug 16 06:15:54 PM PDT 24
Peak memory 223168 kb
Host smart-790c91c7-8ad9-475e-b44b-7882c4ab09ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333152304 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3333152304
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1850677775
Short name T288
Test name
Test status
Simulation time 639975210 ps
CPU time 4.09 seconds
Started Aug 16 06:14:48 PM PDT 24
Finished Aug 16 06:14:52 PM PDT 24
Peak memory 211012 kb
Host smart-b8187f7e-81d2-4f7b-b826-7d161e55ac78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850677775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1850677775
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1581757890
Short name T182
Test name
Test status
Simulation time 2008816872 ps
CPU time 7.92 seconds
Started Aug 16 06:14:47 PM PDT 24
Finished Aug 16 06:14:55 PM PDT 24
Peak memory 211052 kb
Host smart-04214020-91b6-474c-bce5-f72601308423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1581757890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1581757890
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.929247001
Short name T330
Test name
Test status
Simulation time 1667820884 ps
CPU time 21.78 seconds
Started Aug 16 06:14:48 PM PDT 24
Finished Aug 16 06:15:10 PM PDT 24
Peak memory 215620 kb
Host smart-77fc6f04-adcb-4738-adbf-031c34ed7ba9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929247001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.929247001
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1575266029
Short name T125
Test name
Test status
Simulation time 16900411683 ps
CPU time 185.01 seconds
Started Aug 16 06:14:50 PM PDT 24
Finished Aug 16 06:17:55 PM PDT 24
Peak memory 232804 kb
Host smart-141ac863-87ab-4d2e-b8cc-db2a1d4805cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575266029 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1575266029
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2678492199
Short name T172
Test name
Test status
Simulation time 262499528 ps
CPU time 4.9 seconds
Started Aug 16 06:14:57 PM PDT 24
Finished Aug 16 06:15:02 PM PDT 24
Peak memory 211116 kb
Host smart-83bb0041-7cc9-49dc-bd3a-dcfe1dcbcd4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678492199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2678492199
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.982875848
Short name T290
Test name
Test status
Simulation time 9653128777 ps
CPU time 136 seconds
Started Aug 16 06:14:56 PM PDT 24
Finished Aug 16 06:17:13 PM PDT 24
Peak memory 237708 kb
Host smart-85912eb8-62f3-42df-80bf-294f43e0a2c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982875848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.982875848
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.487109253
Short name T215
Test name
Test status
Simulation time 245726418 ps
CPU time 6.52 seconds
Started Aug 16 06:14:48 PM PDT 24
Finished Aug 16 06:14:55 PM PDT 24
Peak memory 211140 kb
Host smart-283181b1-c9b1-4ba4-9d80-87755d77ce63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487109253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.487109253
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1638764243
Short name T140
Test name
Test status
Simulation time 2331082140 ps
CPU time 16.09 seconds
Started Aug 16 06:14:48 PM PDT 24
Finished Aug 16 06:15:05 PM PDT 24
Peak memory 213828 kb
Host smart-895e78b4-44d3-477e-9fe1-976b28e4c16d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638764243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1638764243
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.881072382
Short name T183
Test name
Test status
Simulation time 127244688 ps
CPU time 4.96 seconds
Started Aug 16 06:14:54 PM PDT 24
Finished Aug 16 06:14:59 PM PDT 24
Peak memory 211132 kb
Host smart-e0ce1b28-f1f4-4ab2-9cbe-dad674085ec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881072382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.881072382
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1702752404
Short name T144
Test name
Test status
Simulation time 2771812235 ps
CPU time 145.81 seconds
Started Aug 16 06:14:56 PM PDT 24
Finished Aug 16 06:17:22 PM PDT 24
Peak memory 236788 kb
Host smart-a40a64ef-1ca8-4058-bd41-238171e6782a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702752404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1702752404
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2837386194
Short name T334
Test name
Test status
Simulation time 462304058 ps
CPU time 9.19 seconds
Started Aug 16 06:14:54 PM PDT 24
Finished Aug 16 06:15:04 PM PDT 24
Peak memory 211648 kb
Host smart-7dce04d7-a0be-4cb9-9b48-bd0bff1635a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837386194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2837386194
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1162426581
Short name T115
Test name
Test status
Simulation time 1484302363 ps
CPU time 6.16 seconds
Started Aug 16 06:14:57 PM PDT 24
Finished Aug 16 06:15:03 PM PDT 24
Peak memory 211112 kb
Host smart-f0faa3bf-0aee-43cc-a814-d923d0af7e59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162426581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1162426581
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2792994427
Short name T168
Test name
Test status
Simulation time 7450809821 ps
CPU time 11.73 seconds
Started Aug 16 06:14:56 PM PDT 24
Finished Aug 16 06:15:08 PM PDT 24
Peak memory 211388 kb
Host smart-52dc280b-a7f5-459f-80eb-0b1b19a269ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792994427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2792994427
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.257419351
Short name T297
Test name
Test status
Simulation time 4320122405 ps
CPU time 89.64 seconds
Started Aug 16 06:14:55 PM PDT 24
Finished Aug 16 06:16:25 PM PDT 24
Peak memory 220896 kb
Host smart-0c728810-29eb-485e-9eb3-2d8f40ceccf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257419351 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.257419351
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2628037073
Short name T217
Test name
Test status
Simulation time 347248341 ps
CPU time 3.99 seconds
Started Aug 16 06:14:57 PM PDT 24
Finished Aug 16 06:15:01 PM PDT 24
Peak memory 211144 kb
Host smart-18457c3f-3e00-4fc6-8410-7d77b98bd6b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628037073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2628037073
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.284377144
Short name T281
Test name
Test status
Simulation time 2293339917 ps
CPU time 107.03 seconds
Started Aug 16 06:14:59 PM PDT 24
Finished Aug 16 06:16:46 PM PDT 24
Peak memory 236460 kb
Host smart-bcf70ea9-782e-4f56-b416-f0d3dfa6c0e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284377144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.284377144
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1713348499
Short name T279
Test name
Test status
Simulation time 185121150 ps
CPU time 9 seconds
Started Aug 16 06:14:56 PM PDT 24
Finished Aug 16 06:15:05 PM PDT 24
Peak memory 211240 kb
Host smart-73b77adf-7077-4bb0-96fd-09c5b162cbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713348499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1713348499
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3693511021
Short name T186
Test name
Test status
Simulation time 99500913 ps
CPU time 5.67 seconds
Started Aug 16 06:14:58 PM PDT 24
Finished Aug 16 06:15:04 PM PDT 24
Peak memory 211112 kb
Host smart-586d5fa9-3b65-4bde-9326-ab81444068f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3693511021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3693511021
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.832770644
Short name T69
Test name
Test status
Simulation time 2775556599 ps
CPU time 23.77 seconds
Started Aug 16 06:14:57 PM PDT 24
Finished Aug 16 06:15:21 PM PDT 24
Peak memory 214540 kb
Host smart-23539f2f-471e-4c3b-9b99-a7cad6a78a79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832770644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.832770644
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2475681216
Short name T327
Test name
Test status
Simulation time 333430881 ps
CPU time 4.08 seconds
Started Aug 16 06:14:54 PM PDT 24
Finished Aug 16 06:14:58 PM PDT 24
Peak memory 211204 kb
Host smart-4effbdc2-0d44-4cea-969d-86a55910d6d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475681216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2475681216
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2440112066
Short name T251
Test name
Test status
Simulation time 14693038897 ps
CPU time 159.97 seconds
Started Aug 16 06:15:00 PM PDT 24
Finished Aug 16 06:17:40 PM PDT 24
Peak memory 212388 kb
Host smart-10033d5b-c65a-45cf-8afd-aba1c63bfe80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440112066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2440112066
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2393513110
Short name T132
Test name
Test status
Simulation time 996469411 ps
CPU time 10.78 seconds
Started Aug 16 06:14:56 PM PDT 24
Finished Aug 16 06:15:07 PM PDT 24
Peak memory 211464 kb
Host smart-7fb5934c-f167-4fbf-959d-40823c015927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393513110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2393513110
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.126044910
Short name T208
Test name
Test status
Simulation time 143726581 ps
CPU time 6.53 seconds
Started Aug 16 06:15:00 PM PDT 24
Finished Aug 16 06:15:07 PM PDT 24
Peak memory 211112 kb
Host smart-e061185d-6e81-44cf-8c5c-3968b0ce874b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126044910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.126044910
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3041401358
Short name T320
Test name
Test status
Simulation time 1881777129 ps
CPU time 16.97 seconds
Started Aug 16 06:14:59 PM PDT 24
Finished Aug 16 06:15:16 PM PDT 24
Peak memory 215156 kb
Host smart-9d14a7b3-d345-4150-9520-e0db95d24d79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041401358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3041401358
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2002483013
Short name T185
Test name
Test status
Simulation time 19526538158 ps
CPU time 100.92 seconds
Started Aug 16 06:14:55 PM PDT 24
Finished Aug 16 06:16:36 PM PDT 24
Peak memory 222472 kb
Host smart-62046135-4a9c-4943-a15c-0714cf04434a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002483013 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2002483013
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4240413950
Short name T93
Test name
Test status
Simulation time 87235746 ps
CPU time 4.12 seconds
Started Aug 16 06:14:56 PM PDT 24
Finished Aug 16 06:15:00 PM PDT 24
Peak memory 211132 kb
Host smart-8031d0a4-bf66-4114-8b54-460383b62cdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240413950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4240413950
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2611226054
Short name T247
Test name
Test status
Simulation time 15092446138 ps
CPU time 191.86 seconds
Started Aug 16 06:14:58 PM PDT 24
Finished Aug 16 06:18:10 PM PDT 24
Peak memory 228496 kb
Host smart-b8f6e1fd-022c-469e-baad-2b62bdaa2092
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611226054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2611226054
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3042650263
Short name T312
Test name
Test status
Simulation time 259141094 ps
CPU time 10.57 seconds
Started Aug 16 06:14:55 PM PDT 24
Finished Aug 16 06:15:06 PM PDT 24
Peak memory 211148 kb
Host smart-f2af47a4-0e02-49cf-af46-78320c1df6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042650263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3042650263
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2135032321
Short name T202
Test name
Test status
Simulation time 275291258 ps
CPU time 6 seconds
Started Aug 16 06:14:56 PM PDT 24
Finished Aug 16 06:15:03 PM PDT 24
Peak memory 211076 kb
Host smart-75d4edb6-a3e0-48b8-98b9-b1a1c0c3fbbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2135032321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2135032321
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2122910375
Short name T92
Test name
Test status
Simulation time 814986963 ps
CPU time 20.47 seconds
Started Aug 16 06:14:56 PM PDT 24
Finished Aug 16 06:15:16 PM PDT 24
Peak memory 215812 kb
Host smart-f59411dc-ace7-4629-912d-90e1459975fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122910375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2122910375
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.667759305
Short name T273
Test name
Test status
Simulation time 292857252 ps
CPU time 8.28 seconds
Started Aug 16 06:14:58 PM PDT 24
Finished Aug 16 06:15:06 PM PDT 24
Peak memory 217292 kb
Host smart-2f9c6097-0180-4849-aa51-45afce91b6e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667759305 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.667759305
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.4009828017
Short name T226
Test name
Test status
Simulation time 3274869596 ps
CPU time 6.91 seconds
Started Aug 16 06:15:04 PM PDT 24
Finished Aug 16 06:15:11 PM PDT 24
Peak memory 211256 kb
Host smart-3c48af96-83cf-41b1-877e-3cbd8ef0adca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009828017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4009828017
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3244748249
Short name T282
Test name
Test status
Simulation time 10760844594 ps
CPU time 133.11 seconds
Started Aug 16 06:15:08 PM PDT 24
Finished Aug 16 06:17:21 PM PDT 24
Peak memory 232488 kb
Host smart-ebf1c366-d857-468d-9088-0351f88bdab4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244748249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3244748249
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2270568947
Short name T271
Test name
Test status
Simulation time 255071671 ps
CPU time 10.59 seconds
Started Aug 16 06:15:03 PM PDT 24
Finished Aug 16 06:15:14 PM PDT 24
Peak memory 211564 kb
Host smart-65f7b9cd-8c57-4155-ae70-50e77c539c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270568947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2270568947
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.650227722
Short name T31
Test name
Test status
Simulation time 388279592 ps
CPU time 5.61 seconds
Started Aug 16 06:15:04 PM PDT 24
Finished Aug 16 06:15:10 PM PDT 24
Peak memory 211032 kb
Host smart-49de1378-0b69-4f2b-88f4-6827bba621fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=650227722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.650227722
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.210261887
Short name T170
Test name
Test status
Simulation time 3251334228 ps
CPU time 12.05 seconds
Started Aug 16 06:14:56 PM PDT 24
Finished Aug 16 06:15:08 PM PDT 24
Peak memory 212832 kb
Host smart-8cadb67a-249b-47bf-96f4-3f99218c3096
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210261887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.210261887
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.436081366
Short name T162
Test name
Test status
Simulation time 3043958885 ps
CPU time 120.18 seconds
Started Aug 16 06:15:07 PM PDT 24
Finished Aug 16 06:17:07 PM PDT 24
Peak memory 222220 kb
Host smart-ea1fd42e-3d8f-4882-a524-2da76da8b317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436081366 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.436081366
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4158580304
Short name T201
Test name
Test status
Simulation time 520281576 ps
CPU time 4.78 seconds
Started Aug 16 06:15:06 PM PDT 24
Finished Aug 16 06:15:11 PM PDT 24
Peak memory 211020 kb
Host smart-77dd5b51-0e97-4943-95dd-fac3aaf8aabf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158580304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4158580304
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4084002324
Short name T214
Test name
Test status
Simulation time 1391678530 ps
CPU time 83.71 seconds
Started Aug 16 06:15:03 PM PDT 24
Finished Aug 16 06:16:27 PM PDT 24
Peak memory 236552 kb
Host smart-20c41dd2-5a69-42c3-a64e-a37690ad5167
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084002324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4084002324
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2555659934
Short name T160
Test name
Test status
Simulation time 276317937 ps
CPU time 10.47 seconds
Started Aug 16 06:15:06 PM PDT 24
Finished Aug 16 06:15:16 PM PDT 24
Peak memory 211376 kb
Host smart-9fbf1a4f-66f4-48e1-af3d-d3fa1db5091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555659934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2555659934
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1746294657
Short name T353
Test name
Test status
Simulation time 550681155 ps
CPU time 6.02 seconds
Started Aug 16 06:15:07 PM PDT 24
Finished Aug 16 06:15:13 PM PDT 24
Peak memory 211116 kb
Host smart-7aaef113-a628-4839-85af-fe7ee79ade45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1746294657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1746294657
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1667388859
Short name T71
Test name
Test status
Simulation time 1793935057 ps
CPU time 22.32 seconds
Started Aug 16 06:15:05 PM PDT 24
Finished Aug 16 06:15:27 PM PDT 24
Peak memory 217020 kb
Host smart-1114a8d2-e866-4e54-a167-68c373ddf13d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667388859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1667388859
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1457473214
Short name T159
Test name
Test status
Simulation time 6376305827 ps
CPU time 199.69 seconds
Started Aug 16 06:15:02 PM PDT 24
Finished Aug 16 06:18:22 PM PDT 24
Peak memory 222040 kb
Host smart-ccc3792a-42e7-488f-97a3-84bb031d3238
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457473214 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1457473214
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2895962136
Short name T321
Test name
Test status
Simulation time 85940624 ps
CPU time 4.27 seconds
Started Aug 16 06:15:04 PM PDT 24
Finished Aug 16 06:15:08 PM PDT 24
Peak memory 211116 kb
Host smart-dbea88a1-47ed-4a97-95e6-dc6cfdf67d60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895962136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2895962136
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1543057685
Short name T157
Test name
Test status
Simulation time 10145009109 ps
CPU time 171.86 seconds
Started Aug 16 06:15:06 PM PDT 24
Finished Aug 16 06:17:58 PM PDT 24
Peak memory 236976 kb
Host smart-36fe2330-db6c-4e48-baa4-c3f90dc957fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543057685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1543057685
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.188693108
Short name T16
Test name
Test status
Simulation time 1037622029 ps
CPU time 10.69 seconds
Started Aug 16 06:15:04 PM PDT 24
Finished Aug 16 06:15:15 PM PDT 24
Peak memory 211152 kb
Host smart-00295214-5ab0-46af-848a-834a4846db77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188693108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.188693108
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2807743108
Short name T243
Test name
Test status
Simulation time 930290839 ps
CPU time 5.79 seconds
Started Aug 16 06:15:06 PM PDT 24
Finished Aug 16 06:15:12 PM PDT 24
Peak memory 210984 kb
Host smart-0bf0101a-04cd-4db5-bdb4-02968f27e20f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2807743108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2807743108
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1942973767
Short name T178
Test name
Test status
Simulation time 1362653559 ps
CPU time 8.02 seconds
Started Aug 16 06:15:03 PM PDT 24
Finished Aug 16 06:15:11 PM PDT 24
Peak memory 211628 kb
Host smart-89ef4b60-b082-49c3-9ce7-01225d5ad948
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942973767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1942973767
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2704087970
Short name T305
Test name
Test status
Simulation time 173890653 ps
CPU time 4.04 seconds
Started Aug 16 06:14:34 PM PDT 24
Finished Aug 16 06:14:39 PM PDT 24
Peak memory 211140 kb
Host smart-9793f8f4-38ff-42c6-af60-a96c5518ca71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704087970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2704087970
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.970330629
Short name T263
Test name
Test status
Simulation time 3186901876 ps
CPU time 100.77 seconds
Started Aug 16 06:14:31 PM PDT 24
Finished Aug 16 06:16:12 PM PDT 24
Peak memory 233008 kb
Host smart-28f0394a-c0df-4699-88f3-51919341b676
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970330629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.970330629
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1660743356
Short name T114
Test name
Test status
Simulation time 176261013 ps
CPU time 9.05 seconds
Started Aug 16 06:14:33 PM PDT 24
Finished Aug 16 06:14:42 PM PDT 24
Peak memory 211408 kb
Host smart-5239378c-3e91-48f4-9c5b-6f5fe4fa7d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660743356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1660743356
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.553036359
Short name T133
Test name
Test status
Simulation time 545079149 ps
CPU time 6.47 seconds
Started Aug 16 06:14:32 PM PDT 24
Finished Aug 16 06:14:39 PM PDT 24
Peak memory 211136 kb
Host smart-e80f3e48-346a-4dae-a797-7202aa1a1008
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=553036359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.553036359
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.715157899
Short name T23
Test name
Test status
Simulation time 314215231 ps
CPU time 51.66 seconds
Started Aug 16 06:14:32 PM PDT 24
Finished Aug 16 06:15:24 PM PDT 24
Peak memory 236176 kb
Host smart-f3007587-eef9-4085-9bef-3e375a79ff41
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715157899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.715157899
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3885146573
Short name T286
Test name
Test status
Simulation time 503328820 ps
CPU time 7.98 seconds
Started Aug 16 06:14:33 PM PDT 24
Finished Aug 16 06:14:41 PM PDT 24
Peak memory 211416 kb
Host smart-feb30cd0-89eb-43b4-bdf9-fc1b2455c4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885146573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3885146573
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3937781984
Short name T194
Test name
Test status
Simulation time 1547782109 ps
CPU time 23.62 seconds
Started Aug 16 06:14:32 PM PDT 24
Finished Aug 16 06:14:56 PM PDT 24
Peak memory 215212 kb
Host smart-fd6d55fc-5525-4442-93e5-013bab3b797a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937781984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3937781984
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2242618178
Short name T246
Test name
Test status
Simulation time 5588541115 ps
CPU time 43.43 seconds
Started Aug 16 06:14:31 PM PDT 24
Finished Aug 16 06:15:15 PM PDT 24
Peak memory 230872 kb
Host smart-08ef9b38-efcb-46f4-a846-e5c7791e56f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242618178 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2242618178
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.389610896
Short name T163
Test name
Test status
Simulation time 348956637 ps
CPU time 4.09 seconds
Started Aug 16 06:15:12 PM PDT 24
Finished Aug 16 06:15:17 PM PDT 24
Peak memory 210988 kb
Host smart-c58dfdc4-462a-489f-aa0c-e5c5acefcb0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389610896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.389610896
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.470003889
Short name T233
Test name
Test status
Simulation time 897751379 ps
CPU time 50.77 seconds
Started Aug 16 06:15:16 PM PDT 24
Finished Aug 16 06:16:07 PM PDT 24
Peak memory 235892 kb
Host smart-4ee0eaee-8f01-44b0-a02f-aa43b24da81a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470003889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.470003889
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.526974502
Short name T116
Test name
Test status
Simulation time 693833585 ps
CPU time 9.2 seconds
Started Aug 16 06:15:13 PM PDT 24
Finished Aug 16 06:15:22 PM PDT 24
Peak memory 211560 kb
Host smart-4dd6d8c8-e3c8-44d2-9aa5-40f4fa5d930c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526974502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.526974502
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2969196858
Short name T124
Test name
Test status
Simulation time 101439819 ps
CPU time 5.92 seconds
Started Aug 16 06:15:04 PM PDT 24
Finished Aug 16 06:15:10 PM PDT 24
Peak memory 211108 kb
Host smart-6d803691-81ab-44d5-ae4c-ac174f4fccc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2969196858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2969196858
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4003263919
Short name T287
Test name
Test status
Simulation time 5302350659 ps
CPU time 12.42 seconds
Started Aug 16 06:15:08 PM PDT 24
Finished Aug 16 06:15:21 PM PDT 24
Peak memory 211824 kb
Host smart-af0f59ca-cc64-40f0-9f93-6e0676ee254b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003263919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4003263919
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2209288574
Short name T343
Test name
Test status
Simulation time 5669760496 ps
CPU time 103.27 seconds
Started Aug 16 06:15:13 PM PDT 24
Finished Aug 16 06:16:56 PM PDT 24
Peak memory 223280 kb
Host smart-58766f2b-2e79-45a6-b7ee-7ce667dd39b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209288574 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2209288574
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1933560566
Short name T249
Test name
Test status
Simulation time 129250943 ps
CPU time 4.74 seconds
Started Aug 16 06:15:14 PM PDT 24
Finished Aug 16 06:15:19 PM PDT 24
Peak memory 211136 kb
Host smart-15d329e8-339a-4dcb-91e5-9a31ded85ac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933560566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1933560566
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2136824459
Short name T277
Test name
Test status
Simulation time 19818247010 ps
CPU time 143.32 seconds
Started Aug 16 06:15:16 PM PDT 24
Finished Aug 16 06:17:40 PM PDT 24
Peak memory 234040 kb
Host smart-f02065ae-730b-4ed1-9945-8987ccb90673
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136824459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2136824459
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1335524664
Short name T219
Test name
Test status
Simulation time 261228860 ps
CPU time 10.58 seconds
Started Aug 16 06:15:14 PM PDT 24
Finished Aug 16 06:15:25 PM PDT 24
Peak memory 211136 kb
Host smart-fcf85297-7b95-4275-97a5-c2eafeac81fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335524664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1335524664
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.359587960
Short name T285
Test name
Test status
Simulation time 440649510 ps
CPU time 5.21 seconds
Started Aug 16 06:15:16 PM PDT 24
Finished Aug 16 06:15:21 PM PDT 24
Peak memory 210424 kb
Host smart-7c1734f3-3ba8-409c-acb3-0f8a1d9cfdd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359587960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.359587960
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3333844311
Short name T337
Test name
Test status
Simulation time 2110904989 ps
CPU time 17.68 seconds
Started Aug 16 06:15:13 PM PDT 24
Finished Aug 16 06:15:31 PM PDT 24
Peak memory 215644 kb
Host smart-e9431361-1337-45a3-aabe-0fb5a02e1581
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333844311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3333844311
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4218286872
Short name T341
Test name
Test status
Simulation time 10730704846 ps
CPU time 92.27 seconds
Started Aug 16 06:15:16 PM PDT 24
Finished Aug 16 06:16:48 PM PDT 24
Peak memory 220624 kb
Host smart-c05852aa-c67b-45c8-9674-411d66b0cf8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218286872 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.4218286872
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2080217927
Short name T345
Test name
Test status
Simulation time 1973505969 ps
CPU time 6.78 seconds
Started Aug 16 06:15:12 PM PDT 24
Finished Aug 16 06:15:19 PM PDT 24
Peak memory 211060 kb
Host smart-219e25a8-ada2-485a-ba40-9626d276da9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080217927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2080217927
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.375836477
Short name T300
Test name
Test status
Simulation time 4731011710 ps
CPU time 147.26 seconds
Started Aug 16 06:15:12 PM PDT 24
Finished Aug 16 06:17:40 PM PDT 24
Peak memory 233656 kb
Host smart-8c3d4f7c-668c-4e04-8f2e-a9ac30b869ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375836477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.375836477
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3525749924
Short name T205
Test name
Test status
Simulation time 671024471 ps
CPU time 9.02 seconds
Started Aug 16 06:15:13 PM PDT 24
Finished Aug 16 06:15:22 PM PDT 24
Peak memory 211600 kb
Host smart-b0494c57-e104-4fb6-8d48-eb7e392ab6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525749924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3525749924
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2213024686
Short name T117
Test name
Test status
Simulation time 1706394769 ps
CPU time 6.3 seconds
Started Aug 16 06:15:17 PM PDT 24
Finished Aug 16 06:15:23 PM PDT 24
Peak memory 211032 kb
Host smart-5e28f455-9092-4871-b8f2-565d6b40c7fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2213024686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2213024686
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.146728038
Short name T293
Test name
Test status
Simulation time 741235639 ps
CPU time 9.02 seconds
Started Aug 16 06:15:14 PM PDT 24
Finished Aug 16 06:15:23 PM PDT 24
Peak memory 211632 kb
Host smart-f10f9364-eafa-4557-93bf-17ae5f93c91e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146728038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.146728038
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3563325709
Short name T354
Test name
Test status
Simulation time 13907451235 ps
CPU time 120.15 seconds
Started Aug 16 06:15:14 PM PDT 24
Finished Aug 16 06:17:15 PM PDT 24
Peak memory 222512 kb
Host smart-20e33f56-d326-4412-8727-6919c683a4d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563325709 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3563325709
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3918642920
Short name T270
Test name
Test status
Simulation time 88866955 ps
CPU time 4.05 seconds
Started Aug 16 06:15:17 PM PDT 24
Finished Aug 16 06:15:21 PM PDT 24
Peak memory 211084 kb
Host smart-bc3511d7-e96b-41f7-833e-2ebf33d08c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918642920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3918642920
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1138056442
Short name T348
Test name
Test status
Simulation time 2672620228 ps
CPU time 129.29 seconds
Started Aug 16 06:15:17 PM PDT 24
Finished Aug 16 06:17:26 PM PDT 24
Peak memory 232452 kb
Host smart-8b5493d2-32b8-4492-8cf0-905daf7cfb26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138056442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1138056442
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.175136813
Short name T267
Test name
Test status
Simulation time 4964532263 ps
CPU time 10.67 seconds
Started Aug 16 06:15:16 PM PDT 24
Finished Aug 16 06:15:26 PM PDT 24
Peak memory 211888 kb
Host smart-4370b271-603a-4f46-94f0-2b78de527a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175136813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.175136813
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1428408862
Short name T275
Test name
Test status
Simulation time 381308895 ps
CPU time 5.35 seconds
Started Aug 16 06:15:16 PM PDT 24
Finished Aug 16 06:15:22 PM PDT 24
Peak memory 211108 kb
Host smart-519f3cf6-e00c-4621-9b47-7ed46f8576bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1428408862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1428408862
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.668182789
Short name T131
Test name
Test status
Simulation time 490087107 ps
CPU time 19.3 seconds
Started Aug 16 06:15:16 PM PDT 24
Finished Aug 16 06:15:35 PM PDT 24
Peak memory 213908 kb
Host smart-37b2aab0-00e6-4356-ad14-98c8beed5a80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668182789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.668182789
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.774227476
Short name T137
Test name
Test status
Simulation time 3848790616 ps
CPU time 49.97 seconds
Started Aug 16 06:15:16 PM PDT 24
Finished Aug 16 06:16:06 PM PDT 24
Peak memory 222676 kb
Host smart-13351593-ec14-406e-b0b2-302be5b1ed0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774227476 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.774227476
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1569843694
Short name T235
Test name
Test status
Simulation time 10721856446 ps
CPU time 154.12 seconds
Started Aug 16 06:15:23 PM PDT 24
Finished Aug 16 06:17:57 PM PDT 24
Peak memory 232988 kb
Host smart-7ea359e5-7899-49d6-a28f-8f3e001fb280
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569843694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1569843694
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1720395582
Short name T238
Test name
Test status
Simulation time 204607020 ps
CPU time 9.09 seconds
Started Aug 16 06:15:23 PM PDT 24
Finished Aug 16 06:15:33 PM PDT 24
Peak memory 211528 kb
Host smart-398d1fe5-0473-416d-a2c7-ca651cb86bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720395582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1720395582
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.406237702
Short name T335
Test name
Test status
Simulation time 570425574 ps
CPU time 6.25 seconds
Started Aug 16 06:15:26 PM PDT 24
Finished Aug 16 06:15:32 PM PDT 24
Peak memory 211072 kb
Host smart-2059c57a-0b3b-4075-95e4-0f86893a7c6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=406237702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.406237702
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1871137782
Short name T349
Test name
Test status
Simulation time 300426424 ps
CPU time 15.98 seconds
Started Aug 16 06:15:25 PM PDT 24
Finished Aug 16 06:15:41 PM PDT 24
Peak memory 214980 kb
Host smart-6c990b64-f0c5-4ce6-aa77-1918ef64609c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871137782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1871137782
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.958700932
Short name T129
Test name
Test status
Simulation time 9504094772 ps
CPU time 406.51 seconds
Started Aug 16 06:15:23 PM PDT 24
Finished Aug 16 06:22:09 PM PDT 24
Peak memory 224900 kb
Host smart-70db7db1-25e5-4add-9e51-ebf02b41c6fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958700932 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.958700932
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.4171271424
Short name T350
Test name
Test status
Simulation time 347704909 ps
CPU time 4.14 seconds
Started Aug 16 06:15:22 PM PDT 24
Finished Aug 16 06:15:26 PM PDT 24
Peak memory 211072 kb
Host smart-36ceca7d-2215-41f6-91d6-7806fe8de80c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171271424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.4171271424
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3941587920
Short name T103
Test name
Test status
Simulation time 16575847229 ps
CPU time 65.15 seconds
Started Aug 16 06:15:23 PM PDT 24
Finished Aug 16 06:16:29 PM PDT 24
Peak memory 236720 kb
Host smart-b9c6af29-97b4-4ec8-abea-2d4d3959d2c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941587920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3941587920
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1589638272
Short name T167
Test name
Test status
Simulation time 362752983 ps
CPU time 10.49 seconds
Started Aug 16 06:15:23 PM PDT 24
Finished Aug 16 06:15:34 PM PDT 24
Peak memory 211108 kb
Host smart-234ed36b-f1f7-4959-874a-15f2ba1b5fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589638272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1589638272
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1492863402
Short name T52
Test name
Test status
Simulation time 560358968 ps
CPU time 5.83 seconds
Started Aug 16 06:15:23 PM PDT 24
Finished Aug 16 06:15:29 PM PDT 24
Peak memory 211136 kb
Host smart-969e7bdf-84ea-4f9d-bd5c-a3e202ffd8b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1492863402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1492863402
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.234309543
Short name T70
Test name
Test status
Simulation time 160780308 ps
CPU time 7.1 seconds
Started Aug 16 06:15:25 PM PDT 24
Finished Aug 16 06:15:32 PM PDT 24
Peak memory 212448 kb
Host smart-609cd581-424b-48cc-97f4-dbb68962bb77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234309543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.234309543
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1601195674
Short name T338
Test name
Test status
Simulation time 3569972956 ps
CPU time 70.28 seconds
Started Aug 16 06:15:21 PM PDT 24
Finished Aug 16 06:16:32 PM PDT 24
Peak memory 221184 kb
Host smart-50ee10ba-2524-47a2-8953-5fa54b56f5c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601195674 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1601195674
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1168510787
Short name T209
Test name
Test status
Simulation time 109226448 ps
CPU time 4.14 seconds
Started Aug 16 06:15:25 PM PDT 24
Finished Aug 16 06:15:29 PM PDT 24
Peak memory 211092 kb
Host smart-e4efed43-e11f-4ff2-b4fb-16c44bf18d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168510787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1168510787
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1797385674
Short name T147
Test name
Test status
Simulation time 5710203896 ps
CPU time 98.76 seconds
Started Aug 16 06:15:24 PM PDT 24
Finished Aug 16 06:17:03 PM PDT 24
Peak memory 236616 kb
Host smart-ef7751fb-dedb-43b9-ba70-23911f9088cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797385674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1797385674
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1727007719
Short name T317
Test name
Test status
Simulation time 172196667 ps
CPU time 9.18 seconds
Started Aug 16 06:15:22 PM PDT 24
Finished Aug 16 06:15:31 PM PDT 24
Peak memory 211404 kb
Host smart-a6f766f6-77e1-458a-a635-2f69efd53eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727007719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1727007719
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.536495167
Short name T195
Test name
Test status
Simulation time 777870203 ps
CPU time 5.92 seconds
Started Aug 16 06:15:25 PM PDT 24
Finished Aug 16 06:15:31 PM PDT 24
Peak memory 211152 kb
Host smart-94ac2a8e-2218-45f9-8034-0e14fb65da3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=536495167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.536495167
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2832426111
Short name T220
Test name
Test status
Simulation time 283524716 ps
CPU time 13.31 seconds
Started Aug 16 06:15:23 PM PDT 24
Finished Aug 16 06:15:37 PM PDT 24
Peak memory 214168 kb
Host smart-301b5fb3-7c5b-4091-a4fc-744564fa308b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832426111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2832426111
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1332250514
Short name T344
Test name
Test status
Simulation time 2337784905 ps
CPU time 6.93 seconds
Started Aug 16 06:15:22 PM PDT 24
Finished Aug 16 06:15:29 PM PDT 24
Peak memory 211180 kb
Host smart-b5a2b29a-0a5f-4b8c-ac98-1fd67c9879ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332250514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1332250514
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1969728622
Short name T231
Test name
Test status
Simulation time 11715484401 ps
CPU time 147.61 seconds
Started Aug 16 06:15:24 PM PDT 24
Finished Aug 16 06:17:52 PM PDT 24
Peak memory 233140 kb
Host smart-f1164bbf-4e0b-4893-ba28-94ec27f0a932
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969728622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1969728622
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1543905738
Short name T318
Test name
Test status
Simulation time 531150963 ps
CPU time 10.87 seconds
Started Aug 16 06:15:22 PM PDT 24
Finished Aug 16 06:15:33 PM PDT 24
Peak memory 211068 kb
Host smart-59a45699-4e29-468e-903b-e1caa4ad387c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543905738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1543905738
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.219300686
Short name T122
Test name
Test status
Simulation time 279808713 ps
CPU time 5.9 seconds
Started Aug 16 06:15:22 PM PDT 24
Finished Aug 16 06:15:28 PM PDT 24
Peak memory 211208 kb
Host smart-c3eb933a-9b12-4259-a0e6-17923896f3bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=219300686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.219300686
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3844459881
Short name T150
Test name
Test status
Simulation time 143233203 ps
CPU time 7.62 seconds
Started Aug 16 06:15:26 PM PDT 24
Finished Aug 16 06:15:34 PM PDT 24
Peak memory 211152 kb
Host smart-c64022f5-78b8-44e9-9cc0-1ccdaeded641
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844459881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3844459881
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3485216939
Short name T319
Test name
Test status
Simulation time 4793511101 ps
CPU time 58.46 seconds
Started Aug 16 06:15:26 PM PDT 24
Finished Aug 16 06:16:24 PM PDT 24
Peak memory 221820 kb
Host smart-24020406-b5f1-4635-a88c-4995e7727d5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485216939 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3485216939
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3902779673
Short name T149
Test name
Test status
Simulation time 348207263 ps
CPU time 4.02 seconds
Started Aug 16 06:15:23 PM PDT 24
Finished Aug 16 06:15:27 PM PDT 24
Peak memory 211136 kb
Host smart-cc081466-1dc0-4a2b-a8ce-a47da1de7dea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902779673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3902779673
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3773990694
Short name T237
Test name
Test status
Simulation time 15278521077 ps
CPU time 173.24 seconds
Started Aug 16 06:15:24 PM PDT 24
Finished Aug 16 06:18:18 PM PDT 24
Peak memory 234752 kb
Host smart-8ae13c79-28fc-4500-8f59-5d494ede562c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773990694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3773990694
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.684016780
Short name T307
Test name
Test status
Simulation time 169022680 ps
CPU time 9.33 seconds
Started Aug 16 06:15:24 PM PDT 24
Finished Aug 16 06:15:33 PM PDT 24
Peak memory 211516 kb
Host smart-d605d748-d293-4357-98b5-fd47c56e418f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684016780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.684016780
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2254041666
Short name T155
Test name
Test status
Simulation time 531205516 ps
CPU time 6.01 seconds
Started Aug 16 06:15:21 PM PDT 24
Finished Aug 16 06:15:27 PM PDT 24
Peak memory 211096 kb
Host smart-fdde7c8e-c0a5-4854-b1ab-af98bba7e27b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254041666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2254041666
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1625096055
Short name T191
Test name
Test status
Simulation time 954068965 ps
CPU time 14.77 seconds
Started Aug 16 06:15:21 PM PDT 24
Finished Aug 16 06:15:36 PM PDT 24
Peak memory 213720 kb
Host smart-b5bc3cbd-e779-42cc-a7f8-b318c073e3e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625096055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1625096055
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3711449805
Short name T47
Test name
Test status
Simulation time 4355089870 ps
CPU time 163.34 seconds
Started Aug 16 06:15:24 PM PDT 24
Finished Aug 16 06:18:07 PM PDT 24
Peak memory 221072 kb
Host smart-0c93891c-2bd3-455d-b010-5425e451a312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711449805 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3711449805
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2521532599
Short name T136
Test name
Test status
Simulation time 478376079 ps
CPU time 4.85 seconds
Started Aug 16 06:15:25 PM PDT 24
Finished Aug 16 06:15:30 PM PDT 24
Peak memory 210988 kb
Host smart-845330ea-262b-4729-a40d-2a961d526b31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521532599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2521532599
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3794327215
Short name T105
Test name
Test status
Simulation time 8505185229 ps
CPU time 73.12 seconds
Started Aug 16 06:15:22 PM PDT 24
Finished Aug 16 06:16:35 PM PDT 24
Peak memory 213540 kb
Host smart-6ecf1dc4-d987-4b73-a4f0-a48478e2654d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794327215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3794327215
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1862400628
Short name T135
Test name
Test status
Simulation time 930767417 ps
CPU time 9.08 seconds
Started Aug 16 06:15:26 PM PDT 24
Finished Aug 16 06:15:35 PM PDT 24
Peak memory 211436 kb
Host smart-bc0a1bb7-0bcf-4727-8a99-6cc9aedd5a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862400628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1862400628
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1154508061
Short name T126
Test name
Test status
Simulation time 137564231 ps
CPU time 6.17 seconds
Started Aug 16 06:15:25 PM PDT 24
Finished Aug 16 06:15:31 PM PDT 24
Peak memory 211124 kb
Host smart-a54be16f-ec42-4577-8e9d-934fbecb02ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1154508061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1154508061
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2677350497
Short name T7
Test name
Test status
Simulation time 132058548 ps
CPU time 7.81 seconds
Started Aug 16 06:15:26 PM PDT 24
Finished Aug 16 06:15:34 PM PDT 24
Peak memory 211176 kb
Host smart-5764aaa9-b9b9-442a-bd82-38f6a7e74690
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677350497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2677350497
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2954337363
Short name T14
Test name
Test status
Simulation time 4950627866 ps
CPU time 166.13 seconds
Started Aug 16 06:15:24 PM PDT 24
Finished Aug 16 06:18:11 PM PDT 24
Peak memory 220864 kb
Host smart-9a6bea8a-2b02-45f8-9ad6-88b95786520b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954337363 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2954337363
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2610739594
Short name T158
Test name
Test status
Simulation time 492718558 ps
CPU time 4.06 seconds
Started Aug 16 06:14:39 PM PDT 24
Finished Aug 16 06:14:43 PM PDT 24
Peak memory 211064 kb
Host smart-b468a2a7-8b51-4b5f-a07e-1875d3edc6bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610739594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2610739594
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1370210301
Short name T187
Test name
Test status
Simulation time 9991317276 ps
CPU time 113.84 seconds
Started Aug 16 06:14:32 PM PDT 24
Finished Aug 16 06:16:26 PM PDT 24
Peak memory 237708 kb
Host smart-a350da74-a301-4416-b7da-11711ea8d207
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370210301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1370210301
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.320030097
Short name T306
Test name
Test status
Simulation time 350145714 ps
CPU time 9.21 seconds
Started Aug 16 06:14:32 PM PDT 24
Finished Aug 16 06:14:41 PM PDT 24
Peak memory 211668 kb
Host smart-6f2292b5-19e1-421d-974b-b055ea438c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320030097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.320030097
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1074997795
Short name T154
Test name
Test status
Simulation time 499516324 ps
CPU time 7.62 seconds
Started Aug 16 06:14:32 PM PDT 24
Finished Aug 16 06:14:39 PM PDT 24
Peak memory 211044 kb
Host smart-8b1e1369-66de-4905-9d13-c19feb87e443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074997795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1074997795
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.407547603
Short name T22
Test name
Test status
Simulation time 168223573 ps
CPU time 52.87 seconds
Started Aug 16 06:14:39 PM PDT 24
Finished Aug 16 06:15:32 PM PDT 24
Peak memory 236648 kb
Host smart-e73daae1-d51b-4482-8010-1f1d218570b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407547603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.407547603
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.18591229
Short name T313
Test name
Test status
Simulation time 143591867 ps
CPU time 6.33 seconds
Started Aug 16 06:14:33 PM PDT 24
Finished Aug 16 06:14:39 PM PDT 24
Peak memory 211148 kb
Host smart-6e29650a-1fb7-41d4-a1f9-a9dcbad4e310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18591229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.18591229
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.4194920767
Short name T221
Test name
Test status
Simulation time 4129840511 ps
CPU time 13.67 seconds
Started Aug 16 06:14:29 PM PDT 24
Finished Aug 16 06:14:43 PM PDT 24
Peak memory 213768 kb
Host smart-41e5c6f6-cdc0-4e8a-a94b-8dfb509621b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194920767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.4194920767
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1843125378
Short name T240
Test name
Test status
Simulation time 1134612794 ps
CPU time 43.31 seconds
Started Aug 16 06:14:34 PM PDT 24
Finished Aug 16 06:15:17 PM PDT 24
Peak memory 219264 kb
Host smart-d558542e-c0e8-41f5-9af6-a7d560d02b00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843125378 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1843125378
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.994480187
Short name T294
Test name
Test status
Simulation time 547924723 ps
CPU time 4.91 seconds
Started Aug 16 06:15:26 PM PDT 24
Finished Aug 16 06:15:31 PM PDT 24
Peak memory 211112 kb
Host smart-ea61e595-e797-47df-99df-f2df19595473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994480187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.994480187
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.663693566
Short name T33
Test name
Test status
Simulation time 19468448226 ps
CPU time 88.83 seconds
Started Aug 16 06:15:24 PM PDT 24
Finished Aug 16 06:16:53 PM PDT 24
Peak memory 237660 kb
Host smart-c5cf1774-f5a9-4ace-a471-88e278a7d9ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663693566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.663693566
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1513906254
Short name T234
Test name
Test status
Simulation time 582322756 ps
CPU time 10.62 seconds
Started Aug 16 06:15:27 PM PDT 24
Finished Aug 16 06:15:38 PM PDT 24
Peak memory 211640 kb
Host smart-c61c6092-010e-41ad-a9b6-2f020dfea9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513906254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1513906254
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1543532192
Short name T331
Test name
Test status
Simulation time 399263205 ps
CPU time 5.48 seconds
Started Aug 16 06:15:26 PM PDT 24
Finished Aug 16 06:15:32 PM PDT 24
Peak memory 211124 kb
Host smart-c3cac7d1-3857-4483-86c6-a104a22cbd28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1543532192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1543532192
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3518186189
Short name T134
Test name
Test status
Simulation time 1240839050 ps
CPU time 18.39 seconds
Started Aug 16 06:15:27 PM PDT 24
Finished Aug 16 06:15:45 PM PDT 24
Peak memory 214104 kb
Host smart-19ad085c-8848-4514-ba07-14cb478f9025
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518186189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3518186189
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3752667935
Short name T325
Test name
Test status
Simulation time 8827949428 ps
CPU time 80.6 seconds
Started Aug 16 06:15:26 PM PDT 24
Finished Aug 16 06:16:47 PM PDT 24
Peak memory 221876 kb
Host smart-3609b248-c7e1-46bc-980e-b45e0963b042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752667935 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3752667935
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3785927961
Short name T333
Test name
Test status
Simulation time 168654078 ps
CPU time 3.88 seconds
Started Aug 16 06:15:27 PM PDT 24
Finished Aug 16 06:15:31 PM PDT 24
Peak memory 211060 kb
Host smart-4e23920c-0dc3-4662-b550-0b92db6d6f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785927961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3785927961
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1540792299
Short name T148
Test name
Test status
Simulation time 4644711526 ps
CPU time 78.51 seconds
Started Aug 16 06:15:24 PM PDT 24
Finished Aug 16 06:16:43 PM PDT 24
Peak memory 237724 kb
Host smart-302d3f0a-ac47-4e4d-8ed8-0f5b8a6e4d39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540792299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1540792299
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2014718959
Short name T268
Test name
Test status
Simulation time 252869896 ps
CPU time 10.53 seconds
Started Aug 16 06:15:28 PM PDT 24
Finished Aug 16 06:15:38 PM PDT 24
Peak memory 211616 kb
Host smart-1fbdaa4c-d109-4627-9191-58e1bfdc10f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014718959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2014718959
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3572110013
Short name T30
Test name
Test status
Simulation time 190659269 ps
CPU time 5.52 seconds
Started Aug 16 06:15:25 PM PDT 24
Finished Aug 16 06:15:31 PM PDT 24
Peak memory 211096 kb
Host smart-c8969f03-4fc9-44ea-9bad-3cc5b294a1b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572110013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3572110013
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2618107560
Short name T309
Test name
Test status
Simulation time 585864528 ps
CPU time 16.83 seconds
Started Aug 16 06:15:28 PM PDT 24
Finished Aug 16 06:15:45 PM PDT 24
Peak memory 214344 kb
Host smart-73de5bff-c7ca-4dfb-9e6b-81d7cdce1fa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618107560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2618107560
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2220677947
Short name T108
Test name
Test status
Simulation time 20116956318 ps
CPU time 302.77 seconds
Started Aug 16 06:15:28 PM PDT 24
Finished Aug 16 06:20:30 PM PDT 24
Peak memory 234624 kb
Host smart-94fc129d-171a-4b9e-9faa-913a69a2c9fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220677947 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2220677947
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3537853417
Short name T166
Test name
Test status
Simulation time 127409846 ps
CPU time 4.8 seconds
Started Aug 16 06:15:24 PM PDT 24
Finished Aug 16 06:15:29 PM PDT 24
Peak memory 211140 kb
Host smart-0da7723d-c1eb-4171-b9e6-91357401f478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537853417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3537853417
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1145801016
Short name T346
Test name
Test status
Simulation time 39344275368 ps
CPU time 142.55 seconds
Started Aug 16 06:15:24 PM PDT 24
Finished Aug 16 06:17:46 PM PDT 24
Peak memory 233556 kb
Host smart-19439b12-c8dc-4b4e-969b-fb519cb6cb15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145801016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1145801016
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2423776979
Short name T165
Test name
Test status
Simulation time 261778622 ps
CPU time 10.75 seconds
Started Aug 16 06:15:26 PM PDT 24
Finished Aug 16 06:15:37 PM PDT 24
Peak memory 211140 kb
Host smart-16b5384e-68bc-4083-894c-fae3f87766fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423776979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2423776979
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3767329248
Short name T326
Test name
Test status
Simulation time 143894147 ps
CPU time 6.08 seconds
Started Aug 16 06:15:24 PM PDT 24
Finished Aug 16 06:15:30 PM PDT 24
Peak memory 211120 kb
Host smart-e2c5be5b-636b-404d-8453-ff4c9683a8f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3767329248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3767329248
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.542217243
Short name T119
Test name
Test status
Simulation time 299758083 ps
CPU time 15.08 seconds
Started Aug 16 06:15:26 PM PDT 24
Finished Aug 16 06:15:41 PM PDT 24
Peak memory 215660 kb
Host smart-bab7ea33-ae0c-4b95-9114-6530d7862843
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542217243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.542217243
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.239766496
Short name T188
Test name
Test status
Simulation time 13134828977 ps
CPU time 128.51 seconds
Started Aug 16 06:15:28 PM PDT 24
Finished Aug 16 06:17:36 PM PDT 24
Peak memory 221980 kb
Host smart-a30d3dd7-51b7-4b26-b273-17ca687a15f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239766496 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.239766496
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1204177677
Short name T262
Test name
Test status
Simulation time 270372941 ps
CPU time 4.9 seconds
Started Aug 16 06:15:33 PM PDT 24
Finished Aug 16 06:15:38 PM PDT 24
Peak memory 211116 kb
Host smart-abb1e6bb-28e1-435d-9c14-0c7148a72359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204177677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1204177677
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2173513140
Short name T156
Test name
Test status
Simulation time 121127651093 ps
CPU time 252.35 seconds
Started Aug 16 06:15:34 PM PDT 24
Finished Aug 16 06:19:46 PM PDT 24
Peak memory 237612 kb
Host smart-8218cde2-5965-4e4c-ade7-b9c081c6c428
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173513140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2173513140
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1583216793
Short name T24
Test name
Test status
Simulation time 694097450 ps
CPU time 9.52 seconds
Started Aug 16 06:15:31 PM PDT 24
Finished Aug 16 06:15:41 PM PDT 24
Peak memory 211512 kb
Host smart-14bfc1ef-2ad3-48f0-840f-e2c84bd698e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583216793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1583216793
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1291062757
Short name T3
Test name
Test status
Simulation time 279211096 ps
CPU time 5.99 seconds
Started Aug 16 06:15:33 PM PDT 24
Finished Aug 16 06:15:39 PM PDT 24
Peak memory 211152 kb
Host smart-190e1d1a-ec22-415a-8f31-a8fe2e748c7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291062757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1291062757
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1999190992
Short name T352
Test name
Test status
Simulation time 1079787693 ps
CPU time 11.39 seconds
Started Aug 16 06:15:27 PM PDT 24
Finished Aug 16 06:15:38 PM PDT 24
Peak memory 213636 kb
Host smart-35f779e2-3d25-4e59-9eeb-d5fb29422b90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999190992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1999190992
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3017189207
Short name T49
Test name
Test status
Simulation time 4093721990 ps
CPU time 89.64 seconds
Started Aug 16 06:15:31 PM PDT 24
Finished Aug 16 06:17:01 PM PDT 24
Peak memory 222248 kb
Host smart-ab0ac509-f72e-46cd-ae2e-f8af9acd0f72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017189207 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3017189207
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1402184515
Short name T258
Test name
Test status
Simulation time 336322193 ps
CPU time 4.14 seconds
Started Aug 16 06:15:33 PM PDT 24
Finished Aug 16 06:15:38 PM PDT 24
Peak memory 211124 kb
Host smart-4b486aa4-3569-4c02-ae99-673c37b7a94d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402184515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1402184515
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3042930870
Short name T355
Test name
Test status
Simulation time 3654445935 ps
CPU time 180.51 seconds
Started Aug 16 06:15:32 PM PDT 24
Finished Aug 16 06:18:33 PM PDT 24
Peak memory 233636 kb
Host smart-342d0b54-7655-4525-8a71-a6ff58a73b5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042930870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3042930870
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3190578844
Short name T121
Test name
Test status
Simulation time 251495184 ps
CPU time 10.31 seconds
Started Aug 16 06:15:38 PM PDT 24
Finished Aug 16 06:15:49 PM PDT 24
Peak memory 211152 kb
Host smart-286283a9-a0f6-4968-9d2d-48d0df1c8714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190578844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3190578844
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.360923865
Short name T142
Test name
Test status
Simulation time 109172416 ps
CPU time 5.38 seconds
Started Aug 16 06:15:29 PM PDT 24
Finished Aug 16 06:15:35 PM PDT 24
Peak memory 211064 kb
Host smart-e1f6cc96-374f-40af-bcbf-a722288f66cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=360923865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.360923865
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1584665886
Short name T241
Test name
Test status
Simulation time 1324682355 ps
CPU time 16.76 seconds
Started Aug 16 06:15:34 PM PDT 24
Finished Aug 16 06:15:51 PM PDT 24
Peak memory 213688 kb
Host smart-ff883313-58b7-47ad-bab2-68d22719a475
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584665886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1584665886
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.193593128
Short name T210
Test name
Test status
Simulation time 2059151478 ps
CPU time 6.93 seconds
Started Aug 16 06:15:32 PM PDT 24
Finished Aug 16 06:15:39 PM PDT 24
Peak memory 211140 kb
Host smart-de9e9b47-493a-4c26-8ad5-ef1a9e3e54ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193593128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.193593128
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4188316043
Short name T40
Test name
Test status
Simulation time 32240031094 ps
CPU time 117.36 seconds
Started Aug 16 06:15:33 PM PDT 24
Finished Aug 16 06:17:31 PM PDT 24
Peak memory 228464 kb
Host smart-71978907-7f12-4a1c-8e76-5a561b7cf573
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188316043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4188316043
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2135859877
Short name T123
Test name
Test status
Simulation time 176236227 ps
CPU time 9.01 seconds
Started Aug 16 06:15:33 PM PDT 24
Finished Aug 16 06:15:42 PM PDT 24
Peak memory 211600 kb
Host smart-3c7fc73a-ade6-49fd-9948-bce6fc02b5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135859877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2135859877
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3185498176
Short name T340
Test name
Test status
Simulation time 563328193 ps
CPU time 5.98 seconds
Started Aug 16 06:15:34 PM PDT 24
Finished Aug 16 06:15:40 PM PDT 24
Peak memory 211132 kb
Host smart-4de0da4f-4551-468c-9515-51c0bbae6b62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3185498176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3185498176
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2961706037
Short name T329
Test name
Test status
Simulation time 1309491268 ps
CPU time 15.74 seconds
Started Aug 16 06:15:32 PM PDT 24
Finished Aug 16 06:15:47 PM PDT 24
Peak memory 214488 kb
Host smart-5b44ee14-9bcf-43ce-88e5-aa527d2c2938
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961706037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2961706037
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1999771339
Short name T53
Test name
Test status
Simulation time 9390056580 ps
CPU time 301.95 seconds
Started Aug 16 06:15:33 PM PDT 24
Finished Aug 16 06:20:35 PM PDT 24
Peak memory 224788 kb
Host smart-1181dc90-d2cb-428d-9f4f-b112b24aee95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999771339 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1999771339
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2734677273
Short name T311
Test name
Test status
Simulation time 1186331648 ps
CPU time 4.04 seconds
Started Aug 16 06:15:34 PM PDT 24
Finished Aug 16 06:15:38 PM PDT 24
Peak memory 210472 kb
Host smart-0df995b0-cd73-4c7b-b3ff-4a55aa5f09a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734677273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2734677273
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.20131509
Short name T269
Test name
Test status
Simulation time 24539564727 ps
CPU time 140.88 seconds
Started Aug 16 06:15:34 PM PDT 24
Finished Aug 16 06:17:55 PM PDT 24
Peak memory 224152 kb
Host smart-015ebd45-4866-480e-8976-39e05a993695
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20131509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_co
rrupt_sig_fatal_chk.20131509
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2421442456
Short name T118
Test name
Test status
Simulation time 511964118 ps
CPU time 10.43 seconds
Started Aug 16 06:15:33 PM PDT 24
Finished Aug 16 06:15:44 PM PDT 24
Peak memory 211076 kb
Host smart-4f51db2a-40a9-4afc-ac93-5438a0e0a926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421442456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2421442456
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1256699319
Short name T176
Test name
Test status
Simulation time 420440846 ps
CPU time 5.67 seconds
Started Aug 16 06:15:32 PM PDT 24
Finished Aug 16 06:15:38 PM PDT 24
Peak memory 211096 kb
Host smart-9e36194f-9a69-43b3-a5c8-eab7e81bc314
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1256699319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1256699319
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2601789645
Short name T141
Test name
Test status
Simulation time 1102192205 ps
CPU time 11.59 seconds
Started Aug 16 06:15:32 PM PDT 24
Finished Aug 16 06:15:44 PM PDT 24
Peak memory 214736 kb
Host smart-320cb73a-6d7b-4be8-983f-7a5d98e14fb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601789645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2601789645
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1842177560
Short name T177
Test name
Test status
Simulation time 3104706566 ps
CPU time 192.43 seconds
Started Aug 16 06:15:30 PM PDT 24
Finished Aug 16 06:18:43 PM PDT 24
Peak memory 227556 kb
Host smart-c7445de1-d74b-4b06-b397-b3f3b566addb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842177560 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1842177560
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1432899280
Short name T113
Test name
Test status
Simulation time 267129359 ps
CPU time 4.8 seconds
Started Aug 16 06:15:30 PM PDT 24
Finished Aug 16 06:15:35 PM PDT 24
Peak memory 211120 kb
Host smart-42909e73-59b7-493f-b9f1-4fde4e64d59b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432899280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1432899280
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3479011206
Short name T169
Test name
Test status
Simulation time 522283723 ps
CPU time 10.74 seconds
Started Aug 16 06:15:33 PM PDT 24
Finished Aug 16 06:15:44 PM PDT 24
Peak memory 211136 kb
Host smart-2d429fdf-3091-4235-a870-445c2d883660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479011206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3479011206
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2165201135
Short name T315
Test name
Test status
Simulation time 540713857 ps
CPU time 6.14 seconds
Started Aug 16 06:15:33 PM PDT 24
Finished Aug 16 06:15:39 PM PDT 24
Peak memory 211076 kb
Host smart-85e71ba6-6c92-4711-b58b-a34c4cc59639
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2165201135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2165201135
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.129090144
Short name T192
Test name
Test status
Simulation time 302273769 ps
CPU time 6.33 seconds
Started Aug 16 06:15:33 PM PDT 24
Finished Aug 16 06:15:39 PM PDT 24
Peak memory 211164 kb
Host smart-b1e8f1e8-d355-4b39-9d79-0a01abe1d455
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129090144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.129090144
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3761461280
Short name T295
Test name
Test status
Simulation time 148003061 ps
CPU time 5.02 seconds
Started Aug 16 06:15:32 PM PDT 24
Finished Aug 16 06:15:37 PM PDT 24
Peak memory 211092 kb
Host smart-d857e456-ff81-4a10-9278-06b4c4f86e22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761461280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3761461280
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3433192045
Short name T203
Test name
Test status
Simulation time 7126587093 ps
CPU time 123.26 seconds
Started Aug 16 06:15:34 PM PDT 24
Finished Aug 16 06:17:38 PM PDT 24
Peak memory 237056 kb
Host smart-d4e666c0-09f8-4182-8237-d8dfc8d63122
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433192045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3433192045
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2028512433
Short name T213
Test name
Test status
Simulation time 1131352496 ps
CPU time 10.66 seconds
Started Aug 16 06:15:33 PM PDT 24
Finished Aug 16 06:15:44 PM PDT 24
Peak memory 211508 kb
Host smart-a2d26527-759d-4ecd-b1c5-cff86fcf7710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028512433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2028512433
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4210786262
Short name T308
Test name
Test status
Simulation time 488942900 ps
CPU time 6.23 seconds
Started Aug 16 06:15:32 PM PDT 24
Finished Aug 16 06:15:38 PM PDT 24
Peak memory 211084 kb
Host smart-ff4818eb-f41b-4a08-a388-5e620e0fb174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4210786262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4210786262
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3712063309
Short name T229
Test name
Test status
Simulation time 246212292 ps
CPU time 11.48 seconds
Started Aug 16 06:15:36 PM PDT 24
Finished Aug 16 06:15:48 PM PDT 24
Peak memory 213824 kb
Host smart-e5f3cbd7-dde4-491e-8e4a-ca173e465a7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712063309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3712063309
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.841881300
Short name T151
Test name
Test status
Simulation time 3875734728 ps
CPU time 134.98 seconds
Started Aug 16 06:15:38 PM PDT 24
Finished Aug 16 06:17:53 PM PDT 24
Peak memory 223628 kb
Host smart-7ca28d88-1c53-48e9-a430-025a647b61c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841881300 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.841881300
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3972622274
Short name T198
Test name
Test status
Simulation time 90804870 ps
CPU time 4.06 seconds
Started Aug 16 06:15:38 PM PDT 24
Finished Aug 16 06:15:43 PM PDT 24
Peak memory 211136 kb
Host smart-196c57bb-840a-4f84-9bb0-0bc09366bbc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972622274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3972622274
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3402944141
Short name T41
Test name
Test status
Simulation time 2898460723 ps
CPU time 131.82 seconds
Started Aug 16 06:15:31 PM PDT 24
Finished Aug 16 06:17:43 PM PDT 24
Peak memory 237680 kb
Host smart-f87c9d74-47cb-41c1-83ad-0e9cf39408bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402944141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3402944141
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3787250976
Short name T228
Test name
Test status
Simulation time 1511149523 ps
CPU time 8.97 seconds
Started Aug 16 06:15:31 PM PDT 24
Finished Aug 16 06:15:40 PM PDT 24
Peak memory 211436 kb
Host smart-dc2deb7f-eb1a-490a-98a0-f8c40013ddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787250976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3787250976
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3261537917
Short name T347
Test name
Test status
Simulation time 193383796 ps
CPU time 5.82 seconds
Started Aug 16 06:15:31 PM PDT 24
Finished Aug 16 06:15:37 PM PDT 24
Peak memory 211004 kb
Host smart-0fcda160-b106-4218-9565-ea19e67f3ee3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261537917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3261537917
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2248384069
Short name T322
Test name
Test status
Simulation time 435080319 ps
CPU time 21.21 seconds
Started Aug 16 06:15:33 PM PDT 24
Finished Aug 16 06:15:54 PM PDT 24
Peak memory 215480 kb
Host smart-27e01d53-c549-4005-bb40-949a9cf86d7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248384069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2248384069
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3167962623
Short name T302
Test name
Test status
Simulation time 16587603010 ps
CPU time 157.44 seconds
Started Aug 16 06:15:34 PM PDT 24
Finished Aug 16 06:18:11 PM PDT 24
Peak memory 225256 kb
Host smart-a8422b8e-1eed-46f2-9708-9f1571cce46b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167962623 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.3167962623
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2590926623
Short name T5
Test name
Test status
Simulation time 85695268 ps
CPU time 4.08 seconds
Started Aug 16 06:14:40 PM PDT 24
Finished Aug 16 06:14:44 PM PDT 24
Peak memory 211064 kb
Host smart-7ada9e98-206d-489b-88fc-19d0c3d864c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590926623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2590926623
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3328798327
Short name T248
Test name
Test status
Simulation time 1642493953 ps
CPU time 52.55 seconds
Started Aug 16 06:14:39 PM PDT 24
Finished Aug 16 06:15:32 PM PDT 24
Peak memory 227704 kb
Host smart-e2ced1ef-e4b6-43f3-9e47-538d44f24f66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328798327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3328798327
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1740158867
Short name T289
Test name
Test status
Simulation time 999606331 ps
CPU time 11.27 seconds
Started Aug 16 06:14:40 PM PDT 24
Finished Aug 16 06:14:51 PM PDT 24
Peak memory 211440 kb
Host smart-4f81af35-4e4a-456e-974e-72da61acc290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740158867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1740158867
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2210071314
Short name T254
Test name
Test status
Simulation time 522558756 ps
CPU time 5.14 seconds
Started Aug 16 06:14:43 PM PDT 24
Finished Aug 16 06:14:49 PM PDT 24
Peak memory 211132 kb
Host smart-5488f609-28e2-4bc8-95d4-b34ecef042fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2210071314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2210071314
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3879126840
Short name T28
Test name
Test status
Simulation time 3697954769 ps
CPU time 95.91 seconds
Started Aug 16 06:14:39 PM PDT 24
Finished Aug 16 06:16:15 PM PDT 24
Peak memory 236796 kb
Host smart-1e6e3c8e-f667-42c4-bef6-a4afb33d5f99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879126840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3879126840
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2869284957
Short name T146
Test name
Test status
Simulation time 525854032 ps
CPU time 6.01 seconds
Started Aug 16 06:14:39 PM PDT 24
Finished Aug 16 06:14:46 PM PDT 24
Peak memory 211144 kb
Host smart-85fd48ec-19a1-447e-ba34-1e8816f880a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869284957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2869284957
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2465854936
Short name T323
Test name
Test status
Simulation time 89438710 ps
CPU time 6.59 seconds
Started Aug 16 06:14:43 PM PDT 24
Finished Aug 16 06:14:50 PM PDT 24
Peak memory 210880 kb
Host smart-5dc2ce4e-5feb-4886-8871-6383d015990e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465854936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2465854936
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2212538232
Short name T145
Test name
Test status
Simulation time 5566071629 ps
CPU time 220.18 seconds
Started Aug 16 06:14:43 PM PDT 24
Finished Aug 16 06:18:23 PM PDT 24
Peak memory 224892 kb
Host smart-c663f06f-a0b5-4a3e-a640-9d89af903b45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212538232 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2212538232
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2854615337
Short name T207
Test name
Test status
Simulation time 250105713 ps
CPU time 4.76 seconds
Started Aug 16 06:15:38 PM PDT 24
Finished Aug 16 06:15:43 PM PDT 24
Peak memory 211136 kb
Host smart-f6e9f700-b8a2-4c59-bad1-aacfe18b6743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854615337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2854615337
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4040231029
Short name T193
Test name
Test status
Simulation time 2580767296 ps
CPU time 120.05 seconds
Started Aug 16 06:15:37 PM PDT 24
Finished Aug 16 06:17:37 PM PDT 24
Peak memory 236600 kb
Host smart-0a971e42-bfd8-43b0-9ba0-bc7e940b38ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040231029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4040231029
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1166166692
Short name T351
Test name
Test status
Simulation time 521806778 ps
CPU time 10.53 seconds
Started Aug 16 06:15:33 PM PDT 24
Finished Aug 16 06:15:43 PM PDT 24
Peak memory 211500 kb
Host smart-169ae7d1-67d3-4a3a-9e74-949b1017d89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166166692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1166166692
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2427812609
Short name T291
Test name
Test status
Simulation time 256138901 ps
CPU time 5.29 seconds
Started Aug 16 06:15:31 PM PDT 24
Finished Aug 16 06:15:37 PM PDT 24
Peak memory 211132 kb
Host smart-a7def90b-d6d8-45b5-8416-c09fe3b32ccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2427812609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2427812609
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2881695161
Short name T292
Test name
Test status
Simulation time 155326529 ps
CPU time 7.87 seconds
Started Aug 16 06:15:33 PM PDT 24
Finished Aug 16 06:15:41 PM PDT 24
Peak memory 211112 kb
Host smart-33ee581d-7639-468d-8d5b-b9c7a15015bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881695161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2881695161
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2976403707
Short name T112
Test name
Test status
Simulation time 15012374127 ps
CPU time 231.13 seconds
Started Aug 16 06:15:37 PM PDT 24
Finished Aug 16 06:19:28 PM PDT 24
Peak memory 232424 kb
Host smart-94a62b31-40a9-4944-9a71-d114eb299091
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976403707 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2976403707
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1991772229
Short name T48
Test name
Test status
Simulation time 251379303 ps
CPU time 4.8 seconds
Started Aug 16 06:15:43 PM PDT 24
Finished Aug 16 06:15:48 PM PDT 24
Peak memory 211132 kb
Host smart-8670ded7-b918-46e0-8937-3e0c3d8a185a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991772229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1991772229
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3254285731
Short name T316
Test name
Test status
Simulation time 3587000795 ps
CPU time 92.43 seconds
Started Aug 16 06:15:42 PM PDT 24
Finished Aug 16 06:17:14 PM PDT 24
Peak memory 236628 kb
Host smart-8cc6e1ae-529b-4d55-910e-663a6d23ba94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254285731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3254285731
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.490404036
Short name T299
Test name
Test status
Simulation time 522040912 ps
CPU time 10.43 seconds
Started Aug 16 06:15:41 PM PDT 24
Finished Aug 16 06:15:51 PM PDT 24
Peak memory 211152 kb
Host smart-a54ac724-17b7-4590-9443-ab493022fe04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490404036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.490404036
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1245423828
Short name T304
Test name
Test status
Simulation time 522358508 ps
CPU time 7.66 seconds
Started Aug 16 06:15:38 PM PDT 24
Finished Aug 16 06:15:46 PM PDT 24
Peak memory 211128 kb
Host smart-a467b988-3603-4567-89a7-3363b3f13a31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1245423828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1245423828
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4037583394
Short name T296
Test name
Test status
Simulation time 1057016410 ps
CPU time 18.06 seconds
Started Aug 16 06:15:31 PM PDT 24
Finished Aug 16 06:15:50 PM PDT 24
Peak memory 213648 kb
Host smart-361736af-f182-4c1e-b42a-226f5aeeee9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037583394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4037583394
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3716469360
Short name T45
Test name
Test status
Simulation time 7166755332 ps
CPU time 148.3 seconds
Started Aug 16 06:15:42 PM PDT 24
Finished Aug 16 06:18:11 PM PDT 24
Peak memory 229984 kb
Host smart-1d303308-054d-417a-a51c-9d417c373629
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716469360 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3716469360
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3788829571
Short name T44
Test name
Test status
Simulation time 89879907 ps
CPU time 4.18 seconds
Started Aug 16 06:15:42 PM PDT 24
Finished Aug 16 06:15:46 PM PDT 24
Peak memory 211132 kb
Host smart-f15625bd-135c-4d88-bcd4-a6907fc20bc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788829571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3788829571
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1254866823
Short name T39
Test name
Test status
Simulation time 2539705355 ps
CPU time 154.43 seconds
Started Aug 16 06:15:43 PM PDT 24
Finished Aug 16 06:18:18 PM PDT 24
Peak memory 233628 kb
Host smart-fc38185b-2ba2-4d28-9531-ca8774de2425
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254866823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1254866823
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.717075536
Short name T261
Test name
Test status
Simulation time 175748336 ps
CPU time 8.91 seconds
Started Aug 16 06:15:41 PM PDT 24
Finished Aug 16 06:15:50 PM PDT 24
Peak memory 211640 kb
Host smart-b4f03633-31f6-4c7c-88d2-c1dade7f3107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717075536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.717075536
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3353391944
Short name T259
Test name
Test status
Simulation time 110000047 ps
CPU time 5.29 seconds
Started Aug 16 06:15:46 PM PDT 24
Finished Aug 16 06:15:51 PM PDT 24
Peak memory 211008 kb
Host smart-ea3138a2-ef01-41e6-b369-de35b78634a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3353391944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3353391944
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3773642251
Short name T171
Test name
Test status
Simulation time 274922648 ps
CPU time 15.88 seconds
Started Aug 16 06:15:41 PM PDT 24
Finished Aug 16 06:15:57 PM PDT 24
Peak memory 213980 kb
Host smart-f2d73289-2320-4689-b664-4157139b3b0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773642251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3773642251
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1186043312
Short name T223
Test name
Test status
Simulation time 3465173768 ps
CPU time 139.8 seconds
Started Aug 16 06:15:41 PM PDT 24
Finished Aug 16 06:18:01 PM PDT 24
Peak memory 231208 kb
Host smart-7ed984aa-c2bb-4c6f-9a90-942cf58c13d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186043312 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1186043312
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1492443823
Short name T298
Test name
Test status
Simulation time 87354529 ps
CPU time 4.24 seconds
Started Aug 16 06:15:43 PM PDT 24
Finished Aug 16 06:15:48 PM PDT 24
Peak memory 211092 kb
Host smart-ffac45cb-af0e-40f4-8eef-37c39b71b1e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492443823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1492443823
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1634827772
Short name T175
Test name
Test status
Simulation time 20507703265 ps
CPU time 118.01 seconds
Started Aug 16 06:15:42 PM PDT 24
Finished Aug 16 06:17:40 PM PDT 24
Peak memory 233068 kb
Host smart-2effe8be-55ca-4348-b774-d682dce134e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634827772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1634827772
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3721118467
Short name T255
Test name
Test status
Simulation time 336460286 ps
CPU time 8.8 seconds
Started Aug 16 06:15:46 PM PDT 24
Finished Aug 16 06:15:55 PM PDT 24
Peak memory 211384 kb
Host smart-0ee975e5-95c8-4641-a4e0-cae30a74fb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721118467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3721118467
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.435052323
Short name T34
Test name
Test status
Simulation time 93486532 ps
CPU time 5.12 seconds
Started Aug 16 06:15:42 PM PDT 24
Finished Aug 16 06:15:47 PM PDT 24
Peak memory 211144 kb
Host smart-00754b76-6307-4abe-a1af-b882558a2289
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=435052323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.435052323
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1792883175
Short name T301
Test name
Test status
Simulation time 568271107 ps
CPU time 11.9 seconds
Started Aug 16 06:15:45 PM PDT 24
Finished Aug 16 06:15:57 PM PDT 24
Peak memory 213864 kb
Host smart-d8d7c9b0-8168-4698-8dc7-6c1ada6f5db0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792883175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1792883175
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1073001933
Short name T110
Test name
Test status
Simulation time 12754711276 ps
CPU time 186.36 seconds
Started Aug 16 06:15:42 PM PDT 24
Finished Aug 16 06:18:49 PM PDT 24
Peak memory 224108 kb
Host smart-854f87d6-4b84-4690-ab13-1b5d59eef32c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073001933 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1073001933
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1461994037
Short name T257
Test name
Test status
Simulation time 500895401 ps
CPU time 5.05 seconds
Started Aug 16 06:15:41 PM PDT 24
Finished Aug 16 06:15:46 PM PDT 24
Peak memory 210988 kb
Host smart-f2d32f2a-cebd-4c0f-b982-50473a46fbc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461994037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1461994037
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2927507702
Short name T174
Test name
Test status
Simulation time 6494740308 ps
CPU time 67.39 seconds
Started Aug 16 06:15:42 PM PDT 24
Finished Aug 16 06:16:49 PM PDT 24
Peak memory 232936 kb
Host smart-b51032f7-8df3-4049-ab6a-4e88836cc3b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927507702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2927507702
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3024487049
Short name T260
Test name
Test status
Simulation time 363319311 ps
CPU time 9.02 seconds
Started Aug 16 06:15:43 PM PDT 24
Finished Aug 16 06:15:52 PM PDT 24
Peak memory 211512 kb
Host smart-fd9fb18c-a586-45e1-82c9-16bfddbf308b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024487049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3024487049
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2564120168
Short name T244
Test name
Test status
Simulation time 1494536441 ps
CPU time 5.13 seconds
Started Aug 16 06:15:41 PM PDT 24
Finished Aug 16 06:15:46 PM PDT 24
Peak memory 211136 kb
Host smart-2755d59c-372a-4064-9871-d50029e02759
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2564120168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2564120168
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2799517838
Short name T225
Test name
Test status
Simulation time 810544013 ps
CPU time 14.74 seconds
Started Aug 16 06:15:41 PM PDT 24
Finished Aug 16 06:15:56 PM PDT 24
Peak memory 213784 kb
Host smart-5b15cfc3-42fd-41e0-8053-6b2daa42dcdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799517838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2799517838
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3419112662
Short name T106
Test name
Test status
Simulation time 13076480817 ps
CPU time 63.25 seconds
Started Aug 16 06:15:46 PM PDT 24
Finished Aug 16 06:16:49 PM PDT 24
Peak memory 230292 kb
Host smart-5f37c3b8-e8fd-40bb-b2ee-adfe257e5912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419112662 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3419112662
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.321410404
Short name T206
Test name
Test status
Simulation time 95725285 ps
CPU time 4.25 seconds
Started Aug 16 06:15:43 PM PDT 24
Finished Aug 16 06:15:47 PM PDT 24
Peak memory 211116 kb
Host smart-33d69eea-0f2b-42c5-8aa1-f4816f19bd1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321410404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.321410404
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.13311174
Short name T222
Test name
Test status
Simulation time 3058356206 ps
CPU time 73.77 seconds
Started Aug 16 06:15:43 PM PDT 24
Finished Aug 16 06:16:57 PM PDT 24
Peak memory 235700 kb
Host smart-0d006651-2f46-4dfb-b560-2ff3762efbc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13311174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_co
rrupt_sig_fatal_chk.13311174
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1567720650
Short name T153
Test name
Test status
Simulation time 170144850 ps
CPU time 8.94 seconds
Started Aug 16 06:15:49 PM PDT 24
Finished Aug 16 06:15:58 PM PDT 24
Peak memory 211400 kb
Host smart-77696521-3ed8-4d54-91cd-d857d59cff30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567720650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1567720650
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2273712291
Short name T328
Test name
Test status
Simulation time 139427799 ps
CPU time 6.15 seconds
Started Aug 16 06:15:42 PM PDT 24
Finished Aug 16 06:15:48 PM PDT 24
Peak memory 211120 kb
Host smart-c0365881-c292-4030-92c5-6825e2e6b1ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2273712291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2273712291
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2214542889
Short name T161
Test name
Test status
Simulation time 100962479 ps
CPU time 8.46 seconds
Started Aug 16 06:15:43 PM PDT 24
Finished Aug 16 06:15:51 PM PDT 24
Peak memory 210968 kb
Host smart-4b2454f7-d747-48b7-9512-957d7db9c1ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214542889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2214542889
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.299365647
Short name T152
Test name
Test status
Simulation time 7479247789 ps
CPU time 61.85 seconds
Started Aug 16 06:15:46 PM PDT 24
Finished Aug 16 06:16:48 PM PDT 24
Peak memory 221724 kb
Host smart-85f0b33b-3d04-4b09-813c-fc753a77bb93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299365647 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.299365647
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.767272165
Short name T283
Test name
Test status
Simulation time 89034689 ps
CPU time 4.15 seconds
Started Aug 16 06:15:42 PM PDT 24
Finished Aug 16 06:15:47 PM PDT 24
Peak memory 211092 kb
Host smart-b7db7f91-8161-4d6e-8d39-50627ace406e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767272165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.767272165
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2724328480
Short name T181
Test name
Test status
Simulation time 9692145784 ps
CPU time 128.5 seconds
Started Aug 16 06:15:46 PM PDT 24
Finished Aug 16 06:17:55 PM PDT 24
Peak memory 228320 kb
Host smart-3c76c823-3fcc-421b-b7a0-7a777f45f734
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724328480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2724328480
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1610919686
Short name T51
Test name
Test status
Simulation time 333935910 ps
CPU time 8.97 seconds
Started Aug 16 06:15:46 PM PDT 24
Finished Aug 16 06:15:55 PM PDT 24
Peak memory 211512 kb
Host smart-b3b70e54-ddbe-4f35-bdbf-c3263e7fd74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610919686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1610919686
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.968409631
Short name T212
Test name
Test status
Simulation time 96836596 ps
CPU time 5.44 seconds
Started Aug 16 06:15:44 PM PDT 24
Finished Aug 16 06:15:50 PM PDT 24
Peak memory 211152 kb
Host smart-93c11cde-16b6-4b87-84f0-ab09930102fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968409631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.968409631
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.56751587
Short name T127
Test name
Test status
Simulation time 116037267 ps
CPU time 7.34 seconds
Started Aug 16 06:15:42 PM PDT 24
Finished Aug 16 06:15:50 PM PDT 24
Peak memory 211136 kb
Host smart-76a6ddfe-d40a-4d04-988a-5f453de0b369
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56751587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.rom_ctrl_stress_all.56751587
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.121421885
Short name T11
Test name
Test status
Simulation time 5184802521 ps
CPU time 333.51 seconds
Started Aug 16 06:15:45 PM PDT 24
Finished Aug 16 06:21:19 PM PDT 24
Peak memory 233640 kb
Host smart-2332656d-90fc-471f-a0cb-e3c4feb61285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121421885 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.121421885
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1904733253
Short name T310
Test name
Test status
Simulation time 96758361 ps
CPU time 4.1 seconds
Started Aug 16 06:15:44 PM PDT 24
Finished Aug 16 06:15:48 PM PDT 24
Peak memory 211128 kb
Host smart-f5b20046-80cc-43a1-9001-86ad96977f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904733253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1904733253
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2699431538
Short name T189
Test name
Test status
Simulation time 1246983530 ps
CPU time 68.45 seconds
Started Aug 16 06:15:44 PM PDT 24
Finished Aug 16 06:16:52 PM PDT 24
Peak memory 232444 kb
Host smart-19c49011-41b9-4008-8be1-33449a65e8fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699431538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2699431538
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4154703196
Short name T230
Test name
Test status
Simulation time 692463802 ps
CPU time 8.93 seconds
Started Aug 16 06:15:45 PM PDT 24
Finished Aug 16 06:15:54 PM PDT 24
Peak memory 211524 kb
Host smart-d367db7c-0be1-496c-9e7b-f6b134533948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154703196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4154703196
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3097280540
Short name T196
Test name
Test status
Simulation time 278954057 ps
CPU time 6.16 seconds
Started Aug 16 06:15:41 PM PDT 24
Finished Aug 16 06:15:48 PM PDT 24
Peak memory 211056 kb
Host smart-dd5b88d7-a275-48db-b29a-8e782d575dd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097280540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3097280540
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2447305543
Short name T236
Test name
Test status
Simulation time 293820074 ps
CPU time 15.26 seconds
Started Aug 16 06:15:44 PM PDT 24
Finished Aug 16 06:16:00 PM PDT 24
Peak memory 215552 kb
Host smart-e57cbf64-2639-438b-b45e-c25ac6a9a720
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447305543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2447305543
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3125216942
Short name T211
Test name
Test status
Simulation time 5181547194 ps
CPU time 314.42 seconds
Started Aug 16 06:15:43 PM PDT 24
Finished Aug 16 06:20:58 PM PDT 24
Peak memory 232280 kb
Host smart-2528df80-8ddf-4eba-939b-134bbfbb6ad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125216942 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3125216942
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3767511183
Short name T15
Test name
Test status
Simulation time 430625570 ps
CPU time 4.9 seconds
Started Aug 16 06:15:45 PM PDT 24
Finished Aug 16 06:15:50 PM PDT 24
Peak memory 211140 kb
Host smart-6daf25de-de7c-4bd5-9ced-ad13df5f5d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767511183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3767511183
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.964147026
Short name T19
Test name
Test status
Simulation time 42742457353 ps
CPU time 192.11 seconds
Started Aug 16 06:15:49 PM PDT 24
Finished Aug 16 06:19:01 PM PDT 24
Peak memory 236912 kb
Host smart-85476427-a2d3-412c-93fa-e169c5a763ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964147026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.964147026
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2874550772
Short name T50
Test name
Test status
Simulation time 169294073 ps
CPU time 9.06 seconds
Started Aug 16 06:15:45 PM PDT 24
Finished Aug 16 06:15:55 PM PDT 24
Peak memory 211532 kb
Host smart-9e405f27-11c8-448a-a45f-bf62de284f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874550772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2874550772
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2772701934
Short name T2
Test name
Test status
Simulation time 187711881 ps
CPU time 5.09 seconds
Started Aug 16 06:15:45 PM PDT 24
Finished Aug 16 06:15:51 PM PDT 24
Peak memory 211008 kb
Host smart-8635958c-ede8-408c-8106-54f2894bddcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772701934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2772701934
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3574858837
Short name T266
Test name
Test status
Simulation time 644700395 ps
CPU time 7.84 seconds
Started Aug 16 06:15:47 PM PDT 24
Finished Aug 16 06:15:55 PM PDT 24
Peak memory 211756 kb
Host smart-ab559d1c-16d3-4dbf-ac8b-a2a4647eb072
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574858837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3574858837
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.4052021542
Short name T37
Test name
Test status
Simulation time 8446932195 ps
CPU time 249.54 seconds
Started Aug 16 06:15:45 PM PDT 24
Finished Aug 16 06:19:54 PM PDT 24
Peak memory 224584 kb
Host smart-20d74636-3bbc-4e5f-8081-d3ce52afbb80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052021542 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.4052021542
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.954443846
Short name T199
Test name
Test status
Simulation time 379680849 ps
CPU time 5.05 seconds
Started Aug 16 06:15:50 PM PDT 24
Finished Aug 16 06:15:55 PM PDT 24
Peak memory 211068 kb
Host smart-e50f916e-1a42-4531-870e-e96d67f655cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954443846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.954443846
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2062796832
Short name T280
Test name
Test status
Simulation time 3270974884 ps
CPU time 89.66 seconds
Started Aug 16 06:15:49 PM PDT 24
Finished Aug 16 06:17:18 PM PDT 24
Peak memory 237596 kb
Host smart-4a2c3d0d-d88b-491e-a0ec-6070f83d1a80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062796832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2062796832
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4293453583
Short name T314
Test name
Test status
Simulation time 996999443 ps
CPU time 10.51 seconds
Started Aug 16 06:15:48 PM PDT 24
Finished Aug 16 06:15:59 PM PDT 24
Peak memory 211392 kb
Host smart-e06907be-6746-487f-816d-c75717fb6e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293453583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4293453583
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.591823007
Short name T276
Test name
Test status
Simulation time 294577746 ps
CPU time 15.39 seconds
Started Aug 16 06:15:45 PM PDT 24
Finished Aug 16 06:16:00 PM PDT 24
Peak memory 213792 kb
Host smart-2f3efe49-00b0-495d-bff8-fbedee731c5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591823007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.591823007
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1598134107
Short name T332
Test name
Test status
Simulation time 8333255007 ps
CPU time 159.19 seconds
Started Aug 16 06:15:42 PM PDT 24
Finished Aug 16 06:18:22 PM PDT 24
Peak memory 221576 kb
Host smart-697adb48-b31e-4650-9273-78f31929c627
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598134107 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1598134107
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3278239138
Short name T120
Test name
Test status
Simulation time 334907733 ps
CPU time 4.04 seconds
Started Aug 16 06:14:42 PM PDT 24
Finished Aug 16 06:14:46 PM PDT 24
Peak memory 211132 kb
Host smart-6fbed701-c04d-444f-bc21-969e5e99a959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278239138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3278239138
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1957084128
Short name T104
Test name
Test status
Simulation time 3760216766 ps
CPU time 86.56 seconds
Started Aug 16 06:14:40 PM PDT 24
Finished Aug 16 06:16:07 PM PDT 24
Peak memory 228384 kb
Host smart-56160054-3812-4b8f-b3ee-756025ec1c76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957084128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1957084128
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2931796763
Short name T26
Test name
Test status
Simulation time 830647708 ps
CPU time 8.95 seconds
Started Aug 16 06:14:39 PM PDT 24
Finished Aug 16 06:14:49 PM PDT 24
Peak memory 211444 kb
Host smart-06f5cb04-8e2f-42a3-bcfe-a5893f4bed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931796763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2931796763
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3162536382
Short name T111
Test name
Test status
Simulation time 1850108020 ps
CPU time 5.14 seconds
Started Aug 16 06:14:40 PM PDT 24
Finished Aug 16 06:14:46 PM PDT 24
Peak memory 211092 kb
Host smart-d96a652e-6d21-4d29-8fae-df6d7e17ee90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3162536382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3162536382
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2972560043
Short name T227
Test name
Test status
Simulation time 293719298 ps
CPU time 5.95 seconds
Started Aug 16 06:14:39 PM PDT 24
Finished Aug 16 06:14:46 PM PDT 24
Peak memory 211388 kb
Host smart-6115478f-4b02-4095-93bc-f134c4d7facd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972560043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2972560043
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.775824973
Short name T256
Test name
Test status
Simulation time 397536622 ps
CPU time 11.89 seconds
Started Aug 16 06:14:41 PM PDT 24
Finished Aug 16 06:14:53 PM PDT 24
Peak memory 213824 kb
Host smart-c7150e99-7c11-4ab9-a377-91f136e9ab25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775824973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.775824973
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.4229990299
Short name T252
Test name
Test status
Simulation time 2291598361 ps
CPU time 130.54 seconds
Started Aug 16 06:14:41 PM PDT 24
Finished Aug 16 06:16:52 PM PDT 24
Peak memory 220576 kb
Host smart-720b2910-c07a-42e6-8cf8-b9ec9c97fac8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229990299 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.4229990299
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.4251586408
Short name T164
Test name
Test status
Simulation time 88985642 ps
CPU time 4.07 seconds
Started Aug 16 06:14:41 PM PDT 24
Finished Aug 16 06:14:45 PM PDT 24
Peak memory 211128 kb
Host smart-33aeb229-3198-4a4d-a20e-61decb5b0963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251586408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.4251586408
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2207561107
Short name T42
Test name
Test status
Simulation time 6184241318 ps
CPU time 78.84 seconds
Started Aug 16 06:14:39 PM PDT 24
Finished Aug 16 06:15:58 PM PDT 24
Peak memory 224828 kb
Host smart-cad50ab4-fddb-4000-a71b-7c3587220d99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207561107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2207561107
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2004038924
Short name T339
Test name
Test status
Simulation time 178916807 ps
CPU time 9.18 seconds
Started Aug 16 06:14:40 PM PDT 24
Finished Aug 16 06:14:49 PM PDT 24
Peak memory 211156 kb
Host smart-6598372f-3a1d-420d-9984-8fa002aecd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004038924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2004038924
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1491462255
Short name T190
Test name
Test status
Simulation time 296923438 ps
CPU time 6.23 seconds
Started Aug 16 06:14:40 PM PDT 24
Finished Aug 16 06:14:46 PM PDT 24
Peak memory 211148 kb
Host smart-b1ee329d-1126-4c00-9821-b9ba3736ef2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491462255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1491462255
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2436848435
Short name T143
Test name
Test status
Simulation time 137922931 ps
CPU time 5.85 seconds
Started Aug 16 06:14:39 PM PDT 24
Finished Aug 16 06:14:45 PM PDT 24
Peak memory 211140 kb
Host smart-9755003f-53d1-4ff1-b577-4feb56d3eca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436848435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2436848435
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3143720706
Short name T216
Test name
Test status
Simulation time 229314107 ps
CPU time 14.34 seconds
Started Aug 16 06:14:39 PM PDT 24
Finished Aug 16 06:14:54 PM PDT 24
Peak memory 214076 kb
Host smart-c89a2ce3-fe17-497f-b3de-1d80f9087bf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143720706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3143720706
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1518064151
Short name T204
Test name
Test status
Simulation time 10992043816 ps
CPU time 108.93 seconds
Started Aug 16 06:14:41 PM PDT 24
Finished Aug 16 06:16:30 PM PDT 24
Peak memory 223372 kb
Host smart-a6911508-32c5-40e0-ab5e-b15ddc75fcfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518064151 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1518064151
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2578370466
Short name T264
Test name
Test status
Simulation time 517971798 ps
CPU time 4.76 seconds
Started Aug 16 06:14:42 PM PDT 24
Finished Aug 16 06:14:47 PM PDT 24
Peak memory 211092 kb
Host smart-6b9ec9d2-e298-43ee-affb-5049807f5f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578370466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2578370466
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3344219560
Short name T218
Test name
Test status
Simulation time 7660995202 ps
CPU time 92.1 seconds
Started Aug 16 06:14:41 PM PDT 24
Finished Aug 16 06:16:13 PM PDT 24
Peak memory 236520 kb
Host smart-abb8efa2-bc02-427b-b445-14ad462b26f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344219560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3344219560
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.4075773367
Short name T239
Test name
Test status
Simulation time 2524372332 ps
CPU time 10.44 seconds
Started Aug 16 06:14:40 PM PDT 24
Finished Aug 16 06:14:51 PM PDT 24
Peak memory 211236 kb
Host smart-5b187194-55f6-48fd-abba-e58e32d451ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075773367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.4075773367
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.611482178
Short name T184
Test name
Test status
Simulation time 186537753 ps
CPU time 5.28 seconds
Started Aug 16 06:14:40 PM PDT 24
Finished Aug 16 06:14:46 PM PDT 24
Peak memory 211152 kb
Host smart-d0307dbc-901f-4239-8ef3-ed8d000cd002
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=611482178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.611482178
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.513741912
Short name T245
Test name
Test status
Simulation time 366914045 ps
CPU time 5.38 seconds
Started Aug 16 06:14:42 PM PDT 24
Finished Aug 16 06:14:47 PM PDT 24
Peak memory 211252 kb
Host smart-62a51210-9122-4511-90d8-f3ebd4cdf4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513741912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.513741912
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1506684819
Short name T46
Test name
Test status
Simulation time 14157658307 ps
CPU time 222.71 seconds
Started Aug 16 06:14:43 PM PDT 24
Finished Aug 16 06:18:26 PM PDT 24
Peak memory 235712 kb
Host smart-bf7fc6d6-0997-4f42-b639-50ed5c02d751
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506684819 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1506684819
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4028860354
Short name T128
Test name
Test status
Simulation time 131210678 ps
CPU time 4.9 seconds
Started Aug 16 06:14:45 PM PDT 24
Finished Aug 16 06:14:50 PM PDT 24
Peak memory 211132 kb
Host smart-33395ba9-138c-4331-a051-980c115bc4a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028860354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4028860354
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1985510185
Short name T43
Test name
Test status
Simulation time 20798152572 ps
CPU time 105.82 seconds
Started Aug 16 06:14:47 PM PDT 24
Finished Aug 16 06:16:33 PM PDT 24
Peak memory 228252 kb
Host smart-ba1f9e41-986d-47e9-8148-3dbc84443379
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985510185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1985510185
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3897717188
Short name T324
Test name
Test status
Simulation time 261718640 ps
CPU time 10.5 seconds
Started Aug 16 06:14:48 PM PDT 24
Finished Aug 16 06:14:59 PM PDT 24
Peak memory 211132 kb
Host smart-7c53ee84-dace-4c5b-86ac-337b4636c3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897717188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3897717188
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2126254280
Short name T232
Test name
Test status
Simulation time 283581464 ps
CPU time 6.42 seconds
Started Aug 16 06:14:47 PM PDT 24
Finished Aug 16 06:14:53 PM PDT 24
Peak memory 211112 kb
Host smart-3759307b-bb59-4989-9831-51052e9e33d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126254280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2126254280
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1800702117
Short name T8
Test name
Test status
Simulation time 421232842 ps
CPU time 5.46 seconds
Started Aug 16 06:14:46 PM PDT 24
Finished Aug 16 06:14:51 PM PDT 24
Peak memory 212612 kb
Host smart-d83e6c6b-012e-4eb9-a225-b307c0b72e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800702117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1800702117
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1645673037
Short name T32
Test name
Test status
Simulation time 433509476 ps
CPU time 8.86 seconds
Started Aug 16 06:14:48 PM PDT 24
Finished Aug 16 06:14:57 PM PDT 24
Peak memory 211796 kb
Host smart-8183f4b8-b2f0-4373-b8e7-0776e4b42f6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645673037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1645673037
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1751271979
Short name T173
Test name
Test status
Simulation time 4363169660 ps
CPU time 55.21 seconds
Started Aug 16 06:14:48 PM PDT 24
Finished Aug 16 06:15:43 PM PDT 24
Peak memory 220504 kb
Host smart-f5bfabac-cd46-4d31-aa30-ffaf4babeb07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751271979 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1751271979
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2928732775
Short name T242
Test name
Test status
Simulation time 518593324 ps
CPU time 4.92 seconds
Started Aug 16 06:14:46 PM PDT 24
Finished Aug 16 06:14:51 PM PDT 24
Peak memory 211164 kb
Host smart-38fd10e3-fd6b-4fa0-af5d-f217dff605ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928732775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2928732775
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3386983097
Short name T38
Test name
Test status
Simulation time 2668594799 ps
CPU time 136.87 seconds
Started Aug 16 06:14:49 PM PDT 24
Finished Aug 16 06:17:06 PM PDT 24
Peak memory 233584 kb
Host smart-375f113d-b0c1-409b-8d0f-461f2f77b24e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386983097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3386983097
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3172038988
Short name T109
Test name
Test status
Simulation time 256659089 ps
CPU time 10.38 seconds
Started Aug 16 06:14:48 PM PDT 24
Finished Aug 16 06:14:59 PM PDT 24
Peak memory 211524 kb
Host smart-0a21fb29-a57d-41a6-8f61-9012646e9e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172038988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3172038988
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2673616398
Short name T6
Test name
Test status
Simulation time 101679833 ps
CPU time 5.59 seconds
Started Aug 16 06:14:50 PM PDT 24
Finished Aug 16 06:14:55 PM PDT 24
Peak memory 211108 kb
Host smart-099ddb80-93e2-4662-a872-15696577f3d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2673616398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2673616398
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3884903212
Short name T72
Test name
Test status
Simulation time 202472265 ps
CPU time 5.6 seconds
Started Aug 16 06:14:48 PM PDT 24
Finished Aug 16 06:14:54 PM PDT 24
Peak memory 211220 kb
Host smart-6c84ff55-3f49-490c-beb2-3a762c56576b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884903212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3884903212
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1715993390
Short name T274
Test name
Test status
Simulation time 847923163 ps
CPU time 20.7 seconds
Started Aug 16 06:14:49 PM PDT 24
Finished Aug 16 06:15:10 PM PDT 24
Peak memory 216028 kb
Host smart-ee33ee78-f051-4039-a5c7-2a26ecc9d077
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715993390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1715993390
Directory /workspace/9.rom_ctrl_stress_all/latest
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