Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
507119 |
1 |
|
|
T1 |
108 |
|
T6 |
80 |
|
T9 |
94 |
full_word |
316001 |
1 |
|
|
T1 |
11 |
|
T6 |
8 |
|
T8 |
6 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
822820 |
1 |
|
|
T1 |
119 |
|
T6 |
88 |
|
T8 |
6 |
auto[TlIntgErrCmd] |
94 |
1 |
|
|
T56 |
2 |
|
T57 |
5 |
|
T58 |
4 |
auto[TlIntgErrData] |
95 |
1 |
|
|
T56 |
3 |
|
T57 |
4 |
|
T58 |
7 |
auto[TlIntgErrBoth] |
111 |
1 |
|
|
T56 |
5 |
|
T57 |
1 |
|
T58 |
9 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
149676 |
1 |
|
|
T1 |
119 |
|
T6 |
88 |
|
T8 |
6 |
auto[1] |
673444 |
1 |
|
|
T12 |
11343 |
|
T13 |
24552 |
|
T14 |
8829 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
1 |
15 |
93.75 |
1 |
Automatically Generated Cross Bins for cr_all
Uncovered bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | NUMBER | STATUS |
[auto[TlIntgErrCmd]] |
[full_word] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
73270 |
1 |
|
|
T1 |
108 |
|
T6 |
80 |
|
T9 |
94 |
auto[TlIntgErrNone] |
partial |
auto[1] |
433572 |
1 |
|
|
T12 |
7277 |
|
T13 |
15685 |
|
T14 |
5989 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
76278 |
1 |
|
|
T1 |
11 |
|
T6 |
8 |
|
T8 |
6 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
239700 |
1 |
|
|
T12 |
4066 |
|
T13 |
8867 |
|
T14 |
2840 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
44 |
1 |
|
|
T57 |
1 |
|
T58 |
1 |
|
T121 |
2 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
46 |
1 |
|
|
T56 |
2 |
|
T57 |
3 |
|
T58 |
3 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
4 |
1 |
|
|
T57 |
1 |
|
T122 |
1 |
|
T123 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
36 |
1 |
|
|
T57 |
2 |
|
T58 |
3 |
|
T121 |
2 |
auto[TlIntgErrData] |
partial |
auto[1] |
47 |
1 |
|
|
T56 |
2 |
|
T57 |
2 |
|
T58 |
2 |
auto[TlIntgErrData] |
full_word |
auto[0] |
6 |
1 |
|
|
T56 |
1 |
|
T58 |
1 |
|
T123 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
6 |
1 |
|
|
T58 |
1 |
|
T124 |
2 |
|
T123 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
39 |
1 |
|
|
T56 |
1 |
|
T57 |
1 |
|
T58 |
3 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
65 |
1 |
|
|
T56 |
4 |
|
T58 |
6 |
|
T121 |
8 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
3 |
1 |
|
|
T125 |
1 |
|
T126 |
1 |
|
T127 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
4 |
1 |
|
|
T124 |
1 |
|
T128 |
1 |
|
T129 |
1 |