Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.99	100.00	98.28	97.26		100.00	79.41

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.99	100.00	98.28	97.26		100.00	79.41

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.99	100.00	98.28	97.26		100.00	79.41

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.17	96.89	92.13	97.67	100.00	98.28	98.05

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	97.59	100.00	97.22	90.00	100.00	98.31	100.00
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	93.10	90.70	82.93	97.66		94.20	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	442	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
212	1	1
258	1	1
313	1	1
414	8	8
415	8	8
417	8	8
418	8	8
420	8	8
421	8	8
425	1	1
427	1	1
430	1	1
431	1	1
432	1	1
433	1	1
438	1	1
442	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       212
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T8

 LINE       258
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T8
1	1	Covered	T1,T6,T8

 LINE       418
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
1	0	Not Covered

 LINE       427
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T3,T4

 LINE       438
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T10

 LINE       442
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T8
0	1	0	Covered	T2,T3,T4
1	0	0	Covered	T24,T25,T26

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	62	56	90.32
Total Bits	2884	2805	97.26
Total Bits 0->1	1442	1402	97.23
Total Bits 1->0	1442	1403	97.30

Ports	62	56	90.32
Port Bits	2884	2805	97.26
Port Bits 0->1	1442	1402	97.23
Port Bits 1->0	1442	1403	97.30

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_cfg_i.test	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T6	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T9,T12	Yes	T2,T3,T9	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T6	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T2,T9,T12	Yes	T2,T3,T12	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T6,T8	Yes	T1,T6,T8	INPUT
rom_tl_o.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T6,T8	Yes	T1,T6,T8	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T6,*T8	Yes	T1,T6,T8	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T6,T8	Yes	T1,T6,T8	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T6,T8	Yes	T1,T6,T8	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T6,T9	Yes	T1,T6,T9	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T12,*T13,*T14	Yes	T12,T13,T14	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T6,T8	Yes	T1,T6,T8	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T6,T7	Yes	T1,T6,T7	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T5	Yes	T1,T6,T7	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	OUTPUT
keymgr_data_o.valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
kmac_data_i.error	No	Yes	T3,T27,T28	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T8	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T2,T3,T4	Yes	T2,T4,T6	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	212	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	34	34	100.00	27	79.41
Cover properties	0	0		0
Cover sequences	0	0		0
Total	34	34	100.00	27	79.41

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	27399041	27245018	0	0
BusRomIndicesMatch_A	27384314	27236533	0	0
FpvSecCmRegWeOnehotCheck_A	27399041	60	0	0
FpvSecCmReqFifoRptrCheck_A	27399041	0	0	0
FpvSecCmReqFifoWptrCheck_A	27399041	0	0	0
FpvSecCmRspFifoRptrCheck_A	27399041	0	0	0
FpvSecCmRspFifoWptrCheck_A	27399041	0	0	0
FpvSecCmSramReqFifoRptrCheck_A	27399041	0	0	0
FpvSecCmSramReqFifoWptrCheck_A	27399041	0	0	0
KeymgrDataODataKnown_A	27399041	8084033	0	0
KeymgrDataODataKnown_AKnownEnable	27399041	27245018	0	0
KeymgrDataOValidKnown_A	27399041	27245018	0	0
KeymgrValidChk_A	27399041	8073915	0	0
KmacDataODataKnown_A	27399041	19044740	0	0
KmacDataODataKnown_AKnownEnable	27399041	27245018	0	0
KmacDataOValidKnown_A	27399041	27245018	0	0
PwrmgrDataChk_A	27399041	8073915	0	0
PwrmgrDataOKnown_A	27399041	27245018	0	0
RegsTlOAReadyKnown_A	27399041	27245018	0	0
RegsTlODDataKnown_A	27399041	1039292	0	0
RegsTlODDataKnown_AKnownEnable	27399041	27245018	0	0
RegsTlODValidKnown_A	27399041	27245018	0	0
RomTlOAReadyKnown_A	27399041	27245018	0	0
RomTlODDataKnown_A	27399041	1713682	0	0
RomTlODDataKnown_AKnownEnable	27399041	27245018	0	0
RomTlODValidKnown_A	27399041	27245018	0	0
StabilityChkKmac_A	27399041	19042419	0	0
StabilityChkkeymgr_A	27399041	8082945	0	0
TlAccessChk_A	27399041	19160985	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	27399041	60	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	27399041	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	27399041	408	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	27399041	53193	0	0
gen_fsm_scramble_enabled_asserts.InvalidStateTerminal_A	27399041	52120	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	27245018	0	0
T1	41492	41210	0	0
T2	116202	114284	0	0
T3	16669	16539	0	0
T4	212769	210709	0	0
T5	8563	8502	0	0
T6	18562	18397	0	0
T7	8592	8527	0	0
T8	201362	199927	0	0
T9	13670	13577	0	0
T10	8444	8383	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27384314	27236533	0	0
T1	41492	41210	0	0
T2	116202	114284	0	0
T3	16669	16539	0	0
T4	212769	210709	0	0
T5	8563	8502	0	0
T6	18562	18397	0	0
T7	8592	8527	0	0
T8	201075	199882	0	0
T9	13670	13577	0	0
T10	8444	8383	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	60	0	0
T24	13646	10	0	0
T25	18507	10	0	0
T26	0	10	0	0
T29	0	20	0	0
T30	0	10	0	0
T31	24808	0	0	0
T32	242237	0	0	0
T33	99085	0	0	0
T34	13695	0	0	0
T35	659850	0	0	0
T36	51736	0	0	0
T37	276006	0	0	0
T38	12535	0	0	0

FpvSecCmReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	0	0	0

FpvSecCmReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	0	0	0

FpvSecCmRspFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	0	0	0

FpvSecCmRspFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	0	0	0

FpvSecCmSramReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	0	0	0

FpvSecCmSramReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	8084033	0	0
T1	41492	2808	0	0
T2	116202	712	0	0
T3	16669	23	0	0
T4	212769	13713	0	0
T5	8563	287	0	0
T6	18562	1880	0	0
T7	8592	287	0	0
T8	201362	5575	0	0
T9	13670	1161	0	0
T10	8444	137	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	27245018	0	0
T1	41492	41210	0	0
T2	116202	114284	0	0
T3	16669	16539	0	0
T4	212769	210709	0	0
T5	8563	8502	0	0
T6	18562	18397	0	0
T7	8592	8527	0	0
T8	201362	199927	0	0
T9	13670	13577	0	0
T10	8444	8383	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	27245018	0	0
T1	41492	41210	0	0
T2	116202	114284	0	0
T3	16669	16539	0	0
T4	212769	210709	0	0
T5	8563	8502	0	0
T6	18562	18397	0	0
T7	8592	8527	0	0
T8	201362	199927	0	0
T9	13670	13577	0	0
T10	8444	8383	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	8073915	0	0
T1	41492	2805	0	0
T2	116202	618	0	0
T3	16669	22	0	0
T4	212769	13511	0	0
T5	8563	286	0	0
T6	18562	1878	0	0
T7	8592	286	0	0
T8	201362	5404	0	0
T9	13670	1160	0	0
T10	8444	136	0	0

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	19044740	0	0
T1	41492	38232	0	0
T2	116202	112215	0	0
T3	16669	16368	0	0
T4	212769	195696	0	0
T5	8563	8184	0	0
T6	18562	16368	0	0
T7	8592	8184	0	0
T8	201362	193155	0	0
T9	13670	12373	0	0
T10	8444	8184	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	27245018	0	0
T1	41492	41210	0	0
T2	116202	114284	0	0
T3	16669	16539	0	0
T4	212769	210709	0	0
T5	8563	8502	0	0
T6	18562	18397	0	0
T7	8592	8527	0	0
T8	201362	199927	0	0
T9	13670	13577	0	0
T10	8444	8383	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	27245018	0	0
T1	41492	41210	0	0
T2	116202	114284	0	0
T3	16669	16539	0	0
T4	212769	210709	0	0
T5	8563	8502	0	0
T6	18562	18397	0	0
T7	8592	8527	0	0
T8	201362	199927	0	0
T9	13670	13577	0	0
T10	8444	8383	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	8073915	0	0
T1	41492	2805	0	0
T2	116202	618	0	0
T3	16669	22	0	0
T4	212769	13511	0	0
T5	8563	286	0	0
T6	18562	1878	0	0
T7	8592	286	0	0
T8	201362	5404	0	0
T9	13670	1160	0	0
T10	8444	136	0	0

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	27245018	0	0
T1	41492	41210	0	0
T2	116202	114284	0	0
T3	16669	16539	0	0
T4	212769	210709	0	0
T5	8563	8502	0	0
T6	18562	18397	0	0
T7	8592	8527	0	0
T8	201362	199927	0	0
T9	13670	13577	0	0
T10	8444	8383	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	27245018	0	0
T1	41492	41210	0	0
T2	116202	114284	0	0
T3	16669	16539	0	0
T4	212769	210709	0	0
T5	8563	8502	0	0
T6	18562	18397	0	0
T7	8592	8527	0	0
T8	201362	199927	0	0
T9	13670	13577	0	0
T10	8444	8383	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	1039292	0	0
T1	41492	155	0	0
T2	116202	97	0	0
T3	16669	1	0	0
T4	212769	24	0	0
T5	8563	14	0	0
T6	18562	32	0	0
T7	8592	6	0	0
T8	201362	14	0	0
T9	13670	0	0	0
T10	8444	18	0	0
T27	0	1	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	27245018	0	0
T1	41492	41210	0	0
T2	116202	114284	0	0
T3	16669	16539	0	0
T4	212769	210709	0	0
T5	8563	8502	0	0
T6	18562	18397	0	0
T7	8592	8527	0	0
T8	201362	199927	0	0
T9	13670	13577	0	0
T10	8444	8383	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	27245018	0	0
T1	41492	41210	0	0
T2	116202	114284	0	0
T3	16669	16539	0	0
T4	212769	210709	0	0
T5	8563	8502	0	0
T6	18562	18397	0	0
T7	8592	8527	0	0
T8	201362	199927	0	0
T9	13670	13577	0	0
T10	8444	8383	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	27245018	0	0
T1	41492	41210	0	0
T2	116202	114284	0	0
T3	16669	16539	0	0
T4	212769	210709	0	0
T5	8563	8502	0	0
T6	18562	18397	0	0
T7	8592	8527	0	0
T8	201362	199927	0	0
T9	13670	13577	0	0
T10	8444	8383	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	1713682	0	0
T1	41492	119	0	0
T2	116202	0	0	0
T3	16669	0	0	0
T4	212769	0	0	0
T5	8563	0	0	0
T6	18562	88	0	0
T7	8592	0	0	0
T8	201362	9	0	0
T9	13670	108	0	0
T10	8444	0	0	0
T12	0	13427	0	0
T15	0	227	0	0
T19	0	24	0	0
T20	0	170	0	0
T21	0	100	0	0
T22	0	28	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	27245018	0	0
T1	41492	41210	0	0
T2	116202	114284	0	0
T3	16669	16539	0	0
T4	212769	210709	0	0
T5	8563	8502	0	0
T6	18562	18397	0	0
T7	8592	8527	0	0
T8	201362	199927	0	0
T9	13670	13577	0	0
T10	8444	8383	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	27245018	0	0
T1	41492	41210	0	0
T2	116202	114284	0	0
T3	16669	16539	0	0
T4	212769	210709	0	0
T5	8563	8502	0	0
T6	18562	18397	0	0
T7	8592	8527	0	0
T8	201362	199927	0	0
T9	13670	13577	0	0
T10	8444	8383	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	19042419	0	0
T1	41492	38228	0	0
T2	116202	112190	0	0
T3	16669	16366	0	0
T4	212769	195670	0	0
T5	8563	8183	0	0
T6	18562	16366	0	0
T7	8592	8183	0	0
T8	201362	193136	0	0
T9	13670	12372	0	0
T10	8444	8183	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	8082945	0	0
T1	41492	2805	0	0
T2	116202	703	0	0
T3	16669	22	0	0
T4	212769	13702	0	0
T5	8563	286	0	0
T6	18562	1878	0	0
T7	8592	286	0	0
T8	201362	5563	0	0
T9	13670	1160	0	0
T10	8444	136	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	19160985	0	0
T1	41492	38402	0	0
T2	116202	113572	0	0
T3	16669	16516	0	0
T4	212769	196996	0	0
T5	8563	8215	0	0
T6	18562	16517	0	0
T7	8592	8240	0	0
T8	201362	194352	0	0
T9	13670	12416	0	0
T10	8444	8246	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	60	0	0
T24	13646	10	0	0
T25	18507	10	0	0
T26	0	10	0	0
T29	0	20	0	0
T30	0	10	0	0
T31	24808	0	0	0
T32	242237	0	0	0
T33	99085	0	0	0
T34	13695	0	0	0
T35	659850	0	0	0
T36	51736	0	0	0
T37	276006	0	0	0
T38	12535	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	408	0	0
T2	116202	5	0	0
T3	16669	0	0	0
T4	212769	5	0	0
T5	8563	0	0	0
T6	18562	0	0	0
T7	8592	0	0	0
T8	201362	5	0	0
T9	13670	0	0	0
T10	8444	0	0	0
T19	0	10	0	0
T23	0	10	0	0
T24	0	10	0	0
T25	0	10	0	0
T26	0	10	0	0
T27	16880	0	0	0
T32	0	10	0	0
T37	0	20	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	53193	0	0
T2	116202	767	0	0
T3	16669	34	0	0
T4	212769	602	0	0
T5	8563	0	0	0
T6	18562	0	0	0
T7	8592	0	0	0
T8	201362	301	0	0
T9	13670	0	0	0
T10	8444	0	0	0
T19	0	957	0	0
T23	0	691	0	0
T27	16880	35	0	0
T28	0	35	0	0
T39	0	35	0	0
T40	0	34	0	0

gen_fsm_scramble_enabled_asserts.InvalidStateTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27399041	52120	0	0
T2	116202	748	0	0
T3	16669	33	0	0
T4	212769	586	0	0
T5	8563	0	0	0
T6	18562	0	0	0
T7	8592	0	0	0
T8	201362	292	0	0
T9	13670	0	0	0
T10	8444	0	0	0
T19	0	937	0	0
T23	0	671	0	0
T27	16880	34	0	0
T28	0	34	0	0
T39	0	34	0	0
T40	0	33	0	0