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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.39 96.89 91.99 97.67 100.00 98.28 98.05 98.83


Total test records in report: 454
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T294 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2045197971 Aug 18 05:51:58 PM PDT 24 Aug 18 05:54:21 PM PDT 24 9542401345 ps
T295 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3390105011 Aug 18 05:52:22 PM PDT 24 Aug 18 05:52:28 PM PDT 24 533188092 ps
T296 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2386140962 Aug 18 05:52:07 PM PDT 24 Aug 18 05:52:17 PM PDT 24 251273457 ps
T297 /workspace/coverage/default/5.rom_ctrl_stress_all.1102847020 Aug 18 05:51:35 PM PDT 24 Aug 18 05:51:50 PM PDT 24 1073613708 ps
T298 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2855578832 Aug 18 05:52:01 PM PDT 24 Aug 18 05:52:12 PM PDT 24 3110448860 ps
T299 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3443514408 Aug 18 05:52:14 PM PDT 24 Aug 18 05:52:23 PM PDT 24 168654071 ps
T300 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2266789749 Aug 18 05:52:27 PM PDT 24 Aug 18 05:52:37 PM PDT 24 660757482 ps
T301 /workspace/coverage/default/4.rom_ctrl_stress_all.621303422 Aug 18 05:51:37 PM PDT 24 Aug 18 05:51:49 PM PDT 24 404024052 ps
T302 /workspace/coverage/default/29.rom_ctrl_stress_all.1231387705 Aug 18 05:52:10 PM PDT 24 Aug 18 05:52:30 PM PDT 24 550704861 ps
T303 /workspace/coverage/default/0.rom_ctrl_alert_test.1234780554 Aug 18 05:51:38 PM PDT 24 Aug 18 05:51:43 PM PDT 24 260976919 ps
T304 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2326334123 Aug 18 05:51:52 PM PDT 24 Aug 18 05:52:02 PM PDT 24 510814076 ps
T305 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2343576308 Aug 18 05:51:57 PM PDT 24 Aug 18 05:54:09 PM PDT 24 10621940543 ps
T306 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4148101290 Aug 18 05:52:27 PM PDT 24 Aug 18 05:52:38 PM PDT 24 262491253 ps
T307 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1771281769 Aug 18 05:52:26 PM PDT 24 Aug 18 05:56:08 PM PDT 24 14548872421 ps
T308 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2113277591 Aug 18 05:51:34 PM PDT 24 Aug 18 05:51:41 PM PDT 24 138194610 ps
T309 /workspace/coverage/default/12.rom_ctrl_alert_test.3617714980 Aug 18 05:51:58 PM PDT 24 Aug 18 05:52:02 PM PDT 24 87191895 ps
T310 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3922293877 Aug 18 05:51:58 PM PDT 24 Aug 18 05:52:03 PM PDT 24 383458947 ps
T311 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3424856912 Aug 18 05:52:09 PM PDT 24 Aug 18 05:52:15 PM PDT 24 145535904 ps
T312 /workspace/coverage/default/37.rom_ctrl_alert_test.3747628900 Aug 18 05:52:21 PM PDT 24 Aug 18 05:52:26 PM PDT 24 131315993 ps
T99 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1780536439 Aug 18 05:52:24 PM PDT 24 Aug 18 05:52:30 PM PDT 24 548461734 ps
T313 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3784450677 Aug 18 05:52:02 PM PDT 24 Aug 18 05:55:35 PM PDT 24 12825969576 ps
T314 /workspace/coverage/default/17.rom_ctrl_alert_test.3231094956 Aug 18 05:51:55 PM PDT 24 Aug 18 05:51:59 PM PDT 24 86412138 ps
T315 /workspace/coverage/default/41.rom_ctrl_stress_all.776954495 Aug 18 05:52:15 PM PDT 24 Aug 18 05:52:25 PM PDT 24 388066056 ps
T316 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3772154840 Aug 18 05:52:21 PM PDT 24 Aug 18 05:53:19 PM PDT 24 16462512990 ps
T317 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1120492740 Aug 18 05:51:50 PM PDT 24 Aug 18 05:51:59 PM PDT 24 355310752 ps
T318 /workspace/coverage/default/20.rom_ctrl_alert_test.2160298386 Aug 18 05:51:56 PM PDT 24 Aug 18 05:52:00 PM PDT 24 85776804 ps
T319 /workspace/coverage/default/14.rom_ctrl_alert_test.2051274508 Aug 18 05:51:50 PM PDT 24 Aug 18 05:51:56 PM PDT 24 271958019 ps
T320 /workspace/coverage/default/39.rom_ctrl_stress_all.3597304471 Aug 18 05:52:15 PM PDT 24 Aug 18 05:52:28 PM PDT 24 268756235 ps
T321 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3012536553 Aug 18 05:52:04 PM PDT 24 Aug 18 05:52:14 PM PDT 24 252685381 ps
T322 /workspace/coverage/default/23.rom_ctrl_alert_test.652877470 Aug 18 05:52:02 PM PDT 24 Aug 18 05:52:07 PM PDT 24 261822116 ps
T323 /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3926046384 Aug 18 05:51:38 PM PDT 24 Aug 18 05:53:43 PM PDT 24 11021568766 ps
T324 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1050053516 Aug 18 05:52:00 PM PDT 24 Aug 18 05:54:38 PM PDT 24 3157823249 ps
T325 /workspace/coverage/default/46.rom_ctrl_stress_all.2390917791 Aug 18 05:52:26 PM PDT 24 Aug 18 05:52:38 PM PDT 24 496379143 ps
T326 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1702368223 Aug 18 05:52:00 PM PDT 24 Aug 18 05:52:06 PM PDT 24 393318680 ps
T327 /workspace/coverage/default/30.rom_ctrl_stress_all.2075118923 Aug 18 05:52:12 PM PDT 24 Aug 18 05:52:27 PM PDT 24 1132029568 ps
T328 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2469338538 Aug 18 05:52:13 PM PDT 24 Aug 18 05:52:19 PM PDT 24 605338484 ps
T329 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.363403551 Aug 18 05:51:38 PM PDT 24 Aug 18 05:54:00 PM PDT 24 58195074173 ps
T330 /workspace/coverage/default/5.rom_ctrl_alert_test.1114124322 Aug 18 05:51:44 PM PDT 24 Aug 18 05:51:49 PM PDT 24 261454125 ps
T331 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1778921446 Aug 18 05:51:57 PM PDT 24 Aug 18 05:52:55 PM PDT 24 6301237240 ps
T332 /workspace/coverage/default/0.rom_ctrl_smoke.2762458280 Aug 18 05:51:34 PM PDT 24 Aug 18 05:51:40 PM PDT 24 98967653 ps
T333 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3502356796 Aug 18 05:52:14 PM PDT 24 Aug 18 05:53:56 PM PDT 24 4140589858 ps
T24 /workspace/coverage/default/4.rom_ctrl_sec_cm.2346083899 Aug 18 05:51:36 PM PDT 24 Aug 18 05:52:27 PM PDT 24 759350331 ps
T334 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2711155568 Aug 18 05:52:03 PM PDT 24 Aug 18 05:53:43 PM PDT 24 10753484124 ps
T335 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4073939660 Aug 18 05:52:00 PM PDT 24 Aug 18 05:52:05 PM PDT 24 348715180 ps
T336 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.272696178 Aug 18 05:52:18 PM PDT 24 Aug 18 05:52:24 PM PDT 24 402390570 ps
T337 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.198273621 Aug 18 05:51:38 PM PDT 24 Aug 18 05:54:15 PM PDT 24 40921593711 ps
T338 /workspace/coverage/default/44.rom_ctrl_alert_test.2216737356 Aug 18 05:52:28 PM PDT 24 Aug 18 05:52:32 PM PDT 24 175605209 ps
T339 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2274791315 Aug 18 05:52:10 PM PDT 24 Aug 18 05:54:19 PM PDT 24 10083191155 ps
T340 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3387270554 Aug 18 05:51:58 PM PDT 24 Aug 18 05:52:03 PM PDT 24 362065506 ps
T25 /workspace/coverage/default/3.rom_ctrl_sec_cm.3424693552 Aug 18 05:51:37 PM PDT 24 Aug 18 05:53:17 PM PDT 24 1009897337 ps
T341 /workspace/coverage/default/32.rom_ctrl_stress_all.3141811653 Aug 18 05:52:10 PM PDT 24 Aug 18 05:52:15 PM PDT 24 221445285 ps
T342 /workspace/coverage/default/28.rom_ctrl_alert_test.2620660086 Aug 18 05:52:14 PM PDT 24 Aug 18 05:52:19 PM PDT 24 519835485 ps
T343 /workspace/coverage/default/2.rom_ctrl_alert_test.72911907 Aug 18 05:51:43 PM PDT 24 Aug 18 05:51:48 PM PDT 24 2486369992 ps
T344 /workspace/coverage/default/36.rom_ctrl_stress_all.769390811 Aug 18 05:52:10 PM PDT 24 Aug 18 05:52:21 PM PDT 24 333930361 ps
T345 /workspace/coverage/default/28.rom_ctrl_stress_all.2614999452 Aug 18 05:52:06 PM PDT 24 Aug 18 05:52:21 PM PDT 24 809490507 ps
T346 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2245081427 Aug 18 05:51:45 PM PDT 24 Aug 18 05:51:51 PM PDT 24 97286238 ps
T347 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3960776685 Aug 18 05:52:11 PM PDT 24 Aug 18 05:54:13 PM PDT 24 23980693428 ps
T348 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2791355804 Aug 18 05:52:09 PM PDT 24 Aug 18 05:54:31 PM PDT 24 7594415679 ps
T349 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3106168801 Aug 18 05:52:03 PM PDT 24 Aug 18 05:52:09 PM PDT 24 193998383 ps
T55 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3494313725 Aug 18 05:52:44 PM PDT 24 Aug 18 05:53:14 PM PDT 24 1953328484 ps
T56 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2121948944 Aug 18 05:52:40 PM PDT 24 Aug 18 05:52:45 PM PDT 24 126487646 ps
T57 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1194019893 Aug 18 05:52:41 PM PDT 24 Aug 18 05:52:45 PM PDT 24 351477407 ps
T350 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2820219340 Aug 18 05:52:50 PM PDT 24 Aug 18 05:52:59 PM PDT 24 526361903 ps
T96 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4260228426 Aug 18 05:52:50 PM PDT 24 Aug 18 05:52:57 PM PDT 24 181508493 ps
T351 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3016730286 Aug 18 05:52:42 PM PDT 24 Aug 18 05:52:47 PM PDT 24 252073882 ps
T352 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.99876076 Aug 18 05:52:57 PM PDT 24 Aug 18 05:53:02 PM PDT 24 522617496 ps
T100 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2263036998 Aug 18 05:52:35 PM PDT 24 Aug 18 05:52:42 PM PDT 24 514161441 ps
T353 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.475287742 Aug 18 05:52:51 PM PDT 24 Aug 18 05:52:55 PM PDT 24 362837987 ps
T354 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4253345615 Aug 18 05:52:38 PM PDT 24 Aug 18 05:52:42 PM PDT 24 175687199 ps
T52 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3938074298 Aug 18 05:52:47 PM PDT 24 Aug 18 05:53:56 PM PDT 24 1023798427 ps
T61 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1725125142 Aug 18 05:52:47 PM PDT 24 Aug 18 05:52:52 PM PDT 24 127067401 ps
T355 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1584342738 Aug 18 05:52:52 PM PDT 24 Aug 18 05:53:01 PM PDT 24 502166600 ps
T356 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.212668272 Aug 18 05:52:43 PM PDT 24 Aug 18 05:52:47 PM PDT 24 376353891 ps
T62 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.363906743 Aug 18 05:53:00 PM PDT 24 Aug 18 05:53:21 PM PDT 24 10408334487 ps
T63 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4142254809 Aug 18 05:52:38 PM PDT 24 Aug 18 05:52:45 PM PDT 24 311078442 ps
T64 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.105841029 Aug 18 05:52:42 PM PDT 24 Aug 18 05:53:03 PM PDT 24 532890596 ps
T97 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2550304173 Aug 18 05:52:51 PM PDT 24 Aug 18 05:52:55 PM PDT 24 382608488 ps
T357 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1730277061 Aug 18 05:52:32 PM PDT 24 Aug 18 05:52:37 PM PDT 24 959801888 ps
T65 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2218734623 Aug 18 05:52:44 PM PDT 24 Aug 18 05:52:49 PM PDT 24 499479350 ps
T358 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1985675952 Aug 18 05:52:41 PM PDT 24 Aug 18 05:52:46 PM PDT 24 92065874 ps
T66 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.328270849 Aug 18 05:52:57 PM PDT 24 Aug 18 05:53:39 PM PDT 24 11978779203 ps
T53 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.688031279 Aug 18 05:52:34 PM PDT 24 Aug 18 05:53:42 PM PDT 24 510112131 ps
T359 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3389692353 Aug 18 05:52:42 PM PDT 24 Aug 18 05:52:51 PM PDT 24 148320620 ps
T360 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2883659781 Aug 18 05:52:41 PM PDT 24 Aug 18 05:52:51 PM PDT 24 1977259837 ps
T98 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1054622650 Aug 18 05:52:49 PM PDT 24 Aug 18 05:52:55 PM PDT 24 349527085 ps
T361 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.125294012 Aug 18 05:52:49 PM PDT 24 Aug 18 05:52:54 PM PDT 24 599144326 ps
T67 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3068179802 Aug 18 05:52:44 PM PDT 24 Aug 18 05:52:48 PM PDT 24 126571656 ps
T54 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.550845264 Aug 18 05:52:40 PM PDT 24 Aug 18 05:53:17 PM PDT 24 708946888 ps
T68 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2371490843 Aug 18 05:52:42 PM PDT 24 Aug 18 05:52:59 PM PDT 24 1249581212 ps
T74 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3204600159 Aug 18 05:52:51 PM PDT 24 Aug 18 05:52:56 PM PDT 24 127607075 ps
T362 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1863137836 Aug 18 05:52:35 PM PDT 24 Aug 18 05:52:43 PM PDT 24 405574950 ps
T109 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.12185054 Aug 18 05:52:49 PM PDT 24 Aug 18 05:53:27 PM PDT 24 4581689553 ps
T363 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.137460210 Aug 18 05:52:41 PM PDT 24 Aug 18 05:52:46 PM PDT 24 126827466 ps
T364 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.676413702 Aug 18 05:52:46 PM PDT 24 Aug 18 05:52:50 PM PDT 24 88093116 ps
T365 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.908355883 Aug 18 05:52:47 PM PDT 24 Aug 18 05:52:53 PM PDT 24 135446694 ps
T366 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2852075074 Aug 18 05:52:51 PM PDT 24 Aug 18 05:52:55 PM PDT 24 396084175 ps
T112 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.32531595 Aug 18 05:52:32 PM PDT 24 Aug 18 05:53:41 PM PDT 24 230488168 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3117161674 Aug 18 05:52:43 PM PDT 24 Aug 18 05:52:47 PM PDT 24 334002893 ps
T368 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3087586312 Aug 18 05:52:34 PM PDT 24 Aug 18 05:52:38 PM PDT 24 86408382 ps
T369 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.185555183 Aug 18 05:52:44 PM PDT 24 Aug 18 05:52:48 PM PDT 24 127278654 ps
T370 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4273377308 Aug 18 05:52:50 PM PDT 24 Aug 18 05:53:11 PM PDT 24 1029248400 ps
T371 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1864243250 Aug 18 05:52:48 PM PDT 24 Aug 18 05:52:52 PM PDT 24 175162342 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.831747065 Aug 18 05:52:33 PM PDT 24 Aug 18 05:52:37 PM PDT 24 155561123 ps
T110 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1397265792 Aug 18 05:52:52 PM PDT 24 Aug 18 05:54:00 PM PDT 24 925978416 ps
T75 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2965810662 Aug 18 05:52:52 PM PDT 24 Aug 18 05:53:24 PM PDT 24 3028917123 ps
T373 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1311325601 Aug 18 05:52:47 PM PDT 24 Aug 18 05:52:53 PM PDT 24 346272337 ps
T115 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2434066821 Aug 18 05:52:42 PM PDT 24 Aug 18 05:53:17 PM PDT 24 883719992 ps
T374 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1960763266 Aug 18 05:52:32 PM PDT 24 Aug 18 05:52:39 PM PDT 24 800393277 ps
T76 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2575890513 Aug 18 05:52:50 PM PDT 24 Aug 18 05:53:16 PM PDT 24 586241825 ps
T375 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.793083882 Aug 18 05:52:58 PM PDT 24 Aug 18 05:53:03 PM PDT 24 301507194 ps
T376 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3471754947 Aug 18 05:52:58 PM PDT 24 Aug 18 05:53:03 PM PDT 24 132221830 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1123863959 Aug 18 05:52:41 PM PDT 24 Aug 18 05:52:48 PM PDT 24 418173780 ps
T378 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.476197374 Aug 18 05:52:32 PM PDT 24 Aug 18 05:53:04 PM PDT 24 7818859344 ps
T379 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2985242516 Aug 18 05:52:43 PM PDT 24 Aug 18 05:52:51 PM PDT 24 259852904 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3631659063 Aug 18 05:52:31 PM PDT 24 Aug 18 05:53:02 PM PDT 24 805110253 ps
T77 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.188526631 Aug 18 05:52:43 PM PDT 24 Aug 18 05:53:14 PM PDT 24 3268199044 ps
T381 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1259152977 Aug 18 05:52:42 PM PDT 24 Aug 18 05:53:14 PM PDT 24 3122940967 ps
T78 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2313776285 Aug 18 05:52:59 PM PDT 24 Aug 18 05:53:03 PM PDT 24 524205842 ps
T382 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1201983731 Aug 18 05:52:55 PM PDT 24 Aug 18 05:53:00 PM PDT 24 1245262000 ps
T383 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.656957517 Aug 18 05:52:55 PM PDT 24 Aug 18 05:52:59 PM PDT 24 1249945372 ps
T384 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1110424614 Aug 18 05:52:38 PM PDT 24 Aug 18 05:52:43 PM PDT 24 504763937 ps
T385 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1619224224 Aug 18 05:52:45 PM PDT 24 Aug 18 05:53:22 PM PDT 24 219169554 ps
T386 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3968937766 Aug 18 05:52:35 PM PDT 24 Aug 18 05:52:39 PM PDT 24 336009526 ps
T114 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1700396822 Aug 18 05:52:45 PM PDT 24 Aug 18 05:53:21 PM PDT 24 664008931 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.201211202 Aug 18 05:52:42 PM PDT 24 Aug 18 05:52:47 PM PDT 24 642007735 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1419494440 Aug 18 05:52:45 PM PDT 24 Aug 18 05:52:54 PM PDT 24 345484633 ps
T107 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.246211596 Aug 18 05:52:51 PM PDT 24 Aug 18 05:53:28 PM PDT 24 796646871 ps
T79 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4261570958 Aug 18 05:52:55 PM PDT 24 Aug 18 05:53:15 PM PDT 24 2171958540 ps
T389 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3257846852 Aug 18 05:52:49 PM PDT 24 Aug 18 05:52:54 PM PDT 24 382116156 ps
T390 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.988723442 Aug 18 05:52:43 PM PDT 24 Aug 18 05:52:50 PM PDT 24 255168066 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4211933572 Aug 18 05:52:46 PM PDT 24 Aug 18 05:52:51 PM PDT 24 500455185 ps
T85 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2331431086 Aug 18 05:52:33 PM PDT 24 Aug 18 05:52:39 PM PDT 24 524421443 ps
T392 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1471617132 Aug 18 05:52:49 PM PDT 24 Aug 18 05:52:56 PM PDT 24 266341292 ps
T393 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2976827777 Aug 18 05:52:42 PM PDT 24 Aug 18 05:53:04 PM PDT 24 542802770 ps
T108 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1365817073 Aug 18 05:52:41 PM PDT 24 Aug 18 05:53:50 PM PDT 24 731888931 ps
T394 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.795074577 Aug 18 05:52:44 PM PDT 24 Aug 18 05:52:49 PM PDT 24 196239295 ps
T395 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1272253352 Aug 18 05:52:43 PM PDT 24 Aug 18 05:52:48 PM PDT 24 130558769 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4112993547 Aug 18 05:52:33 PM PDT 24 Aug 18 05:52:39 PM PDT 24 178199227 ps
T397 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1553107088 Aug 18 05:52:48 PM PDT 24 Aug 18 05:53:09 PM PDT 24 533942532 ps
T84 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1418603414 Aug 18 05:52:49 PM PDT 24 Aug 18 05:52:54 PM PDT 24 252308821 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1265483926 Aug 18 05:52:39 PM PDT 24 Aug 18 05:52:43 PM PDT 24 87480548 ps
T399 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.535350452 Aug 18 05:52:42 PM PDT 24 Aug 18 05:53:03 PM PDT 24 2192912908 ps
T400 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3456281763 Aug 18 05:52:32 PM PDT 24 Aug 18 05:52:37 PM PDT 24 363765702 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1674499747 Aug 18 05:52:35 PM PDT 24 Aug 18 05:52:39 PM PDT 24 396297435 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.739466451 Aug 18 05:52:35 PM PDT 24 Aug 18 05:52:40 PM PDT 24 334973486 ps
T80 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.818534687 Aug 18 05:52:49 PM PDT 24 Aug 18 05:52:54 PM PDT 24 171791168 ps
T403 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.5408075 Aug 18 05:52:58 PM PDT 24 Aug 18 05:53:16 PM PDT 24 5125369019 ps
T404 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.647035521 Aug 18 05:52:57 PM PDT 24 Aug 18 05:53:04 PM PDT 24 892126742 ps
T405 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3920138140 Aug 18 05:52:50 PM PDT 24 Aug 18 05:52:57 PM PDT 24 519402102 ps
T406 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3908583137 Aug 18 05:52:51 PM PDT 24 Aug 18 05:52:56 PM PDT 24 85438222 ps
T407 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2366474494 Aug 18 05:52:40 PM PDT 24 Aug 18 05:52:44 PM PDT 24 85891467 ps
T113 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1820481137 Aug 18 05:52:51 PM PDT 24 Aug 18 05:54:01 PM PDT 24 621792041 ps
T408 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3799012989 Aug 18 05:53:00 PM PDT 24 Aug 18 05:53:04 PM PDT 24 337115847 ps
T409 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2364000973 Aug 18 05:52:44 PM PDT 24 Aug 18 05:52:48 PM PDT 24 88106154 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2424997075 Aug 18 05:52:32 PM PDT 24 Aug 18 05:52:36 PM PDT 24 88885987 ps
T411 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.365337134 Aug 18 05:52:53 PM PDT 24 Aug 18 05:53:01 PM PDT 24 373934224 ps
T412 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.750803028 Aug 18 05:52:44 PM PDT 24 Aug 18 05:52:51 PM PDT 24 135270067 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2306214263 Aug 18 05:52:47 PM PDT 24 Aug 18 05:52:51 PM PDT 24 88946971 ps
T414 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1672563168 Aug 18 05:52:34 PM PDT 24 Aug 18 05:52:40 PM PDT 24 98279520 ps
T106 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.326218364 Aug 18 05:52:45 PM PDT 24 Aug 18 05:53:53 PM PDT 24 1473124239 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4270572112 Aug 18 05:52:33 PM PDT 24 Aug 18 05:52:37 PM PDT 24 88202162 ps
T416 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2154833228 Aug 18 05:52:51 PM PDT 24 Aug 18 05:52:58 PM PDT 24 182475762 ps
T417 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4260394224 Aug 18 05:52:51 PM PDT 24 Aug 18 05:52:56 PM PDT 24 527510688 ps
T81 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3342405301 Aug 18 05:52:33 PM PDT 24 Aug 18 05:52:52 PM PDT 24 1325799882 ps
T111 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2341868205 Aug 18 05:53:00 PM PDT 24 Aug 18 05:54:09 PM PDT 24 1095424810 ps
T418 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3850211385 Aug 18 05:52:51 PM PDT 24 Aug 18 05:53:27 PM PDT 24 689897344 ps
T419 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.651377696 Aug 18 05:52:50 PM PDT 24 Aug 18 05:52:57 PM PDT 24 511516765 ps
T420 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.580701289 Aug 18 05:52:59 PM PDT 24 Aug 18 05:53:06 PM PDT 24 363016753 ps
T421 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.577036092 Aug 18 05:52:41 PM PDT 24 Aug 18 05:52:48 PM PDT 24 98596975 ps
T422 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.386018825 Aug 18 05:52:40 PM PDT 24 Aug 18 05:52:45 PM PDT 24 591630014 ps
T423 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1854507387 Aug 18 05:52:41 PM PDT 24 Aug 18 05:52:46 PM PDT 24 349479433 ps
T424 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2254743271 Aug 18 05:52:39 PM PDT 24 Aug 18 05:52:46 PM PDT 24 127374861 ps
T425 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1338681881 Aug 18 05:52:50 PM PDT 24 Aug 18 05:53:00 PM PDT 24 326577227 ps
T426 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1856850393 Aug 18 05:52:44 PM PDT 24 Aug 18 05:52:49 PM PDT 24 128010349 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1569206357 Aug 18 05:52:38 PM PDT 24 Aug 18 05:52:46 PM PDT 24 130952285 ps
T428 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1829497934 Aug 18 05:52:51 PM PDT 24 Aug 18 05:53:00 PM PDT 24 691526865 ps
T429 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1925643347 Aug 18 05:52:49 PM PDT 24 Aug 18 05:52:57 PM PDT 24 257152857 ps
T430 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2016439999 Aug 18 05:52:44 PM PDT 24 Aug 18 05:52:51 PM PDT 24 9870393633 ps
T431 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.538131205 Aug 18 05:52:41 PM PDT 24 Aug 18 05:52:52 PM PDT 24 524878249 ps
T432 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1718467349 Aug 18 05:52:44 PM PDT 24 Aug 18 05:53:16 PM PDT 24 822874659 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.781718228 Aug 18 05:52:40 PM PDT 24 Aug 18 05:52:46 PM PDT 24 522516456 ps
T434 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2194472765 Aug 18 05:52:41 PM PDT 24 Aug 18 05:52:46 PM PDT 24 309634342 ps
T435 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2270715101 Aug 18 05:52:49 PM PDT 24 Aug 18 05:52:53 PM PDT 24 199938751 ps
T436 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.763733534 Aug 18 05:52:32 PM PDT 24 Aug 18 05:53:09 PM PDT 24 221132845 ps
T82 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4217551202 Aug 18 05:52:44 PM PDT 24 Aug 18 05:52:48 PM PDT 24 334491590 ps
T437 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3527820759 Aug 18 05:52:50 PM PDT 24 Aug 18 05:53:28 PM PDT 24 364554775 ps
T438 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1917408650 Aug 18 05:52:42 PM PDT 24 Aug 18 05:53:19 PM PDT 24 694600259 ps
T83 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.864564411 Aug 18 05:52:32 PM PDT 24 Aug 18 05:52:36 PM PDT 24 837653418 ps
T439 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2728520257 Aug 18 05:52:43 PM PDT 24 Aug 18 05:52:48 PM PDT 24 134009237 ps
T440 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2239166511 Aug 18 05:52:45 PM PDT 24 Aug 18 05:52:49 PM PDT 24 174635337 ps
T441 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3482396901 Aug 18 05:52:46 PM PDT 24 Aug 18 05:53:22 PM PDT 24 2497127200 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1899618882 Aug 18 05:52:34 PM PDT 24 Aug 18 05:52:39 PM PDT 24 132162087 ps
T443 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.646599044 Aug 18 05:52:44 PM PDT 24 Aug 18 05:52:48 PM PDT 24 141322805 ps
T444 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3641385064 Aug 18 05:52:49 PM PDT 24 Aug 18 05:52:54 PM PDT 24 261486858 ps
T445 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2754776338 Aug 18 05:52:42 PM PDT 24 Aug 18 05:52:49 PM PDT 24 150763497 ps
T446 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3197717606 Aug 18 05:52:52 PM PDT 24 Aug 18 05:52:58 PM PDT 24 239201157 ps
T447 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3406788110 Aug 18 05:53:00 PM PDT 24 Aug 18 05:53:05 PM PDT 24 260097650 ps
T448 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.928961337 Aug 18 05:53:00 PM PDT 24 Aug 18 05:53:36 PM PDT 24 281845238 ps
T449 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.620262043 Aug 18 05:52:52 PM PDT 24 Aug 18 05:53:09 PM PDT 24 1488142169 ps
T450 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2109690528 Aug 18 05:52:44 PM PDT 24 Aug 18 05:52:50 PM PDT 24 155172254 ps
T451 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2644786029 Aug 18 05:52:44 PM PDT 24 Aug 18 05:52:51 PM PDT 24 2900924730 ps
T452 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2532691149 Aug 18 05:52:55 PM PDT 24 Aug 18 05:52:59 PM PDT 24 355268735 ps
T453 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2694589918 Aug 18 05:52:46 PM PDT 24 Aug 18 05:52:51 PM PDT 24 132046191 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.715741140 Aug 18 05:52:32 PM PDT 24 Aug 18 05:52:40 PM PDT 24 179296512 ps

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3619304143
Short name T4
Test name
Test status
Simulation time 14532015990 ps
CPU time 230.04 seconds
Started Aug 18 05:51:58 PM PDT 24
Finished Aug 18 05:55:48 PM PDT 24
Peak memory 223756 kb
Host smart-5cbdad6a-1ca7-4370-a742-13e7d8b4495b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619304143 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3619304143
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.751607527
Short name T9
Test name
Test status
Simulation time 1564625018 ps
CPU time 75.68 seconds
Started Aug 18 05:51:58 PM PDT 24
Finished Aug 18 05:53:14 PM PDT 24
Peak memory 237220 kb
Host smart-08bab8ca-8fca-4811-992d-cfecd78f3874
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751607527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.751607527
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4071336521
Short name T170
Test name
Test status
Simulation time 12191294856 ps
CPU time 147.42 seconds
Started Aug 18 05:51:48 PM PDT 24
Finished Aug 18 05:54:15 PM PDT 24
Peak memory 237616 kb
Host smart-19e95002-5650-46ff-826c-f97d4c54ec94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071336521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.4071336521
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.32531595
Short name T112
Test name
Test status
Simulation time 230488168 ps
CPU time 69.34 seconds
Started Aug 18 05:52:32 PM PDT 24
Finished Aug 18 05:53:41 PM PDT 24
Peak memory 219524 kb
Host smart-cda065ce-b8ec-4116-b2cd-efafb7382e7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32531595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg
_err.32531595
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.550584017
Short name T12
Test name
Test status
Simulation time 1901733407 ps
CPU time 80.72 seconds
Started Aug 18 05:52:21 PM PDT 24
Finished Aug 18 05:53:42 PM PDT 24
Peak memory 219536 kb
Host smart-955ae1e0-ba48-48c8-a773-a1907ac1499b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550584017 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.550584017
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3424612808
Short name T17
Test name
Test status
Simulation time 1082713251 ps
CPU time 99.29 seconds
Started Aug 18 05:51:37 PM PDT 24
Finished Aug 18 05:53:16 PM PDT 24
Peak memory 235292 kb
Host smart-9d6e8564-6d7b-4061-b04a-d4861113e8ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424612808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3424612808
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.487110737
Short name T103
Test name
Test status
Simulation time 522975852 ps
CPU time 4.93 seconds
Started Aug 18 05:51:56 PM PDT 24
Finished Aug 18 05:52:01 PM PDT 24
Peak memory 211068 kb
Host smart-306a6982-70ee-419a-9e2f-4bbcbee94d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487110737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.487110737
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.363906743
Short name T62
Test name
Test status
Simulation time 10408334487 ps
CPU time 20.58 seconds
Started Aug 18 05:53:00 PM PDT 24
Finished Aug 18 05:53:21 PM PDT 24
Peak memory 219712 kb
Host smart-b89b7e47-8b18-4ee2-ba4b-bb28840d1e4d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363906743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.363906743
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.12185054
Short name T109
Test name
Test status
Simulation time 4581689553 ps
CPU time 38.34 seconds
Started Aug 18 05:52:49 PM PDT 24
Finished Aug 18 05:53:27 PM PDT 24
Peak memory 214448 kb
Host smart-f86bf18b-d300-4663-ba36-45933415c7b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12185054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_int
g_err.12185054
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1761591994
Short name T35
Test name
Test status
Simulation time 51773715279 ps
CPU time 151.01 seconds
Started Aug 18 05:52:19 PM PDT 24
Finished Aug 18 05:54:50 PM PDT 24
Peak memory 237656 kb
Host smart-70f12fea-61b9-4fb7-81fe-7b05b3c3ad05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761591994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1761591994
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1419256635
Short name T21
Test name
Test status
Simulation time 174328233 ps
CPU time 8.9 seconds
Started Aug 18 05:51:56 PM PDT 24
Finished Aug 18 05:52:05 PM PDT 24
Peak memory 211488 kb
Host smart-6c605b77-f3ea-4ab1-9636-1499a36372d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419256635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1419256635
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2371490843
Short name T68
Test name
Test status
Simulation time 1249581212 ps
CPU time 17.77 seconds
Started Aug 18 05:52:42 PM PDT 24
Finished Aug 18 05:52:59 PM PDT 24
Peak memory 211400 kb
Host smart-d4407dd2-d079-49e2-aa81-53785bf62add
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371490843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2371490843
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4034171126
Short name T229
Test name
Test status
Simulation time 693008026 ps
CPU time 9.06 seconds
Started Aug 18 05:51:38 PM PDT 24
Finished Aug 18 05:51:48 PM PDT 24
Peak memory 211096 kb
Host smart-aebc22d2-a9d5-4ff4-b750-715022bf7b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034171126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4034171126
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3057249244
Short name T60
Test name
Test status
Simulation time 385945661 ps
CPU time 5.28 seconds
Started Aug 18 05:51:52 PM PDT 24
Finished Aug 18 05:51:57 PM PDT 24
Peak memory 211080 kb
Host smart-20ec5db2-4f47-4e8d-905d-3ca4bc2025bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3057249244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3057249244
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3938074298
Short name T52
Test name
Test status
Simulation time 1023798427 ps
CPU time 68.75 seconds
Started Aug 18 05:52:47 PM PDT 24
Finished Aug 18 05:53:56 PM PDT 24
Peak memory 213172 kb
Host smart-3b8689a8-917d-4e78-9876-a4af3ab0bced
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938074298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3938074298
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.326218364
Short name T106
Test name
Test status
Simulation time 1473124239 ps
CPU time 68.21 seconds
Started Aug 18 05:52:45 PM PDT 24
Finished Aug 18 05:53:53 PM PDT 24
Peak memory 219572 kb
Host smart-f61d0ce6-1bd9-447b-a621-14a66d5ac0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326218364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.326218364
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1864498161
Short name T153
Test name
Test status
Simulation time 9695834421 ps
CPU time 88.41 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:53:29 PM PDT 24
Peak memory 222768 kb
Host smart-d4227d8f-7376-4477-9702-22883b29b74e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864498161 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1864498161
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1880271638
Short name T86
Test name
Test status
Simulation time 846600350 ps
CPU time 5.67 seconds
Started Aug 18 05:51:38 PM PDT 24
Finished Aug 18 05:51:44 PM PDT 24
Peak memory 211112 kb
Host smart-d1c28c24-c33b-4a8e-baf0-f28dafb269fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1880271638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1880271638
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4053975074
Short name T27
Test name
Test status
Simulation time 140913352 ps
CPU time 6.19 seconds
Started Aug 18 05:51:40 PM PDT 24
Finished Aug 18 05:51:46 PM PDT 24
Peak memory 211108 kb
Host smart-0f513f87-bd9b-4cf8-b809-499284996dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053975074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4053975074
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.864564411
Short name T83
Test name
Test status
Simulation time 837653418 ps
CPU time 4.07 seconds
Started Aug 18 05:52:32 PM PDT 24
Finished Aug 18 05:52:36 PM PDT 24
Peak memory 211356 kb
Host smart-d57c3b6e-df84-4ce8-a7bf-844bd7d7f2d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864564411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.864564411
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.739466451
Short name T402
Test name
Test status
Simulation time 334973486 ps
CPU time 4.22 seconds
Started Aug 18 05:52:35 PM PDT 24
Finished Aug 18 05:52:40 PM PDT 24
Peak memory 219520 kb
Host smart-6888c3f2-f43e-4fd0-81ad-a89a72cc432a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739466451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.739466451
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2331431086
Short name T85
Test name
Test status
Simulation time 524421443 ps
CPU time 6.18 seconds
Started Aug 18 05:52:33 PM PDT 24
Finished Aug 18 05:52:39 PM PDT 24
Peak memory 211412 kb
Host smart-208a5c8b-f911-48f3-84f2-030b2ddaeb45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331431086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2331431086
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4112993547
Short name T396
Test name
Test status
Simulation time 178199227 ps
CPU time 5.56 seconds
Started Aug 18 05:52:33 PM PDT 24
Finished Aug 18 05:52:39 PM PDT 24
Peak memory 219588 kb
Host smart-c8c8b6b2-b3fd-40f5-92cd-158097f33947
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112993547 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4112993547
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2263036998
Short name T100
Test name
Test status
Simulation time 514161441 ps
CPU time 6.91 seconds
Started Aug 18 05:52:35 PM PDT 24
Finished Aug 18 05:52:42 PM PDT 24
Peak memory 218416 kb
Host smart-57becf81-b161-436c-9d53-9d09eaca4c58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263036998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2263036998
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.831747065
Short name T372
Test name
Test status
Simulation time 155561123 ps
CPU time 3.96 seconds
Started Aug 18 05:52:33 PM PDT 24
Finished Aug 18 05:52:37 PM PDT 24
Peak memory 211324 kb
Host smart-91bc8501-93a3-47f9-a280-7c961c6c4da7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831747065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.831747065
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3456281763
Short name T400
Test name
Test status
Simulation time 363765702 ps
CPU time 4.2 seconds
Started Aug 18 05:52:32 PM PDT 24
Finished Aug 18 05:52:37 PM PDT 24
Peak memory 211328 kb
Host smart-4a9ca493-fd9f-464a-9331-20459ef9a4bd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456281763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3456281763
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3342405301
Short name T81
Test name
Test status
Simulation time 1325799882 ps
CPU time 18.39 seconds
Started Aug 18 05:52:33 PM PDT 24
Finished Aug 18 05:52:52 PM PDT 24
Peak memory 211432 kb
Host smart-f2eed944-e972-44c5-b7eb-8dc91c85e8ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342405301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3342405301
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1672563168
Short name T414
Test name
Test status
Simulation time 98279520 ps
CPU time 5.93 seconds
Started Aug 18 05:52:34 PM PDT 24
Finished Aug 18 05:52:40 PM PDT 24
Peak memory 219548 kb
Host smart-2389670c-f67c-48b9-86e3-e9021242e5d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672563168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1672563168
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.715741140
Short name T454
Test name
Test status
Simulation time 179296512 ps
CPU time 8.67 seconds
Started Aug 18 05:52:32 PM PDT 24
Finished Aug 18 05:52:40 PM PDT 24
Peak memory 215424 kb
Host smart-89fe07ce-0e65-4758-b018-7c0d3ba31e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715741140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.715741140
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.763733534
Short name T436
Test name
Test status
Simulation time 221132845 ps
CPU time 37.04 seconds
Started Aug 18 05:52:32 PM PDT 24
Finished Aug 18 05:53:09 PM PDT 24
Peak memory 213100 kb
Host smart-a35c38b8-70ba-410d-9274-c7c413785711
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763733534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.763733534
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2424997075
Short name T410
Test name
Test status
Simulation time 88885987 ps
CPU time 4.05 seconds
Started Aug 18 05:52:32 PM PDT 24
Finished Aug 18 05:52:36 PM PDT 24
Peak memory 211344 kb
Host smart-b50875e3-0b72-4ab5-936c-0d381df5fbeb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424997075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2424997075
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4253345615
Short name T354
Test name
Test status
Simulation time 175687199 ps
CPU time 4.25 seconds
Started Aug 18 05:52:38 PM PDT 24
Finished Aug 18 05:52:42 PM PDT 24
Peak memory 219544 kb
Host smart-f31dfcdf-7f0d-409a-ac5f-3be8c9527d78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253345615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4253345615
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1863137836
Short name T362
Test name
Test status
Simulation time 405574950 ps
CPU time 7.3 seconds
Started Aug 18 05:52:35 PM PDT 24
Finished Aug 18 05:52:43 PM PDT 24
Peak memory 219564 kb
Host smart-8ed967a5-bc15-44ad-b4e6-f0f21624a376
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863137836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1863137836
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1110424614
Short name T384
Test name
Test status
Simulation time 504763937 ps
CPU time 4.84 seconds
Started Aug 18 05:52:38 PM PDT 24
Finished Aug 18 05:52:43 PM PDT 24
Peak memory 216084 kb
Host smart-b315cd27-1a5a-4509-98ba-642958666629
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110424614 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1110424614
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1730277061
Short name T357
Test name
Test status
Simulation time 959801888 ps
CPU time 4.8 seconds
Started Aug 18 05:52:32 PM PDT 24
Finished Aug 18 05:52:37 PM PDT 24
Peak memory 218184 kb
Host smart-dad4d2bd-a076-4779-825e-06da7c043c24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730277061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1730277061
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1674499747
Short name T401
Test name
Test status
Simulation time 396297435 ps
CPU time 3.89 seconds
Started Aug 18 05:52:35 PM PDT 24
Finished Aug 18 05:52:39 PM PDT 24
Peak memory 211280 kb
Host smart-7b4e3801-47ce-4ee2-b27f-b66b3b6253b3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674499747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1674499747
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4270572112
Short name T415
Test name
Test status
Simulation time 88202162 ps
CPU time 3.93 seconds
Started Aug 18 05:52:33 PM PDT 24
Finished Aug 18 05:52:37 PM PDT 24
Peak memory 211344 kb
Host smart-f4ccd274-b349-42e0-b7cf-98895d104d1c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270572112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4270572112
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.476197374
Short name T378
Test name
Test status
Simulation time 7818859344 ps
CPU time 31.13 seconds
Started Aug 18 05:52:32 PM PDT 24
Finished Aug 18 05:53:04 PM PDT 24
Peak memory 211624 kb
Host smart-d07d4172-f031-4b37-9d6e-0961152cede7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476197374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.476197374
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1960763266
Short name T374
Test name
Test status
Simulation time 800393277 ps
CPU time 6.33 seconds
Started Aug 18 05:52:32 PM PDT 24
Finished Aug 18 05:52:39 PM PDT 24
Peak memory 219544 kb
Host smart-b7870e3d-55ad-40a4-bef8-81a463445447
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960763266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1960763266
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1569206357
Short name T427
Test name
Test status
Simulation time 130952285 ps
CPU time 7.2 seconds
Started Aug 18 05:52:38 PM PDT 24
Finished Aug 18 05:52:46 PM PDT 24
Peak memory 216236 kb
Host smart-2b7f630c-256f-41e4-a68e-c0628fc4d56b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569206357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1569206357
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3471754947
Short name T376
Test name
Test status
Simulation time 132221830 ps
CPU time 5.08 seconds
Started Aug 18 05:52:58 PM PDT 24
Finished Aug 18 05:53:03 PM PDT 24
Peak memory 219604 kb
Host smart-16aa5933-d65d-41b0-aaf6-f67fe4c9ba58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471754947 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3471754947
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2364000973
Short name T409
Test name
Test status
Simulation time 88106154 ps
CPU time 4.12 seconds
Started Aug 18 05:52:44 PM PDT 24
Finished Aug 18 05:52:48 PM PDT 24
Peak memory 211340 kb
Host smart-325cfb8c-f774-4dfb-9e3c-1ecfd43d91de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364000973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2364000973
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.535350452
Short name T399
Test name
Test status
Simulation time 2192912908 ps
CPU time 20.89 seconds
Started Aug 18 05:52:42 PM PDT 24
Finished Aug 18 05:53:03 PM PDT 24
Peak memory 211516 kb
Host smart-7cd6cc75-aabf-4f6d-ba88-8d14a11016fd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535350452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.535350452
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2728520257
Short name T439
Test name
Test status
Simulation time 134009237 ps
CPU time 4.85 seconds
Started Aug 18 05:52:43 PM PDT 24
Finished Aug 18 05:52:48 PM PDT 24
Peak memory 218812 kb
Host smart-b487edd7-9e1c-4a4b-a50a-e929b25b2f04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728520257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2728520257
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.988723442
Short name T390
Test name
Test status
Simulation time 255168066 ps
CPU time 7.2 seconds
Started Aug 18 05:52:43 PM PDT 24
Finished Aug 18 05:52:50 PM PDT 24
Peak memory 219604 kb
Host smart-5195b5a2-723f-4a6e-8a95-5d12d9d7bdf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988723442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.988723442
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.550845264
Short name T54
Test name
Test status
Simulation time 708946888 ps
CPU time 36.25 seconds
Started Aug 18 05:52:40 PM PDT 24
Finished Aug 18 05:53:17 PM PDT 24
Peak memory 219560 kb
Host smart-319d3a3a-e12c-491b-8688-27bf0e2c4670
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550845264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.550845264
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.656957517
Short name T383
Test name
Test status
Simulation time 1249945372 ps
CPU time 4.2 seconds
Started Aug 18 05:52:55 PM PDT 24
Finished Aug 18 05:52:59 PM PDT 24
Peak memory 219584 kb
Host smart-c9b2f5ed-cdfd-430b-8b2e-6f24468b65e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656957517 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.656957517
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1418603414
Short name T84
Test name
Test status
Simulation time 252308821 ps
CPU time 4.76 seconds
Started Aug 18 05:52:49 PM PDT 24
Finished Aug 18 05:52:54 PM PDT 24
Peak memory 218692 kb
Host smart-2fe33568-3878-4244-be17-2dcbd5bed114
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418603414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1418603414
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.620262043
Short name T449
Test name
Test status
Simulation time 1488142169 ps
CPU time 17.66 seconds
Started Aug 18 05:52:52 PM PDT 24
Finished Aug 18 05:53:09 PM PDT 24
Peak memory 211352 kb
Host smart-557add7a-9aa7-494e-b70b-5f7cff44fda9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620262043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.620262043
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4260228426
Short name T96
Test name
Test status
Simulation time 181508493 ps
CPU time 6.09 seconds
Started Aug 18 05:52:50 PM PDT 24
Finished Aug 18 05:52:57 PM PDT 24
Peak memory 211408 kb
Host smart-91c1213f-5bec-455e-9d87-ab45e4f8af8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260228426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.4260228426
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1311325601
Short name T373
Test name
Test status
Simulation time 346272337 ps
CPU time 6.16 seconds
Started Aug 18 05:52:47 PM PDT 24
Finished Aug 18 05:52:53 PM PDT 24
Peak memory 219604 kb
Host smart-ce6b8565-fdf3-4c5f-9f6b-bd6699672577
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311325601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1311325601
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1820481137
Short name T113
Test name
Test status
Simulation time 621792041 ps
CPU time 69.42 seconds
Started Aug 18 05:52:51 PM PDT 24
Finished Aug 18 05:54:01 PM PDT 24
Peak memory 213272 kb
Host smart-520c5166-acba-444e-9d8f-47d04b9b9b7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820481137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1820481137
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2270715101
Short name T435
Test name
Test status
Simulation time 199938751 ps
CPU time 4.54 seconds
Started Aug 18 05:52:49 PM PDT 24
Finished Aug 18 05:52:53 PM PDT 24
Peak memory 214548 kb
Host smart-fcaae85b-8d7d-46ff-8e96-efc49f93bc7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270715101 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2270715101
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3920138140
Short name T405
Test name
Test status
Simulation time 519402102 ps
CPU time 6.58 seconds
Started Aug 18 05:52:50 PM PDT 24
Finished Aug 18 05:52:57 PM PDT 24
Peak memory 218216 kb
Host smart-cb580c0d-c741-46ef-aeed-ac896835c5d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920138140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3920138140
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.5408075
Short name T403
Test name
Test status
Simulation time 5125369019 ps
CPU time 17.91 seconds
Started Aug 18 05:52:58 PM PDT 24
Finished Aug 18 05:53:16 PM PDT 24
Peak memory 211552 kb
Host smart-6ed16b66-9ba5-4d9b-9653-6e63169bf9d9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5408075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pass
thru_mem_tl_intg_err.5408075
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1471617132
Short name T392
Test name
Test status
Simulation time 266341292 ps
CPU time 6.47 seconds
Started Aug 18 05:52:49 PM PDT 24
Finished Aug 18 05:52:56 PM PDT 24
Peak memory 211332 kb
Host smart-905bc2e5-94ab-4df8-a134-9eb072df9a71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471617132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1471617132
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2820219340
Short name T350
Test name
Test status
Simulation time 526361903 ps
CPU time 8.35 seconds
Started Aug 18 05:52:50 PM PDT 24
Finished Aug 18 05:52:59 PM PDT 24
Peak memory 219668 kb
Host smart-a5a3caba-4d25-4621-a73d-f0539319608f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820219340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2820219340
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3197717606
Short name T446
Test name
Test status
Simulation time 239201157 ps
CPU time 5.52 seconds
Started Aug 18 05:52:52 PM PDT 24
Finished Aug 18 05:52:58 PM PDT 24
Peak memory 215392 kb
Host smart-496ebe1c-4fa4-4aeb-896f-fa9e2a47be35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197717606 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3197717606
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.99876076
Short name T352
Test name
Test status
Simulation time 522617496 ps
CPU time 4.78 seconds
Started Aug 18 05:52:57 PM PDT 24
Finished Aug 18 05:53:02 PM PDT 24
Peak memory 218576 kb
Host smart-21b3cb8b-3465-43fb-a233-010c63ac38bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99876076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.99876076
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2575890513
Short name T76
Test name
Test status
Simulation time 586241825 ps
CPU time 26.28 seconds
Started Aug 18 05:52:50 PM PDT 24
Finished Aug 18 05:53:16 PM PDT 24
Peak memory 211380 kb
Host smart-a4b85465-d089-4085-a4de-396dec877ee2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575890513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2575890513
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1054622650
Short name T98
Test name
Test status
Simulation time 349527085 ps
CPU time 5.81 seconds
Started Aug 18 05:52:49 PM PDT 24
Finished Aug 18 05:52:55 PM PDT 24
Peak memory 211896 kb
Host smart-6d595a2e-983d-4e07-b789-8dae71c37afd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054622650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1054622650
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.647035521
Short name T404
Test name
Test status
Simulation time 892126742 ps
CPU time 6.75 seconds
Started Aug 18 05:52:57 PM PDT 24
Finished Aug 18 05:53:04 PM PDT 24
Peak memory 219676 kb
Host smart-64d04c19-5358-4896-9b97-dbc4403dd91e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647035521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.647035521
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.793083882
Short name T375
Test name
Test status
Simulation time 301507194 ps
CPU time 4.29 seconds
Started Aug 18 05:52:58 PM PDT 24
Finished Aug 18 05:53:03 PM PDT 24
Peak memory 214144 kb
Host smart-85a6b726-2490-4b08-8292-791938df06ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793083882 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.793083882
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2852075074
Short name T366
Test name
Test status
Simulation time 396084175 ps
CPU time 4.15 seconds
Started Aug 18 05:52:51 PM PDT 24
Finished Aug 18 05:52:55 PM PDT 24
Peak memory 219540 kb
Host smart-d986b993-8fad-48ca-b716-6815a8ea0c7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852075074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2852075074
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4273377308
Short name T370
Test name
Test status
Simulation time 1029248400 ps
CPU time 20.86 seconds
Started Aug 18 05:52:50 PM PDT 24
Finished Aug 18 05:53:11 PM PDT 24
Peak memory 211448 kb
Host smart-5d534741-7313-49b4-af09-6dfc2bc3e0a3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273377308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4273377308
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3799012989
Short name T408
Test name
Test status
Simulation time 337115847 ps
CPU time 4.15 seconds
Started Aug 18 05:53:00 PM PDT 24
Finished Aug 18 05:53:04 PM PDT 24
Peak memory 219544 kb
Host smart-68082bc9-660d-4ff7-8535-42a77bcfa27a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799012989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3799012989
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1338681881
Short name T425
Test name
Test status
Simulation time 326577227 ps
CPU time 9.44 seconds
Started Aug 18 05:52:50 PM PDT 24
Finished Aug 18 05:53:00 PM PDT 24
Peak memory 219668 kb
Host smart-f16596da-7e6f-4309-99a5-064336704aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338681881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1338681881
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.246211596
Short name T107
Test name
Test status
Simulation time 796646871 ps
CPU time 37.11 seconds
Started Aug 18 05:52:51 PM PDT 24
Finished Aug 18 05:53:28 PM PDT 24
Peak memory 212040 kb
Host smart-a0f53ac7-81fc-47a2-8f4e-c54031ef4e81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246211596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.246211596
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4260394224
Short name T417
Test name
Test status
Simulation time 527510688 ps
CPU time 4.97 seconds
Started Aug 18 05:52:51 PM PDT 24
Finished Aug 18 05:52:56 PM PDT 24
Peak memory 215076 kb
Host smart-28639784-1e7f-4cb5-b964-40334446606d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260394224 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.4260394224
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3204600159
Short name T74
Test name
Test status
Simulation time 127607075 ps
CPU time 4.75 seconds
Started Aug 18 05:52:51 PM PDT 24
Finished Aug 18 05:52:56 PM PDT 24
Peak memory 211380 kb
Host smart-898aad81-c7f4-4d21-b38b-1d6e89fe9f2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204600159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3204600159
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2154833228
Short name T416
Test name
Test status
Simulation time 182475762 ps
CPU time 6.11 seconds
Started Aug 18 05:52:51 PM PDT 24
Finished Aug 18 05:52:58 PM PDT 24
Peak memory 211812 kb
Host smart-1853e492-903e-464a-87f6-6a5a382ca41a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154833228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2154833228
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1584342738
Short name T355
Test name
Test status
Simulation time 502166600 ps
CPU time 8.94 seconds
Started Aug 18 05:52:52 PM PDT 24
Finished Aug 18 05:53:01 PM PDT 24
Peak memory 219648 kb
Host smart-b937ddff-0b51-4a41-80b9-c977f8bf0764
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584342738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1584342738
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1397265792
Short name T110
Test name
Test status
Simulation time 925978416 ps
CPU time 68.08 seconds
Started Aug 18 05:52:52 PM PDT 24
Finished Aug 18 05:54:00 PM PDT 24
Peak memory 211856 kb
Host smart-c8f9abd3-595f-44cb-b012-3e5d698e8707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397265792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1397265792
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3257846852
Short name T389
Test name
Test status
Simulation time 382116156 ps
CPU time 4.28 seconds
Started Aug 18 05:52:49 PM PDT 24
Finished Aug 18 05:52:54 PM PDT 24
Peak memory 214496 kb
Host smart-892aab3c-49c8-4330-bf9c-0acbc751e555
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257846852 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3257846852
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3406788110
Short name T447
Test name
Test status
Simulation time 260097650 ps
CPU time 4.7 seconds
Started Aug 18 05:53:00 PM PDT 24
Finished Aug 18 05:53:05 PM PDT 24
Peak memory 211432 kb
Host smart-86ee9fdd-ad81-457c-9526-c61f4b98ed8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406788110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3406788110
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1553107088
Short name T397
Test name
Test status
Simulation time 533942532 ps
CPU time 20.56 seconds
Started Aug 18 05:52:48 PM PDT 24
Finished Aug 18 05:53:09 PM PDT 24
Peak memory 211432 kb
Host smart-079dad1a-5dbd-48f2-81d0-dcf8da1687cb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553107088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1553107088
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.651377696
Short name T419
Test name
Test status
Simulation time 511516765 ps
CPU time 6.39 seconds
Started Aug 18 05:52:50 PM PDT 24
Finished Aug 18 05:52:57 PM PDT 24
Peak memory 219576 kb
Host smart-d405164e-babb-432a-a8ee-e3497cc08609
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651377696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.651377696
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.580701289
Short name T420
Test name
Test status
Simulation time 363016753 ps
CPU time 6.19 seconds
Started Aug 18 05:52:59 PM PDT 24
Finished Aug 18 05:53:06 PM PDT 24
Peak memory 217336 kb
Host smart-7d40b146-c7d0-4950-8364-9e3d177179df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580701289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.580701289
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3527820759
Short name T437
Test name
Test status
Simulation time 364554775 ps
CPU time 38.12 seconds
Started Aug 18 05:52:50 PM PDT 24
Finished Aug 18 05:53:28 PM PDT 24
Peak memory 212868 kb
Host smart-8eebe177-71f6-41b8-8144-56b826529d28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527820759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3527820759
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.475287742
Short name T353
Test name
Test status
Simulation time 362837987 ps
CPU time 4.22 seconds
Started Aug 18 05:52:51 PM PDT 24
Finished Aug 18 05:52:55 PM PDT 24
Peak memory 219572 kb
Host smart-d9c8daef-505e-4e89-8c09-d08216bd54c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475287742 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.475287742
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.818534687
Short name T80
Test name
Test status
Simulation time 171791168 ps
CPU time 4.76 seconds
Started Aug 18 05:52:49 PM PDT 24
Finished Aug 18 05:52:54 PM PDT 24
Peak memory 211412 kb
Host smart-74bcb426-80df-49e3-adc2-ccdea438bb85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818534687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.818534687
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.328270849
Short name T66
Test name
Test status
Simulation time 11978779203 ps
CPU time 41.6 seconds
Started Aug 18 05:52:57 PM PDT 24
Finished Aug 18 05:53:39 PM PDT 24
Peak memory 211692 kb
Host smart-91d5f59f-ee5e-4405-a81e-54069b0f0cf8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328270849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.328270849
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3908583137
Short name T406
Test name
Test status
Simulation time 85438222 ps
CPU time 4.18 seconds
Started Aug 18 05:52:51 PM PDT 24
Finished Aug 18 05:52:56 PM PDT 24
Peak memory 218924 kb
Host smart-5b272199-8809-48ef-be5a-9d7b76f2d076
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908583137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3908583137
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1829497934
Short name T428
Test name
Test status
Simulation time 691526865 ps
CPU time 9.21 seconds
Started Aug 18 05:52:51 PM PDT 24
Finished Aug 18 05:53:00 PM PDT 24
Peak memory 219648 kb
Host smart-291140f4-0da4-429d-a123-8059d050f028
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829497934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1829497934
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2341868205
Short name T111
Test name
Test status
Simulation time 1095424810 ps
CPU time 69.05 seconds
Started Aug 18 05:53:00 PM PDT 24
Finished Aug 18 05:54:09 PM PDT 24
Peak memory 213180 kb
Host smart-d212a241-f014-4020-8dba-a68aefa87d3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341868205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2341868205
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2532691149
Short name T452
Test name
Test status
Simulation time 355268735 ps
CPU time 4.62 seconds
Started Aug 18 05:52:55 PM PDT 24
Finished Aug 18 05:52:59 PM PDT 24
Peak memory 215864 kb
Host smart-fd3794e5-4c1e-4c34-8506-1894c5e87184
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532691149 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2532691149
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3641385064
Short name T444
Test name
Test status
Simulation time 261486858 ps
CPU time 4.74 seconds
Started Aug 18 05:52:49 PM PDT 24
Finished Aug 18 05:52:54 PM PDT 24
Peak memory 218408 kb
Host smart-76a393a4-767e-4ce3-8f5d-70c11565a71f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641385064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3641385064
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2965810662
Short name T75
Test name
Test status
Simulation time 3028917123 ps
CPU time 31.6 seconds
Started Aug 18 05:52:52 PM PDT 24
Finished Aug 18 05:53:24 PM PDT 24
Peak memory 211536 kb
Host smart-bd58ae5b-aa63-48bf-9d0a-2813d9d6e315
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965810662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2965810662
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1201983731
Short name T382
Test name
Test status
Simulation time 1245262000 ps
CPU time 4.81 seconds
Started Aug 18 05:52:55 PM PDT 24
Finished Aug 18 05:53:00 PM PDT 24
Peak memory 218700 kb
Host smart-ef004332-2b3e-4fcb-bff8-631a532d8483
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201983731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1201983731
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.365337134
Short name T411
Test name
Test status
Simulation time 373934224 ps
CPU time 8.05 seconds
Started Aug 18 05:52:53 PM PDT 24
Finished Aug 18 05:53:01 PM PDT 24
Peak memory 219612 kb
Host smart-6cb49bb2-a002-41bc-8253-686ec007b57a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365337134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.365337134
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.928961337
Short name T448
Test name
Test status
Simulation time 281845238 ps
CPU time 35.62 seconds
Started Aug 18 05:53:00 PM PDT 24
Finished Aug 18 05:53:36 PM PDT 24
Peak memory 212008 kb
Host smart-127d1c63-ee37-4b62-90a0-feb403be0da0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928961337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.928961337
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.125294012
Short name T361
Test name
Test status
Simulation time 599144326 ps
CPU time 4.87 seconds
Started Aug 18 05:52:49 PM PDT 24
Finished Aug 18 05:52:54 PM PDT 24
Peak memory 219672 kb
Host smart-59be5d7f-5288-4847-8bd9-afc1ef534cd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125294012 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.125294012
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2313776285
Short name T78
Test name
Test status
Simulation time 524205842 ps
CPU time 4 seconds
Started Aug 18 05:52:59 PM PDT 24
Finished Aug 18 05:53:03 PM PDT 24
Peak memory 211436 kb
Host smart-1d792475-d037-4b60-b4f1-42ce8d7a1400
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313776285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2313776285
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4261570958
Short name T79
Test name
Test status
Simulation time 2171958540 ps
CPU time 20.48 seconds
Started Aug 18 05:52:55 PM PDT 24
Finished Aug 18 05:53:15 PM PDT 24
Peak memory 211480 kb
Host smart-526c88f5-bc98-49ae-9c5e-03df9d85ee08
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261570958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.4261570958
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2550304173
Short name T97
Test name
Test status
Simulation time 382608488 ps
CPU time 4.05 seconds
Started Aug 18 05:52:51 PM PDT 24
Finished Aug 18 05:52:55 PM PDT 24
Peak memory 218908 kb
Host smart-fe4ff860-5d85-4b0a-ab86-5e1f9cb9a3d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550304173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2550304173
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1925643347
Short name T429
Test name
Test status
Simulation time 257152857 ps
CPU time 7.84 seconds
Started Aug 18 05:52:49 PM PDT 24
Finished Aug 18 05:52:57 PM PDT 24
Peak memory 216300 kb
Host smart-29209822-f129-4170-822f-56de3e3e0b18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925643347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1925643347
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3850211385
Short name T418
Test name
Test status
Simulation time 689897344 ps
CPU time 35.72 seconds
Started Aug 18 05:52:51 PM PDT 24
Finished Aug 18 05:53:27 PM PDT 24
Peak memory 219556 kb
Host smart-cb76c3bc-0b72-4e1d-973c-93f22ddd3df9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850211385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3850211385
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1725125142
Short name T61
Test name
Test status
Simulation time 127067401 ps
CPU time 4.93 seconds
Started Aug 18 05:52:47 PM PDT 24
Finished Aug 18 05:52:52 PM PDT 24
Peak memory 211428 kb
Host smart-a66b8625-8ebc-4f02-b1b6-337fa55a4d2f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725125142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1725125142
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2694589918
Short name T453
Test name
Test status
Simulation time 132046191 ps
CPU time 5.05 seconds
Started Aug 18 05:52:46 PM PDT 24
Finished Aug 18 05:52:51 PM PDT 24
Peak memory 211340 kb
Host smart-4f038754-1263-4146-a501-a1470029b8c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694589918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2694589918
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4142254809
Short name T63
Test name
Test status
Simulation time 311078442 ps
CPU time 7.08 seconds
Started Aug 18 05:52:38 PM PDT 24
Finished Aug 18 05:52:45 PM PDT 24
Peak memory 219568 kb
Host smart-c22a9c1b-f58f-46a3-a892-4734f8809e3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142254809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4142254809
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.201211202
Short name T387
Test name
Test status
Simulation time 642007735 ps
CPU time 4.76 seconds
Started Aug 18 05:52:42 PM PDT 24
Finished Aug 18 05:52:47 PM PDT 24
Peak memory 219660 kb
Host smart-24cacaac-589b-49b7-8baa-27a406921e0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201211202 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.201211202
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1899618882
Short name T442
Test name
Test status
Simulation time 132162087 ps
CPU time 4.87 seconds
Started Aug 18 05:52:34 PM PDT 24
Finished Aug 18 05:52:39 PM PDT 24
Peak memory 211356 kb
Host smart-0922d53a-6e63-44d6-9913-985ea5786e9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899618882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1899618882
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3087586312
Short name T368
Test name
Test status
Simulation time 86408382 ps
CPU time 3.95 seconds
Started Aug 18 05:52:34 PM PDT 24
Finished Aug 18 05:52:38 PM PDT 24
Peak memory 211340 kb
Host smart-f32f57e4-6b9f-43a2-955b-628b8cc1cb5d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087586312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3087586312
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3968937766
Short name T386
Test name
Test status
Simulation time 336009526 ps
CPU time 3.99 seconds
Started Aug 18 05:52:35 PM PDT 24
Finished Aug 18 05:52:39 PM PDT 24
Peak memory 211320 kb
Host smart-d4c84852-5f6b-497b-9ea5-5d92a3840730
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968937766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3968937766
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3631659063
Short name T380
Test name
Test status
Simulation time 805110253 ps
CPU time 30.38 seconds
Started Aug 18 05:52:31 PM PDT 24
Finished Aug 18 05:53:02 PM PDT 24
Peak memory 211408 kb
Host smart-884abf5a-7857-4d18-9089-27a4cbafa25f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631659063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3631659063
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4211933572
Short name T391
Test name
Test status
Simulation time 500455185 ps
CPU time 4.82 seconds
Started Aug 18 05:52:46 PM PDT 24
Finished Aug 18 05:52:51 PM PDT 24
Peak memory 218868 kb
Host smart-105f6a1c-a86e-47af-a402-2180728a3a2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211933572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.4211933572
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2254743271
Short name T424
Test name
Test status
Simulation time 127374861 ps
CPU time 6.83 seconds
Started Aug 18 05:52:39 PM PDT 24
Finished Aug 18 05:52:46 PM PDT 24
Peak memory 219672 kb
Host smart-2fe6194f-9b86-425d-b543-cff68cf629f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254743271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2254743271
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.688031279
Short name T53
Test name
Test status
Simulation time 510112131 ps
CPU time 68.13 seconds
Started Aug 18 05:52:34 PM PDT 24
Finished Aug 18 05:53:42 PM PDT 24
Peak memory 213212 kb
Host smart-be2c19ec-4c6a-431d-be79-0e4599b78e84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688031279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.688031279
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1272253352
Short name T395
Test name
Test status
Simulation time 130558769 ps
CPU time 4.97 seconds
Started Aug 18 05:52:43 PM PDT 24
Finished Aug 18 05:52:48 PM PDT 24
Peak memory 211328 kb
Host smart-14746a37-65d8-416c-9d55-0dc3c97a66b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272253352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1272253352
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2194472765
Short name T434
Test name
Test status
Simulation time 309634342 ps
CPU time 4.11 seconds
Started Aug 18 05:52:41 PM PDT 24
Finished Aug 18 05:52:46 PM PDT 24
Peak memory 218112 kb
Host smart-6fbdc9b3-10d5-4320-a06a-25b3f872d073
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194472765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2194472765
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.577036092
Short name T421
Test name
Test status
Simulation time 98596975 ps
CPU time 7.2 seconds
Started Aug 18 05:52:41 PM PDT 24
Finished Aug 18 05:52:48 PM PDT 24
Peak memory 211280 kb
Host smart-d3a1ed92-8da5-496c-b33f-16326746fe7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577036092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.577036092
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3016730286
Short name T351
Test name
Test status
Simulation time 252073882 ps
CPU time 4.99 seconds
Started Aug 18 05:52:42 PM PDT 24
Finished Aug 18 05:52:47 PM PDT 24
Peak memory 213284 kb
Host smart-3bbf2723-b748-420c-84c3-5e77051287a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016730286 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3016730286
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2121948944
Short name T56
Test name
Test status
Simulation time 126487646 ps
CPU time 4.7 seconds
Started Aug 18 05:52:40 PM PDT 24
Finished Aug 18 05:52:45 PM PDT 24
Peak memory 211348 kb
Host smart-483c5013-f5e0-4150-84bf-628fdf4cb61d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121948944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2121948944
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.185555183
Short name T369
Test name
Test status
Simulation time 127278654 ps
CPU time 4.75 seconds
Started Aug 18 05:52:44 PM PDT 24
Finished Aug 18 05:52:48 PM PDT 24
Peak memory 211316 kb
Host smart-078c17c0-3d95-462b-b038-03464f946b01
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185555183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.185555183
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1265483926
Short name T398
Test name
Test status
Simulation time 87480548 ps
CPU time 3.92 seconds
Started Aug 18 05:52:39 PM PDT 24
Finished Aug 18 05:52:43 PM PDT 24
Peak memory 211296 kb
Host smart-ba2a5d62-ddb5-421b-9713-0240c28b37e4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265483926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1265483926
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.750803028
Short name T412
Test name
Test status
Simulation time 135270067 ps
CPU time 6.64 seconds
Started Aug 18 05:52:44 PM PDT 24
Finished Aug 18 05:52:51 PM PDT 24
Peak memory 219516 kb
Host smart-34217a17-c675-4fe0-8ad9-1d1b0db99c13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750803028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.750803028
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1419494440
Short name T388
Test name
Test status
Simulation time 345484633 ps
CPU time 8.94 seconds
Started Aug 18 05:52:45 PM PDT 24
Finished Aug 18 05:52:54 PM PDT 24
Peak memory 215464 kb
Host smart-9f9a6265-7016-48e4-9c03-49c6031d02b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419494440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1419494440
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2434066821
Short name T115
Test name
Test status
Simulation time 883719992 ps
CPU time 35.03 seconds
Started Aug 18 05:52:42 PM PDT 24
Finished Aug 18 05:53:17 PM PDT 24
Peak memory 219572 kb
Host smart-f3460a5e-46c3-46ac-9601-b9be0873e12a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434066821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2434066821
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1856850393
Short name T426
Test name
Test status
Simulation time 128010349 ps
CPU time 4.86 seconds
Started Aug 18 05:52:44 PM PDT 24
Finished Aug 18 05:52:49 PM PDT 24
Peak memory 211428 kb
Host smart-f7632456-9fcc-40dc-880f-efa17b0e17cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856850393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1856850393
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2306214263
Short name T413
Test name
Test status
Simulation time 88946971 ps
CPU time 4.52 seconds
Started Aug 18 05:52:47 PM PDT 24
Finished Aug 18 05:52:51 PM PDT 24
Peak memory 211396 kb
Host smart-c49ca12d-4f1b-47dc-8fe5-36c24efc41d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306214263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2306214263
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1123863959
Short name T377
Test name
Test status
Simulation time 418173780 ps
CPU time 7.09 seconds
Started Aug 18 05:52:41 PM PDT 24
Finished Aug 18 05:52:48 PM PDT 24
Peak memory 211408 kb
Host smart-fa311f17-931d-4831-91aa-26fe123f4ecf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123863959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1123863959
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.781718228
Short name T433
Test name
Test status
Simulation time 522516456 ps
CPU time 5.51 seconds
Started Aug 18 05:52:40 PM PDT 24
Finished Aug 18 05:52:46 PM PDT 24
Peak memory 216344 kb
Host smart-e6fdb411-5157-41d0-ab1b-a40dd59a178f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781718228 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.781718228
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3068179802
Short name T67
Test name
Test status
Simulation time 126571656 ps
CPU time 4.72 seconds
Started Aug 18 05:52:44 PM PDT 24
Finished Aug 18 05:52:48 PM PDT 24
Peak memory 211380 kb
Host smart-ed25bd02-165f-4402-901a-cde8f642fe8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068179802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3068179802
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1985675952
Short name T358
Test name
Test status
Simulation time 92065874 ps
CPU time 4.25 seconds
Started Aug 18 05:52:41 PM PDT 24
Finished Aug 18 05:52:46 PM PDT 24
Peak memory 211264 kb
Host smart-79ff784a-1b6e-4820-b744-29bb35e656a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985675952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1985675952
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2366474494
Short name T407
Test name
Test status
Simulation time 85891467 ps
CPU time 4.08 seconds
Started Aug 18 05:52:40 PM PDT 24
Finished Aug 18 05:52:44 PM PDT 24
Peak memory 211296 kb
Host smart-dabb35b3-21c9-42f3-be07-fe50faebab75
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366474494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2366474494
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.188526631
Short name T77
Test name
Test status
Simulation time 3268199044 ps
CPU time 30.23 seconds
Started Aug 18 05:52:43 PM PDT 24
Finished Aug 18 05:53:14 PM PDT 24
Peak memory 211568 kb
Host smart-9022b8d0-0dc0-4aa3-9e8d-85832653e7bb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188526631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.188526631
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3117161674
Short name T367
Test name
Test status
Simulation time 334002893 ps
CPU time 4.09 seconds
Started Aug 18 05:52:43 PM PDT 24
Finished Aug 18 05:52:47 PM PDT 24
Peak memory 219520 kb
Host smart-d5c51297-cf51-4946-bcf7-31320c7c2fc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117161674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3117161674
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2109690528
Short name T450
Test name
Test status
Simulation time 155172254 ps
CPU time 6.59 seconds
Started Aug 18 05:52:44 PM PDT 24
Finished Aug 18 05:52:50 PM PDT 24
Peak memory 219692 kb
Host smart-e8d33946-0136-4304-85ec-e4bd17e9306a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109690528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2109690528
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1365817073
Short name T108
Test name
Test status
Simulation time 731888931 ps
CPU time 69.15 seconds
Started Aug 18 05:52:41 PM PDT 24
Finished Aug 18 05:53:50 PM PDT 24
Peak memory 212024 kb
Host smart-736047ad-38e5-4d74-9570-10b1916b90ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365817073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1365817073
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.795074577
Short name T394
Test name
Test status
Simulation time 196239295 ps
CPU time 4.83 seconds
Started Aug 18 05:52:44 PM PDT 24
Finished Aug 18 05:52:49 PM PDT 24
Peak memory 219604 kb
Host smart-eda5f422-73e8-4fd5-87ac-ee2303625172
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795074577 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.795074577
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2644786029
Short name T451
Test name
Test status
Simulation time 2900924730 ps
CPU time 6.69 seconds
Started Aug 18 05:52:44 PM PDT 24
Finished Aug 18 05:52:51 PM PDT 24
Peak memory 211556 kb
Host smart-4e5b1916-8111-4850-af05-5cc0f436f2a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644786029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2644786029
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1259152977
Short name T381
Test name
Test status
Simulation time 3122940967 ps
CPU time 31.42 seconds
Started Aug 18 05:52:42 PM PDT 24
Finished Aug 18 05:53:14 PM PDT 24
Peak memory 211552 kb
Host smart-db844f03-2f62-40ec-948f-735897361098
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259152977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1259152977
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1194019893
Short name T57
Test name
Test status
Simulation time 351477407 ps
CPU time 4.05 seconds
Started Aug 18 05:52:41 PM PDT 24
Finished Aug 18 05:52:45 PM PDT 24
Peak memory 219576 kb
Host smart-823caad0-2a84-4f99-ab3e-69461f822bc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194019893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1194019893
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2883659781
Short name T360
Test name
Test status
Simulation time 1977259837 ps
CPU time 10.35 seconds
Started Aug 18 05:52:41 PM PDT 24
Finished Aug 18 05:52:51 PM PDT 24
Peak memory 219636 kb
Host smart-e858295a-1e72-473c-9c22-991b77f4f9ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883659781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2883659781
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1917408650
Short name T438
Test name
Test status
Simulation time 694600259 ps
CPU time 36.57 seconds
Started Aug 18 05:52:42 PM PDT 24
Finished Aug 18 05:53:19 PM PDT 24
Peak memory 212056 kb
Host smart-c5366ad5-eb7d-4f97-891a-935e34e22ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917408650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1917408650
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2016439999
Short name T430
Test name
Test status
Simulation time 9870393633 ps
CPU time 6.89 seconds
Started Aug 18 05:52:44 PM PDT 24
Finished Aug 18 05:52:51 PM PDT 24
Peak memory 219756 kb
Host smart-c5c00b7f-71e9-42a8-aefa-faeff567b92b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016439999 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2016439999
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.646599044
Short name T443
Test name
Test status
Simulation time 141322805 ps
CPU time 4.15 seconds
Started Aug 18 05:52:44 PM PDT 24
Finished Aug 18 05:52:48 PM PDT 24
Peak memory 219564 kb
Host smart-31350fb0-0e8e-4544-906b-d0ac9d880299
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646599044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.646599044
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.105841029
Short name T64
Test name
Test status
Simulation time 532890596 ps
CPU time 21.13 seconds
Started Aug 18 05:52:42 PM PDT 24
Finished Aug 18 05:53:03 PM PDT 24
Peak memory 211416 kb
Host smart-37211fc8-dc36-4e89-a55a-d8aa0c341306
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105841029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.105841029
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1854507387
Short name T423
Test name
Test status
Simulation time 349479433 ps
CPU time 4.19 seconds
Started Aug 18 05:52:41 PM PDT 24
Finished Aug 18 05:52:46 PM PDT 24
Peak memory 211440 kb
Host smart-f392db55-4b77-42e4-823a-e96e40f8d77c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854507387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1854507387
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.538131205
Short name T431
Test name
Test status
Simulation time 524878249 ps
CPU time 10.91 seconds
Started Aug 18 05:52:41 PM PDT 24
Finished Aug 18 05:52:52 PM PDT 24
Peak memory 216568 kb
Host smart-6e787dbc-021d-4d33-98db-3ac5ca445fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538131205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.538131205
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1700396822
Short name T114
Test name
Test status
Simulation time 664008931 ps
CPU time 36.25 seconds
Started Aug 18 05:52:45 PM PDT 24
Finished Aug 18 05:53:21 PM PDT 24
Peak memory 212016 kb
Host smart-1694ce4f-376f-4a37-8b25-ca00b0f423b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700396822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1700396822
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.212668272
Short name T356
Test name
Test status
Simulation time 376353891 ps
CPU time 4.46 seconds
Started Aug 18 05:52:43 PM PDT 24
Finished Aug 18 05:52:47 PM PDT 24
Peak memory 215520 kb
Host smart-5b8b3add-4310-41a4-bc5e-a58c933a2530
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212668272 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.212668272
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.137460210
Short name T363
Test name
Test status
Simulation time 126827466 ps
CPU time 4.89 seconds
Started Aug 18 05:52:41 PM PDT 24
Finished Aug 18 05:52:46 PM PDT 24
Peak memory 211416 kb
Host smart-ad71cc55-211c-44e7-bc58-980515bd8875
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137460210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.137460210
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3494313725
Short name T55
Test name
Test status
Simulation time 1953328484 ps
CPU time 29.85 seconds
Started Aug 18 05:52:44 PM PDT 24
Finished Aug 18 05:53:14 PM PDT 24
Peak memory 211444 kb
Host smart-b360d4db-c960-443d-b2bd-5a3b829990fb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494313725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3494313725
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1864243250
Short name T371
Test name
Test status
Simulation time 175162342 ps
CPU time 4.14 seconds
Started Aug 18 05:52:48 PM PDT 24
Finished Aug 18 05:52:52 PM PDT 24
Peak memory 218584 kb
Host smart-f78cc0c0-175a-442e-b346-220cc377bdbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864243250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1864243250
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2985242516
Short name T379
Test name
Test status
Simulation time 259852904 ps
CPU time 7.86 seconds
Started Aug 18 05:52:43 PM PDT 24
Finished Aug 18 05:52:51 PM PDT 24
Peak memory 219664 kb
Host smart-58eea7cb-78c2-491f-8177-d1f5fcfcae67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985242516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2985242516
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.908355883
Short name T365
Test name
Test status
Simulation time 135446694 ps
CPU time 5.31 seconds
Started Aug 18 05:52:47 PM PDT 24
Finished Aug 18 05:52:53 PM PDT 24
Peak memory 219616 kb
Host smart-3f01ed4e-3bcb-42a5-884f-1f283d448241
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908355883 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.908355883
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4217551202
Short name T82
Test name
Test status
Simulation time 334491590 ps
CPU time 4.24 seconds
Started Aug 18 05:52:44 PM PDT 24
Finished Aug 18 05:52:48 PM PDT 24
Peak memory 211444 kb
Host smart-79cedb87-e19c-4200-a6db-2e494d3f72c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217551202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4217551202
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2976827777
Short name T393
Test name
Test status
Simulation time 542802770 ps
CPU time 21.35 seconds
Started Aug 18 05:52:42 PM PDT 24
Finished Aug 18 05:53:04 PM PDT 24
Peak memory 211432 kb
Host smart-e256dc21-6cee-4df8-b1a2-208e159757d5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976827777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2976827777
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2218734623
Short name T65
Test name
Test status
Simulation time 499479350 ps
CPU time 4.82 seconds
Started Aug 18 05:52:44 PM PDT 24
Finished Aug 18 05:52:49 PM PDT 24
Peak memory 211368 kb
Host smart-a2451a17-9232-4c40-82e6-7b64422950ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218734623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2218734623
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2754776338
Short name T445
Test name
Test status
Simulation time 150763497 ps
CPU time 6.85 seconds
Started Aug 18 05:52:42 PM PDT 24
Finished Aug 18 05:52:49 PM PDT 24
Peak memory 219664 kb
Host smart-ba956cd8-5c15-4317-ab3d-f17298c327f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754776338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2754776338
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3482396901
Short name T441
Test name
Test status
Simulation time 2497127200 ps
CPU time 35.91 seconds
Started Aug 18 05:52:46 PM PDT 24
Finished Aug 18 05:53:22 PM PDT 24
Peak memory 211732 kb
Host smart-324e3a04-7898-4ea9-a905-4f3cb8544ff7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482396901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3482396901
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.386018825
Short name T422
Test name
Test status
Simulation time 591630014 ps
CPU time 5.09 seconds
Started Aug 18 05:52:40 PM PDT 24
Finished Aug 18 05:52:45 PM PDT 24
Peak memory 216256 kb
Host smart-37b6a8c9-e5f8-41ee-93aa-da6f80a54743
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386018825 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.386018825
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.676413702
Short name T364
Test name
Test status
Simulation time 88093116 ps
CPU time 4.09 seconds
Started Aug 18 05:52:46 PM PDT 24
Finished Aug 18 05:52:50 PM PDT 24
Peak memory 211424 kb
Host smart-1592bf03-e62c-423d-b3f3-28ea44533396
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676413702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.676413702
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1718467349
Short name T432
Test name
Test status
Simulation time 822874659 ps
CPU time 31.76 seconds
Started Aug 18 05:52:44 PM PDT 24
Finished Aug 18 05:53:16 PM PDT 24
Peak memory 211432 kb
Host smart-c6be6748-fba0-4cf3-9ab5-cc529624c0f8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718467349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1718467349
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2239166511
Short name T440
Test name
Test status
Simulation time 174635337 ps
CPU time 4.22 seconds
Started Aug 18 05:52:45 PM PDT 24
Finished Aug 18 05:52:49 PM PDT 24
Peak memory 211408 kb
Host smart-70ba75cf-edd1-4b78-a226-a10e7f62007f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239166511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2239166511
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3389692353
Short name T359
Test name
Test status
Simulation time 148320620 ps
CPU time 9.22 seconds
Started Aug 18 05:52:42 PM PDT 24
Finished Aug 18 05:52:51 PM PDT 24
Peak memory 219584 kb
Host smart-8d50375d-a529-4eda-8df1-a82c1f88df54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389692353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3389692353
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1619224224
Short name T385
Test name
Test status
Simulation time 219169554 ps
CPU time 37.04 seconds
Started Aug 18 05:52:45 PM PDT 24
Finished Aug 18 05:53:22 PM PDT 24
Peak memory 219592 kb
Host smart-b8bec23d-4104-4001-8fd6-6e6ed2c477e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619224224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1619224224
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1234780554
Short name T303
Test name
Test status
Simulation time 260976919 ps
CPU time 4.9 seconds
Started Aug 18 05:51:38 PM PDT 24
Finished Aug 18 05:51:43 PM PDT 24
Peak memory 211056 kb
Host smart-ce061b08-3766-468e-a2fd-afc31a76fe8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234780554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1234780554
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1276640821
Short name T16
Test name
Test status
Simulation time 2894552924 ps
CPU time 90.44 seconds
Started Aug 18 05:51:42 PM PDT 24
Finished Aug 18 05:53:13 PM PDT 24
Peak memory 212336 kb
Host smart-72a960fd-ba36-42d2-aadf-65b41f10e3eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276640821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1276640821
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.777539895
Short name T179
Test name
Test status
Simulation time 276124255 ps
CPU time 5.89 seconds
Started Aug 18 05:51:38 PM PDT 24
Finished Aug 18 05:51:44 PM PDT 24
Peak memory 211112 kb
Host smart-7f51c772-ddb3-4def-9e5f-14d388676c7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=777539895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.777539895
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2762458280
Short name T332
Test name
Test status
Simulation time 98967653 ps
CPU time 5.52 seconds
Started Aug 18 05:51:34 PM PDT 24
Finished Aug 18 05:51:40 PM PDT 24
Peak memory 212112 kb
Host smart-fe52469b-20aa-466d-8f5a-4cb6fb5279b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762458280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2762458280
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1784751688
Short name T235
Test name
Test status
Simulation time 199866700 ps
CPU time 13.33 seconds
Started Aug 18 05:51:37 PM PDT 24
Finished Aug 18 05:51:50 PM PDT 24
Peak memory 214324 kb
Host smart-cb315289-5c5e-4c5d-9dfb-d8a8a4920f15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784751688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1784751688
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3053329093
Short name T293
Test name
Test status
Simulation time 1340770687 ps
CPU time 21.47 seconds
Started Aug 18 05:51:38 PM PDT 24
Finished Aug 18 05:52:00 PM PDT 24
Peak memory 218660 kb
Host smart-a70c460a-aeac-4ac5-b1b8-8b93e711125c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053329093 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3053329093
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.438738322
Short name T266
Test name
Test status
Simulation time 174972293 ps
CPU time 4.76 seconds
Started Aug 18 05:51:37 PM PDT 24
Finished Aug 18 05:51:42 PM PDT 24
Peak memory 211064 kb
Host smart-2a1ac78c-3054-40c0-bbf2-eb7c6a184109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438738322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.438738322
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3094965510
Short name T201
Test name
Test status
Simulation time 3627077885 ps
CPU time 50.61 seconds
Started Aug 18 05:51:37 PM PDT 24
Finished Aug 18 05:52:28 PM PDT 24
Peak memory 227608 kb
Host smart-ea841601-43e5-4fb1-849c-c66101021442
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094965510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3094965510
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.508855809
Short name T133
Test name
Test status
Simulation time 178754449 ps
CPU time 8.92 seconds
Started Aug 18 05:51:42 PM PDT 24
Finished Aug 18 05:51:51 PM PDT 24
Peak memory 211580 kb
Host smart-fa893a17-c93e-465a-b0d0-611fcb38405c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508855809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.508855809
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.4255326142
Short name T19
Test name
Test status
Simulation time 220465083 ps
CPU time 52.82 seconds
Started Aug 18 05:51:44 PM PDT 24
Finished Aug 18 05:52:37 PM PDT 24
Peak memory 236068 kb
Host smart-5ac8adea-dfe8-453b-a87e-99c568e93480
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255326142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.4255326142
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2617179114
Short name T101
Test name
Test status
Simulation time 869308965 ps
CPU time 16.71 seconds
Started Aug 18 05:51:49 PM PDT 24
Finished Aug 18 05:52:06 PM PDT 24
Peak memory 214160 kb
Host smart-b8703d38-9c98-446c-a54b-9ab988994155
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617179114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2617179114
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.242665837
Short name T230
Test name
Test status
Simulation time 515527213 ps
CPU time 6.7 seconds
Started Aug 18 05:51:53 PM PDT 24
Finished Aug 18 05:52:00 PM PDT 24
Peak memory 211020 kb
Host smart-6e47bbd6-3e41-47bf-9611-8f5976497dc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242665837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.242665837
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1438895847
Short name T3
Test name
Test status
Simulation time 8964290036 ps
CPU time 103.71 seconds
Started Aug 18 05:51:48 PM PDT 24
Finished Aug 18 05:53:31 PM PDT 24
Peak memory 228408 kb
Host smart-cb012d3f-7989-442a-8c0d-d4acd1f48a9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438895847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1438895847
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3305194968
Short name T220
Test name
Test status
Simulation time 508033610 ps
CPU time 10.49 seconds
Started Aug 18 05:51:51 PM PDT 24
Finished Aug 18 05:52:01 PM PDT 24
Peak memory 211396 kb
Host smart-6695bd5f-2ed6-423e-8124-73aa2f857180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305194968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3305194968
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2951405583
Short name T129
Test name
Test status
Simulation time 4538616831 ps
CPU time 7.97 seconds
Started Aug 18 05:51:54 PM PDT 24
Finished Aug 18 05:52:02 PM PDT 24
Peak memory 211144 kb
Host smart-697b6f18-cfba-499f-87ad-c042e9c19e9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2951405583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2951405583
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.564644998
Short name T161
Test name
Test status
Simulation time 1129414094 ps
CPU time 25.68 seconds
Started Aug 18 05:51:43 PM PDT 24
Finished Aug 18 05:52:09 PM PDT 24
Peak memory 215640 kb
Host smart-67b34dff-fb9b-4293-8c34-0c8099d1a1e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564644998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.564644998
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3056186376
Short name T127
Test name
Test status
Simulation time 1350726529 ps
CPU time 50.34 seconds
Started Aug 18 05:51:46 PM PDT 24
Finished Aug 18 05:52:36 PM PDT 24
Peak memory 221488 kb
Host smart-730c26ac-3222-46b6-9082-1f0243df8799
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056186376 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3056186376
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1588482072
Short name T274
Test name
Test status
Simulation time 322802297 ps
CPU time 3.96 seconds
Started Aug 18 05:52:03 PM PDT 24
Finished Aug 18 05:52:07 PM PDT 24
Peak memory 210956 kb
Host smart-afe2d373-5b69-4bdd-afd4-c98a42379c4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588482072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1588482072
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2178761455
Short name T196
Test name
Test status
Simulation time 2954013623 ps
CPU time 133.52 seconds
Started Aug 18 05:51:51 PM PDT 24
Finished Aug 18 05:54:05 PM PDT 24
Peak memory 212492 kb
Host smart-c34de58d-11c5-4b93-8ee0-8348d4cab4f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178761455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2178761455
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2855578832
Short name T298
Test name
Test status
Simulation time 3110448860 ps
CPU time 10.84 seconds
Started Aug 18 05:52:01 PM PDT 24
Finished Aug 18 05:52:12 PM PDT 24
Peak memory 211456 kb
Host smart-6db623ad-e1a0-40a4-8ca3-824d3d7b1622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855578832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2855578832
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1271173478
Short name T228
Test name
Test status
Simulation time 168680082 ps
CPU time 5.27 seconds
Started Aug 18 05:51:47 PM PDT 24
Finished Aug 18 05:51:52 PM PDT 24
Peak memory 211060 kb
Host smart-f7464eca-dc24-43f0-bfd7-6ada836a588c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271173478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1271173478
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.4041266628
Short name T270
Test name
Test status
Simulation time 564094051 ps
CPU time 12.63 seconds
Started Aug 18 05:51:51 PM PDT 24
Finished Aug 18 05:52:04 PM PDT 24
Peak memory 214616 kb
Host smart-92395620-f523-4cad-a809-c2d7e6aa78de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041266628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.4041266628
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3617714980
Short name T309
Test name
Test status
Simulation time 87191895 ps
CPU time 4.12 seconds
Started Aug 18 05:51:58 PM PDT 24
Finished Aug 18 05:52:02 PM PDT 24
Peak memory 211064 kb
Host smart-042494f1-f47d-41a7-ade6-c00cbe576b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617714980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3617714980
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3151031300
Short name T216
Test name
Test status
Simulation time 3174103736 ps
CPU time 74.36 seconds
Started Aug 18 05:51:50 PM PDT 24
Finished Aug 18 05:53:05 PM PDT 24
Peak memory 224740 kb
Host smart-6cf5704f-19f1-4ae8-b119-5d3aa46e9d87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151031300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3151031300
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1120492740
Short name T317
Test name
Test status
Simulation time 355310752 ps
CPU time 9.01 seconds
Started Aug 18 05:51:50 PM PDT 24
Finished Aug 18 05:51:59 PM PDT 24
Peak memory 211420 kb
Host smart-cb181c6a-5f31-42be-afbd-17e984b02bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120492740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1120492740
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3587174294
Short name T288
Test name
Test status
Simulation time 188693774 ps
CPU time 5.1 seconds
Started Aug 18 05:51:56 PM PDT 24
Finished Aug 18 05:52:01 PM PDT 24
Peak memory 211080 kb
Host smart-f139a587-c5ea-4a47-ba80-ccabaa3945f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3587174294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3587174294
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2313945084
Short name T102
Test name
Test status
Simulation time 578722704 ps
CPU time 17.22 seconds
Started Aug 18 05:51:52 PM PDT 24
Finished Aug 18 05:52:09 PM PDT 24
Peak memory 212332 kb
Host smart-2f218abd-545c-43ce-9963-ef66c67715fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313945084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2313945084
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1778921446
Short name T331
Test name
Test status
Simulation time 6301237240 ps
CPU time 57.91 seconds
Started Aug 18 05:51:57 PM PDT 24
Finished Aug 18 05:52:55 PM PDT 24
Peak memory 220556 kb
Host smart-ba90b853-e5a7-40f1-8f49-d75e0ef5bb19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778921446 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.1778921446
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3727216052
Short name T123
Test name
Test status
Simulation time 133835628 ps
CPU time 4.74 seconds
Started Aug 18 05:51:49 PM PDT 24
Finished Aug 18 05:51:54 PM PDT 24
Peak memory 211076 kb
Host smart-0af731d2-14ba-4b4b-b44e-fd4c6e96393f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727216052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3727216052
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3024769547
Short name T227
Test name
Test status
Simulation time 1253007621 ps
CPU time 78.23 seconds
Started Aug 18 05:51:59 PM PDT 24
Finished Aug 18 05:53:17 PM PDT 24
Peak memory 232512 kb
Host smart-2a6cb457-314e-4d64-a2d1-61de798105e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024769547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3024769547
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3012536553
Short name T321
Test name
Test status
Simulation time 252685381 ps
CPU time 10.37 seconds
Started Aug 18 05:52:04 PM PDT 24
Finished Aug 18 05:52:14 PM PDT 24
Peak memory 211452 kb
Host smart-148d4734-e7d7-4288-99e9-99d1133a7f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012536553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3012536553
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3923388765
Short name T286
Test name
Test status
Simulation time 97985214 ps
CPU time 5.57 seconds
Started Aug 18 05:51:50 PM PDT 24
Finished Aug 18 05:51:56 PM PDT 24
Peak memory 211076 kb
Host smart-4aec6aa9-e3ce-47d6-bbaf-5faeefa69cbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3923388765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3923388765
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1452171865
Short name T231
Test name
Test status
Simulation time 4334816380 ps
CPU time 19.25 seconds
Started Aug 18 05:51:55 PM PDT 24
Finished Aug 18 05:52:15 PM PDT 24
Peak memory 214252 kb
Host smart-164fcac5-89ed-414c-95b0-8f1cc1579fb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452171865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1452171865
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1785895022
Short name T120
Test name
Test status
Simulation time 3011495891 ps
CPU time 98.24 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:53:38 PM PDT 24
Peak memory 219724 kb
Host smart-ff00eb88-cfbb-4062-ab7f-d3664ecd00eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785895022 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1785895022
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2051274508
Short name T319
Test name
Test status
Simulation time 271958019 ps
CPU time 4.86 seconds
Started Aug 18 05:51:50 PM PDT 24
Finished Aug 18 05:51:56 PM PDT 24
Peak memory 211092 kb
Host smart-6d12eee1-2fa3-47b3-9c97-3b77f5ad1ea8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051274508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2051274508
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1050053516
Short name T324
Test name
Test status
Simulation time 3157823249 ps
CPU time 157.86 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:54:38 PM PDT 24
Peak memory 237032 kb
Host smart-9d81a51a-b3ce-47c0-9f38-82cf105bbd57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050053516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1050053516
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2326334123
Short name T304
Test name
Test status
Simulation time 510814076 ps
CPU time 10.58 seconds
Started Aug 18 05:51:52 PM PDT 24
Finished Aug 18 05:52:02 PM PDT 24
Peak memory 211096 kb
Host smart-c57b55bc-b2ba-4570-afbc-04684902771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326334123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2326334123
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3106168801
Short name T349
Test name
Test status
Simulation time 193998383 ps
CPU time 5.36 seconds
Started Aug 18 05:52:03 PM PDT 24
Finished Aug 18 05:52:09 PM PDT 24
Peak memory 211044 kb
Host smart-858bca43-e925-47d6-acdc-8f7324263acc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3106168801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3106168801
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2358302896
Short name T73
Test name
Test status
Simulation time 1149603539 ps
CPU time 13.36 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:52:16 PM PDT 24
Peak memory 214220 kb
Host smart-c0c80ac2-5220-4300-86c0-6d22bda2d400
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358302896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2358302896
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.4148292903
Short name T49
Test name
Test status
Simulation time 3403021308 ps
CPU time 190.31 seconds
Started Aug 18 05:52:03 PM PDT 24
Finished Aug 18 05:55:13 PM PDT 24
Peak memory 222424 kb
Host smart-25cc2609-e9b8-437f-ae9f-674228cbec7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148292903 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.4148292903
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2775801517
Short name T20
Test name
Test status
Simulation time 184050653 ps
CPU time 4.15 seconds
Started Aug 18 05:51:57 PM PDT 24
Finished Aug 18 05:52:01 PM PDT 24
Peak memory 210988 kb
Host smart-a4d18740-3eeb-4255-9174-1cf232ffb63b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775801517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2775801517
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.602976570
Short name T6
Test name
Test status
Simulation time 2102725170 ps
CPU time 58.35 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:53:00 PM PDT 24
Peak memory 227772 kb
Host smart-2f383e29-59e4-4444-a1ae-8862ae26731c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602976570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.602976570
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.685279345
Short name T223
Test name
Test status
Simulation time 261147187 ps
CPU time 10.54 seconds
Started Aug 18 05:52:03 PM PDT 24
Finished Aug 18 05:52:14 PM PDT 24
Peak memory 211068 kb
Host smart-1444ce03-a025-448f-bc71-94ea9cbb0ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685279345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.685279345
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1702368223
Short name T326
Test name
Test status
Simulation time 393318680 ps
CPU time 5.6 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:52:06 PM PDT 24
Peak memory 211080 kb
Host smart-67a6dd17-6a53-4e1a-9318-38c2a990ece0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1702368223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1702368223
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3418231147
Short name T251
Test name
Test status
Simulation time 1037766454 ps
CPU time 12.35 seconds
Started Aug 18 05:51:51 PM PDT 24
Finished Aug 18 05:52:04 PM PDT 24
Peak memory 214544 kb
Host smart-5a905597-746f-4afd-a7ea-e40a26761696
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418231147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3418231147
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1010762651
Short name T208
Test name
Test status
Simulation time 8967442219 ps
CPU time 83.29 seconds
Started Aug 18 05:51:59 PM PDT 24
Finished Aug 18 05:53:23 PM PDT 24
Peak memory 221480 kb
Host smart-0497a50b-6c93-452c-9901-d777df52e751
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010762651 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1010762651
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2096105145
Short name T104
Test name
Test status
Simulation time 594206524 ps
CPU time 4.12 seconds
Started Aug 18 05:51:55 PM PDT 24
Finished Aug 18 05:51:59 PM PDT 24
Peak memory 211060 kb
Host smart-2522dfdd-f3ca-46e8-9c12-1c82fa677a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096105145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2096105145
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2343576308
Short name T305
Test name
Test status
Simulation time 10621940543 ps
CPU time 131.62 seconds
Started Aug 18 05:51:57 PM PDT 24
Finished Aug 18 05:54:09 PM PDT 24
Peak memory 213508 kb
Host smart-f7b281b1-8777-411f-951e-d3835ad4e771
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343576308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2343576308
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3989442311
Short name T280
Test name
Test status
Simulation time 666324911 ps
CPU time 9.16 seconds
Started Aug 18 05:51:58 PM PDT 24
Finished Aug 18 05:52:07 PM PDT 24
Peak memory 211588 kb
Host smart-3b04d9d8-ee72-414e-a403-c2162433d6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989442311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3989442311
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1984275998
Short name T130
Test name
Test status
Simulation time 134248788 ps
CPU time 6.17 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:52:08 PM PDT 24
Peak memory 212280 kb
Host smart-48eb22a8-cf3f-446f-84e1-3026566f3563
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984275998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1984275998
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1383700036
Short name T118
Test name
Test status
Simulation time 7145546074 ps
CPU time 211.38 seconds
Started Aug 18 05:51:59 PM PDT 24
Finished Aug 18 05:55:30 PM PDT 24
Peak memory 227580 kb
Host smart-feb878e6-febd-4ae6-93f6-f1ff5b59757a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383700036 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1383700036
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3231094956
Short name T314
Test name
Test status
Simulation time 86412138 ps
CPU time 4.2 seconds
Started Aug 18 05:51:55 PM PDT 24
Finished Aug 18 05:51:59 PM PDT 24
Peak memory 211060 kb
Host smart-6de2a78c-6eca-4540-9aa8-0635b9a2edeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231094956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3231094956
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3784450677
Short name T313
Test name
Test status
Simulation time 12825969576 ps
CPU time 212.51 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:55:35 PM PDT 24
Peak memory 211700 kb
Host smart-2c56b6df-00aa-4f2f-9744-91490f4a7c7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784450677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3784450677
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.212626534
Short name T289
Test name
Test status
Simulation time 170800994 ps
CPU time 9.55 seconds
Started Aug 18 05:51:52 PM PDT 24
Finished Aug 18 05:52:02 PM PDT 24
Peak memory 211612 kb
Host smart-6a6ba8cb-7cff-432c-9407-bf06f535ebc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212626534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.212626534
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.645085197
Short name T2
Test name
Test status
Simulation time 542270974 ps
CPU time 6.45 seconds
Started Aug 18 05:51:57 PM PDT 24
Finished Aug 18 05:52:03 PM PDT 24
Peak memory 211108 kb
Host smart-62ea818b-3a5f-418f-9f40-49f30f7ff95a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645085197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.645085197
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1867619342
Short name T69
Test name
Test status
Simulation time 598624075 ps
CPU time 12.88 seconds
Started Aug 18 05:51:57 PM PDT 24
Finished Aug 18 05:52:10 PM PDT 24
Peak memory 213804 kb
Host smart-fa083980-739e-4fed-b443-f5b456ababa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867619342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1867619342
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.348485831
Short name T89
Test name
Test status
Simulation time 6232027672 ps
CPU time 63.17 seconds
Started Aug 18 05:51:53 PM PDT 24
Finished Aug 18 05:52:57 PM PDT 24
Peak memory 221316 kb
Host smart-397fb854-a02d-4826-80f4-51157c36465b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348485831 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.348485831
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1369897959
Short name T158
Test name
Test status
Simulation time 1039232713 ps
CPU time 4.1 seconds
Started Aug 18 05:52:03 PM PDT 24
Finished Aug 18 05:52:08 PM PDT 24
Peak memory 211052 kb
Host smart-477860fa-7b57-41ca-af2d-c1014e46d800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369897959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1369897959
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.675986074
Short name T36
Test name
Test status
Simulation time 2161791456 ps
CPU time 102.47 seconds
Started Aug 18 05:51:55 PM PDT 24
Finished Aug 18 05:53:38 PM PDT 24
Peak memory 237644 kb
Host smart-bf4936f9-ccce-4325-84c0-04d8c49db753
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675986074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.675986074
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3006314025
Short name T148
Test name
Test status
Simulation time 512160772 ps
CPU time 10.48 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:52:12 PM PDT 24
Peak memory 211408 kb
Host smart-1983f37a-415a-4dd3-907c-c8ea7233f9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006314025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3006314025
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3387270554
Short name T340
Test name
Test status
Simulation time 362065506 ps
CPU time 5.11 seconds
Started Aug 18 05:51:58 PM PDT 24
Finished Aug 18 05:52:03 PM PDT 24
Peak memory 211080 kb
Host smart-82da0299-b9c0-4fdb-b072-0fea820da07e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387270554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3387270554
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.380323694
Short name T183
Test name
Test status
Simulation time 652781513 ps
CPU time 5.38 seconds
Started Aug 18 05:51:53 PM PDT 24
Finished Aug 18 05:51:59 PM PDT 24
Peak memory 211080 kb
Host smart-b2a86944-af62-403c-97e9-7b7b80ecbc04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380323694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.380323694
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2711155568
Short name T334
Test name
Test status
Simulation time 10753484124 ps
CPU time 100.26 seconds
Started Aug 18 05:52:03 PM PDT 24
Finished Aug 18 05:53:43 PM PDT 24
Peak memory 231744 kb
Host smart-d19fd0e1-74dd-432f-8490-e81912a2906e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711155568 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2711155568
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1913730924
Short name T254
Test name
Test status
Simulation time 336405570 ps
CPU time 4.07 seconds
Started Aug 18 05:51:58 PM PDT 24
Finished Aug 18 05:52:02 PM PDT 24
Peak memory 211076 kb
Host smart-e168cd5b-5387-4baf-be59-afe5b47af878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913730924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1913730924
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1869317534
Short name T26
Test name
Test status
Simulation time 4208534224 ps
CPU time 70.67 seconds
Started Aug 18 05:51:57 PM PDT 24
Finished Aug 18 05:53:07 PM PDT 24
Peak memory 228348 kb
Host smart-1b4d74e5-ee87-49f1-a717-f985026f308c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869317534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1869317534
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2305351857
Short name T278
Test name
Test status
Simulation time 697402587 ps
CPU time 9.16 seconds
Started Aug 18 05:52:03 PM PDT 24
Finished Aug 18 05:52:12 PM PDT 24
Peak memory 211488 kb
Host smart-497aca0c-9c07-4ff9-8066-10040d4a148b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305351857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2305351857
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3922293877
Short name T310
Test name
Test status
Simulation time 383458947 ps
CPU time 5.18 seconds
Started Aug 18 05:51:58 PM PDT 24
Finished Aug 18 05:52:03 PM PDT 24
Peak memory 211056 kb
Host smart-cdc3a05a-2a02-46a0-a2a3-e5076180e30c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922293877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3922293877
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3989338514
Short name T176
Test name
Test status
Simulation time 279710716 ps
CPU time 12.7 seconds
Started Aug 18 05:51:53 PM PDT 24
Finished Aug 18 05:52:06 PM PDT 24
Peak memory 213664 kb
Host smart-b1e6da85-1782-47f2-9d5f-d3bd4318a67d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989338514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3989338514
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.72911907
Short name T343
Test name
Test status
Simulation time 2486369992 ps
CPU time 4.88 seconds
Started Aug 18 05:51:43 PM PDT 24
Finished Aug 18 05:51:48 PM PDT 24
Peak memory 211148 kb
Host smart-512912b2-92a6-457b-bc3f-4e091415556d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72911907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.72911907
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3853127448
Short name T37
Test name
Test status
Simulation time 14984220229 ps
CPU time 136.1 seconds
Started Aug 18 05:51:39 PM PDT 24
Finished Aug 18 05:53:55 PM PDT 24
Peak memory 237628 kb
Host smart-bd65541f-16b4-44ce-8ee4-a8c6cd964fcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853127448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3853127448
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2368422663
Short name T236
Test name
Test status
Simulation time 1189910649 ps
CPU time 10.57 seconds
Started Aug 18 05:51:36 PM PDT 24
Finished Aug 18 05:51:47 PM PDT 24
Peak memory 211588 kb
Host smart-56c5371c-9848-417a-af21-c41a79e73e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368422663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2368422663
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2726889751
Short name T187
Test name
Test status
Simulation time 265675546 ps
CPU time 6.23 seconds
Started Aug 18 05:51:37 PM PDT 24
Finished Aug 18 05:51:44 PM PDT 24
Peak memory 211016 kb
Host smart-c0c8cb0b-21b2-4991-8fc8-38fe1b7344d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726889751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2726889751
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2100620664
Short name T18
Test name
Test status
Simulation time 323976271 ps
CPU time 100.26 seconds
Started Aug 18 05:51:42 PM PDT 24
Finished Aug 18 05:53:23 PM PDT 24
Peak memory 236660 kb
Host smart-926df40e-9f6a-4c50-a9d9-0213baca702d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100620664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2100620664
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2272526618
Short name T105
Test name
Test status
Simulation time 537574376 ps
CPU time 6.06 seconds
Started Aug 18 05:51:38 PM PDT 24
Finished Aug 18 05:51:45 PM PDT 24
Peak memory 211908 kb
Host smart-3f6c699c-c157-4945-9ce3-5461bb84b552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272526618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2272526618
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1696316008
Short name T149
Test name
Test status
Simulation time 145344524 ps
CPU time 9.04 seconds
Started Aug 18 05:51:40 PM PDT 24
Finished Aug 18 05:51:49 PM PDT 24
Peak memory 211220 kb
Host smart-69be7600-544b-46bb-ac36-c9c77efa6fca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696316008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1696316008
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4067042470
Short name T154
Test name
Test status
Simulation time 9823020321 ps
CPU time 196.15 seconds
Started Aug 18 05:51:38 PM PDT 24
Finished Aug 18 05:54:54 PM PDT 24
Peak memory 227840 kb
Host smart-83b93194-f2d1-498e-9184-34971cc88332
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067042470 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.4067042470
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2160298386
Short name T318
Test name
Test status
Simulation time 85776804 ps
CPU time 3.97 seconds
Started Aug 18 05:51:56 PM PDT 24
Finished Aug 18 05:52:00 PM PDT 24
Peak memory 211044 kb
Host smart-7cae41de-2971-4a0f-bd41-0519015c43f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160298386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2160298386
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4179865577
Short name T238
Test name
Test status
Simulation time 4280402526 ps
CPU time 113.46 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:53:54 PM PDT 24
Peak memory 212388 kb
Host smart-3516b29a-aa6d-4ff6-81d6-f9f8082bf36e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179865577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4179865577
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3563170953
Short name T22
Test name
Test status
Simulation time 169001556 ps
CPU time 9.05 seconds
Started Aug 18 05:51:52 PM PDT 24
Finished Aug 18 05:52:01 PM PDT 24
Peak memory 211476 kb
Host smart-43eb80a9-f9f8-43f9-8bca-839f2184e019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563170953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3563170953
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1137589243
Short name T15
Test name
Test status
Simulation time 525586021 ps
CPU time 8.31 seconds
Started Aug 18 05:51:58 PM PDT 24
Finished Aug 18 05:52:06 PM PDT 24
Peak memory 211080 kb
Host smart-a26d5754-f896-45fa-b32e-515ec7ba6fb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1137589243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1137589243
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3960991668
Short name T95
Test name
Test status
Simulation time 548642994 ps
CPU time 12.12 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:52:12 PM PDT 24
Peak memory 211428 kb
Host smart-be805dde-a803-4d86-99ed-466f71a5de70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960991668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3960991668
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3144376955
Short name T172
Test name
Test status
Simulation time 15230029308 ps
CPU time 149.89 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:54:32 PM PDT 24
Peak memory 224768 kb
Host smart-9981424b-71a1-4e93-a0e7-65f45a661f78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144376955 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3144376955
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2082680733
Short name T93
Test name
Test status
Simulation time 321758388 ps
CPU time 4.24 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:52:04 PM PDT 24
Peak memory 211016 kb
Host smart-82a9e2e2-f816-4045-be4d-bb8d75d5afe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082680733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2082680733
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2404784440
Short name T247
Test name
Test status
Simulation time 3949685333 ps
CPU time 106.9 seconds
Started Aug 18 05:52:03 PM PDT 24
Finished Aug 18 05:53:50 PM PDT 24
Peak memory 228108 kb
Host smart-c70076d1-7f4e-44d5-a267-f9e700692e01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404784440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2404784440
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.841872365
Short name T94
Test name
Test status
Simulation time 3171522087 ps
CPU time 14.64 seconds
Started Aug 18 05:52:05 PM PDT 24
Finished Aug 18 05:52:20 PM PDT 24
Peak memory 211176 kb
Host smart-16933a40-afd3-4b0b-b608-29bc9ee0b5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841872365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.841872365
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4073939660
Short name T335
Test name
Test status
Simulation time 348715180 ps
CPU time 5.11 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:52:05 PM PDT 24
Peak memory 211100 kb
Host smart-b16082ce-d6be-492b-8b7e-d397b8acfd53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073939660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4073939660
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.878774356
Short name T240
Test name
Test status
Simulation time 2370856701 ps
CPU time 13.05 seconds
Started Aug 18 05:51:57 PM PDT 24
Finished Aug 18 05:52:10 PM PDT 24
Peak memory 213644 kb
Host smart-cc73bfa1-7ea2-4e53-9685-1c3eb585d10f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878774356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.878774356
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4119491599
Short name T134
Test name
Test status
Simulation time 42411290361 ps
CPU time 129.47 seconds
Started Aug 18 05:52:10 PM PDT 24
Finished Aug 18 05:54:20 PM PDT 24
Peak memory 235552 kb
Host smart-8c3cb5a0-f3ac-4b71-b4c5-8441a29c7ce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119491599 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.4119491599
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.645562162
Short name T239
Test name
Test status
Simulation time 349502609 ps
CPU time 4.01 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:52:06 PM PDT 24
Peak memory 211076 kb
Host smart-7f907bc8-db4e-44ee-9c2a-4fa3bafa296e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645562162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.645562162
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.479020835
Short name T155
Test name
Test status
Simulation time 1222640159 ps
CPU time 75.89 seconds
Started Aug 18 05:51:59 PM PDT 24
Finished Aug 18 05:53:15 PM PDT 24
Peak memory 236504 kb
Host smart-855453c5-8884-446b-9f5d-bc09ebda7283
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479020835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.479020835
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2386140962
Short name T296
Test name
Test status
Simulation time 251273457 ps
CPU time 10.76 seconds
Started Aug 18 05:52:07 PM PDT 24
Finished Aug 18 05:52:17 PM PDT 24
Peak memory 211100 kb
Host smart-889a2e7e-6a5c-4628-972b-7efc0e9c4708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386140962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2386140962
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.729961959
Short name T225
Test name
Test status
Simulation time 985190032 ps
CPU time 7.69 seconds
Started Aug 18 05:52:01 PM PDT 24
Finished Aug 18 05:52:09 PM PDT 24
Peak memory 211092 kb
Host smart-3a58500a-b777-4759-96d1-0fe1dd81bfdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=729961959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.729961959
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2981357175
Short name T217
Test name
Test status
Simulation time 288408395 ps
CPU time 16.11 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:52:16 PM PDT 24
Peak memory 212992 kb
Host smart-3aa995a8-0d1d-488a-80b5-ee908b756895
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981357175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2981357175
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2045197971
Short name T294
Test name
Test status
Simulation time 9542401345 ps
CPU time 143.29 seconds
Started Aug 18 05:51:58 PM PDT 24
Finished Aug 18 05:54:21 PM PDT 24
Peak memory 221512 kb
Host smart-b6da25fd-3667-488a-acfb-eabbc74c9460
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045197971 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2045197971
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.652877470
Short name T322
Test name
Test status
Simulation time 261822116 ps
CPU time 4.83 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:52:07 PM PDT 24
Peak memory 211008 kb
Host smart-db9b8cd6-85d1-49c2-9047-b23e0226cdcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652877470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.652877470
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2676106106
Short name T174
Test name
Test status
Simulation time 6563072806 ps
CPU time 56.9 seconds
Started Aug 18 05:51:59 PM PDT 24
Finished Aug 18 05:52:56 PM PDT 24
Peak memory 236540 kb
Host smart-6067ae07-0b61-40e2-ae12-58a0e262ab9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676106106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2676106106
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2694916783
Short name T281
Test name
Test status
Simulation time 519854539 ps
CPU time 10.68 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:52:11 PM PDT 24
Peak memory 211428 kb
Host smart-db23e9bc-fa78-41aa-a086-01f126886ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694916783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2694916783
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1526453081
Short name T164
Test name
Test status
Simulation time 136326171 ps
CPU time 5.82 seconds
Started Aug 18 05:52:04 PM PDT 24
Finished Aug 18 05:52:10 PM PDT 24
Peak memory 211076 kb
Host smart-6d18b370-8da0-4cbf-b275-69fd2f8190d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1526453081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1526453081
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4202480855
Short name T121
Test name
Test status
Simulation time 100901059 ps
CPU time 8.03 seconds
Started Aug 18 05:52:01 PM PDT 24
Finished Aug 18 05:52:09 PM PDT 24
Peak memory 210932 kb
Host smart-b501ee7c-1321-4b92-a1c1-8eca537d0b69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202480855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4202480855
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1560213436
Short name T246
Test name
Test status
Simulation time 133932726 ps
CPU time 4.92 seconds
Started Aug 18 05:52:08 PM PDT 24
Finished Aug 18 05:52:13 PM PDT 24
Peak memory 211060 kb
Host smart-7ce17f69-9b67-4508-9009-a000790761ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560213436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1560213436
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2274791315
Short name T339
Test name
Test status
Simulation time 10083191155 ps
CPU time 128.37 seconds
Started Aug 18 05:52:10 PM PDT 24
Finished Aug 18 05:54:19 PM PDT 24
Peak memory 233476 kb
Host smart-3c79817e-81a0-44e4-82c2-aa8948f50e13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274791315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2274791315
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2099018566
Short name T41
Test name
Test status
Simulation time 347566233 ps
CPU time 8.98 seconds
Started Aug 18 05:52:06 PM PDT 24
Finished Aug 18 05:52:15 PM PDT 24
Peak memory 211472 kb
Host smart-c93a1538-28d3-47a5-882c-00ef7496ae78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099018566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2099018566
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3444684318
Short name T142
Test name
Test status
Simulation time 376538189 ps
CPU time 5.4 seconds
Started Aug 18 05:52:06 PM PDT 24
Finished Aug 18 05:52:11 PM PDT 24
Peak memory 211076 kb
Host smart-0f490871-dbcf-4fad-9191-0fa00c086e03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3444684318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3444684318
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.318519683
Short name T279
Test name
Test status
Simulation time 845648115 ps
CPU time 16.69 seconds
Started Aug 18 05:52:10 PM PDT 24
Finished Aug 18 05:52:27 PM PDT 24
Peak memory 216568 kb
Host smart-66789527-8321-4b09-b551-7cca6d2d5ce1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318519683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.318519683
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1663884278
Short name T267
Test name
Test status
Simulation time 5876195190 ps
CPU time 57.05 seconds
Started Aug 18 05:51:59 PM PDT 24
Finished Aug 18 05:52:57 PM PDT 24
Peak memory 221664 kb
Host smart-4aa741ff-a98a-4f2c-8bc1-3cdd9517bdf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663884278 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1663884278
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3743969375
Short name T182
Test name
Test status
Simulation time 346837267 ps
CPU time 4.14 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:52:05 PM PDT 24
Peak memory 211084 kb
Host smart-8564299f-6b1d-41a5-9195-f5dc7b2baba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743969375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3743969375
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1978035881
Short name T263
Test name
Test status
Simulation time 2659058822 ps
CPU time 70.8 seconds
Started Aug 18 05:52:03 PM PDT 24
Finished Aug 18 05:53:14 PM PDT 24
Peak memory 232568 kb
Host smart-d17d9f16-3bb8-4f01-b5fb-af08e57419fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978035881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1978035881
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3883116288
Short name T291
Test name
Test status
Simulation time 957652848 ps
CPU time 10.49 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:52:13 PM PDT 24
Peak memory 211044 kb
Host smart-8ed66c79-a0b2-44a1-a18f-36cdf5604532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883116288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3883116288
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1451489768
Short name T184
Test name
Test status
Simulation time 136369713 ps
CPU time 6 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:52:09 PM PDT 24
Peak memory 211080 kb
Host smart-450a5cae-5460-444e-b58d-9d076ea7fe73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1451489768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1451489768
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.568638415
Short name T185
Test name
Test status
Simulation time 1314818416 ps
CPU time 13.31 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:52:16 PM PDT 24
Peak memory 214340 kb
Host smart-24c459b0-3390-4685-ada9-5691255d5bb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568638415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.568638415
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1078576670
Short name T242
Test name
Test status
Simulation time 347009249 ps
CPU time 4.18 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:52:04 PM PDT 24
Peak memory 211012 kb
Host smart-1988a8f1-f058-4ac7-84bb-f2cbf7feedbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078576670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1078576670
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4029352237
Short name T45
Test name
Test status
Simulation time 10787294746 ps
CPU time 90.09 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:53:31 PM PDT 24
Peak memory 237584 kb
Host smart-c934011f-4b77-48c7-a32c-3d2dcfedb08a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029352237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4029352237
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1604639724
Short name T244
Test name
Test status
Simulation time 3940570574 ps
CPU time 14.48 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:52:17 PM PDT 24
Peak memory 211516 kb
Host smart-64efd991-6e47-4321-a035-e8cff5c407c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604639724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1604639724
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1171118271
Short name T125
Test name
Test status
Simulation time 554060378 ps
CPU time 5.87 seconds
Started Aug 18 05:52:01 PM PDT 24
Finished Aug 18 05:52:07 PM PDT 24
Peak memory 211080 kb
Host smart-138e4fe4-eb7b-443b-89ad-2f6776f328da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1171118271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1171118271
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3509349277
Short name T192
Test name
Test status
Simulation time 569216742 ps
CPU time 9.55 seconds
Started Aug 18 05:52:10 PM PDT 24
Finished Aug 18 05:52:20 PM PDT 24
Peak memory 211432 kb
Host smart-41facf00-aa15-4854-b092-8a14bc92d99f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509349277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3509349277
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1893121023
Short name T28
Test name
Test status
Simulation time 3857979367 ps
CPU time 159.49 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:54:42 PM PDT 24
Peak memory 231224 kb
Host smart-dc857829-c88b-41eb-98b1-3fa8c81fbb26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893121023 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1893121023
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.116918017
Short name T162
Test name
Test status
Simulation time 126721889 ps
CPU time 4.82 seconds
Started Aug 18 05:52:04 PM PDT 24
Finished Aug 18 05:52:09 PM PDT 24
Peak memory 211036 kb
Host smart-d2f33cca-69df-4171-9323-e318d0b34be0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116918017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.116918017
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2863560700
Short name T261
Test name
Test status
Simulation time 722364035 ps
CPU time 9.11 seconds
Started Aug 18 05:52:04 PM PDT 24
Finished Aug 18 05:52:13 PM PDT 24
Peak memory 211468 kb
Host smart-7e5d04ea-4ee2-4c46-9a44-bc08f22588f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863560700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2863560700
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.649125578
Short name T138
Test name
Test status
Simulation time 530488717 ps
CPU time 5.91 seconds
Started Aug 18 05:52:04 PM PDT 24
Finished Aug 18 05:52:10 PM PDT 24
Peak memory 211100 kb
Host smart-0a2888e8-6752-4c08-9a3a-4c42e8d60862
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649125578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.649125578
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2452574427
Short name T177
Test name
Test status
Simulation time 1076621255 ps
CPU time 7.82 seconds
Started Aug 18 05:52:04 PM PDT 24
Finished Aug 18 05:52:12 PM PDT 24
Peak memory 212500 kb
Host smart-e9b25433-8db9-4579-b501-cd5388a864ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452574427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2452574427
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2733017940
Short name T259
Test name
Test status
Simulation time 8884082589 ps
CPU time 308.53 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:57:09 PM PDT 24
Peak memory 222944 kb
Host smart-67984599-1703-4236-881f-cd09f8b72bef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733017940 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2733017940
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2620660086
Short name T342
Test name
Test status
Simulation time 519835485 ps
CPU time 4.92 seconds
Started Aug 18 05:52:14 PM PDT 24
Finished Aug 18 05:52:19 PM PDT 24
Peak memory 211088 kb
Host smart-df3beb11-bbc0-4747-a9b3-762c66194ba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620660086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2620660086
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3244912881
Short name T178
Test name
Test status
Simulation time 4498541158 ps
CPU time 107.09 seconds
Started Aug 18 05:52:10 PM PDT 24
Finished Aug 18 05:53:58 PM PDT 24
Peak memory 236620 kb
Host smart-ee515238-f606-47d1-8e1b-d61bf052e3ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244912881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3244912881
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3312685171
Short name T180
Test name
Test status
Simulation time 1474575371 ps
CPU time 10.41 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:52:11 PM PDT 24
Peak memory 211492 kb
Host smart-958f1565-988f-429b-b121-02ee5377ddb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312685171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3312685171
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1141257441
Short name T126
Test name
Test status
Simulation time 190090565 ps
CPU time 5.26 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:52:08 PM PDT 24
Peak memory 211060 kb
Host smart-a955e104-a71d-457f-8654-942bd4f16fc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1141257441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1141257441
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2614999452
Short name T345
Test name
Test status
Simulation time 809490507 ps
CPU time 14.61 seconds
Started Aug 18 05:52:06 PM PDT 24
Finished Aug 18 05:52:21 PM PDT 24
Peak memory 213380 kb
Host smart-a660b84d-b31b-4b23-89c0-5b3b82734bcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614999452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2614999452
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1356485939
Short name T275
Test name
Test status
Simulation time 5497867270 ps
CPU time 375.51 seconds
Started Aug 18 05:51:58 PM PDT 24
Finished Aug 18 05:58:13 PM PDT 24
Peak memory 223460 kb
Host smart-591be89e-398e-41b8-b122-9baea5f78a37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356485939 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1356485939
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3471637569
Short name T215
Test name
Test status
Simulation time 165643888 ps
CPU time 4.04 seconds
Started Aug 18 05:52:10 PM PDT 24
Finished Aug 18 05:52:14 PM PDT 24
Peak memory 211076 kb
Host smart-9ef9f5dd-1397-4a96-bc13-8bc60a418502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471637569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3471637569
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.506731995
Short name T42
Test name
Test status
Simulation time 8982947451 ps
CPU time 76.53 seconds
Started Aug 18 05:52:00 PM PDT 24
Finished Aug 18 05:53:17 PM PDT 24
Peak memory 236620 kb
Host smart-0d2908d4-d4aa-484c-a0da-46492cff84dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506731995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.506731995
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3741287679
Short name T256
Test name
Test status
Simulation time 169552683 ps
CPU time 9.07 seconds
Started Aug 18 05:52:04 PM PDT 24
Finished Aug 18 05:52:13 PM PDT 24
Peak memory 211592 kb
Host smart-ce5b73bf-1ace-4213-8b83-56a6d21c0464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741287679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3741287679
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3574191038
Short name T145
Test name
Test status
Simulation time 188775989 ps
CPU time 5.1 seconds
Started Aug 18 05:52:09 PM PDT 24
Finished Aug 18 05:52:14 PM PDT 24
Peak memory 211068 kb
Host smart-9f8e9372-49a7-4a3e-bf29-bc8fcf175ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3574191038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3574191038
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1231387705
Short name T302
Test name
Test status
Simulation time 550704861 ps
CPU time 19.15 seconds
Started Aug 18 05:52:10 PM PDT 24
Finished Aug 18 05:52:30 PM PDT 24
Peak memory 215484 kb
Host smart-30787926-009b-4a12-b119-47a115719580
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231387705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1231387705
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2791355804
Short name T348
Test name
Test status
Simulation time 7594415679 ps
CPU time 141.14 seconds
Started Aug 18 05:52:09 PM PDT 24
Finished Aug 18 05:54:31 PM PDT 24
Peak memory 223108 kb
Host smart-c7ba9c4d-5301-4179-b129-5949d947b5b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791355804 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2791355804
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1050343819
Short name T219
Test name
Test status
Simulation time 567175237 ps
CPU time 4.89 seconds
Started Aug 18 05:51:37 PM PDT 24
Finished Aug 18 05:51:42 PM PDT 24
Peak memory 211044 kb
Host smart-7b65ac28-9538-4694-bb28-3a8e27ce09d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050343819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1050343819
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3506723255
Short name T150
Test name
Test status
Simulation time 1716495255 ps
CPU time 66.27 seconds
Started Aug 18 05:51:37 PM PDT 24
Finished Aug 18 05:52:43 PM PDT 24
Peak memory 211688 kb
Host smart-4641c55d-bf12-453e-9e48-258bfd4893a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506723255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3506723255
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2979974481
Short name T191
Test name
Test status
Simulation time 696278925 ps
CPU time 8.92 seconds
Started Aug 18 05:51:36 PM PDT 24
Finished Aug 18 05:51:45 PM PDT 24
Peak memory 211492 kb
Host smart-2fa61468-6055-4a20-9740-5d5d2132931a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979974481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2979974481
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.654255476
Short name T292
Test name
Test status
Simulation time 545707329 ps
CPU time 6.3 seconds
Started Aug 18 05:51:41 PM PDT 24
Finished Aug 18 05:51:48 PM PDT 24
Peak memory 211092 kb
Host smart-7870b4cd-c3a4-4017-a7cb-6f94d5a52ab5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654255476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.654255476
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3424693552
Short name T25
Test name
Test status
Simulation time 1009897337 ps
CPU time 100.05 seconds
Started Aug 18 05:51:37 PM PDT 24
Finished Aug 18 05:53:17 PM PDT 24
Peak memory 235224 kb
Host smart-1cbd7ae6-b794-46c1-b87d-7f3aaee401e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424693552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3424693552
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1093267866
Short name T167
Test name
Test status
Simulation time 252844269 ps
CPU time 6.26 seconds
Started Aug 18 05:51:43 PM PDT 24
Finished Aug 18 05:51:49 PM PDT 24
Peak memory 211072 kb
Host smart-7d0a7feb-ba4a-4622-8124-dca1b808cc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093267866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1093267866
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.929346691
Short name T210
Test name
Test status
Simulation time 1682410267 ps
CPU time 6.37 seconds
Started Aug 18 05:51:44 PM PDT 24
Finished Aug 18 05:51:50 PM PDT 24
Peak memory 211476 kb
Host smart-b02cb17e-558c-4367-81b5-358b9ae88920
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929346691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.929346691
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3479840971
Short name T10
Test name
Test status
Simulation time 206369932 ps
CPU time 4.95 seconds
Started Aug 18 05:52:10 PM PDT 24
Finished Aug 18 05:52:15 PM PDT 24
Peak memory 211016 kb
Host smart-2d3d5fd5-cfad-4290-b326-3c357a947af4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479840971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3479840971
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1176783317
Short name T30
Test name
Test status
Simulation time 6384230844 ps
CPU time 100.4 seconds
Started Aug 18 05:52:09 PM PDT 24
Finished Aug 18 05:53:50 PM PDT 24
Peak memory 211344 kb
Host smart-53a306e3-e6a1-4a74-93e1-55aa79fe441a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176783317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1176783317
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1420288703
Short name T257
Test name
Test status
Simulation time 175311603 ps
CPU time 9.09 seconds
Started Aug 18 05:52:11 PM PDT 24
Finished Aug 18 05:52:20 PM PDT 24
Peak memory 211096 kb
Host smart-721590df-e152-4dc6-b654-0767815ed876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420288703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1420288703
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3843780800
Short name T287
Test name
Test status
Simulation time 144360359 ps
CPU time 6.02 seconds
Started Aug 18 05:52:08 PM PDT 24
Finished Aug 18 05:52:15 PM PDT 24
Peak memory 211052 kb
Host smart-fd69c570-bb83-46e5-974a-9c6489ce5cd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3843780800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3843780800
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2075118923
Short name T327
Test name
Test status
Simulation time 1132029568 ps
CPU time 14.08 seconds
Started Aug 18 05:52:12 PM PDT 24
Finished Aug 18 05:52:27 PM PDT 24
Peak memory 214156 kb
Host smart-9ef480d1-e8e5-4857-ba45-257306ef035e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075118923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2075118923
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3502356796
Short name T333
Test name
Test status
Simulation time 4140589858 ps
CPU time 102.07 seconds
Started Aug 18 05:52:14 PM PDT 24
Finished Aug 18 05:53:56 PM PDT 24
Peak memory 230640 kb
Host smart-2d257dbb-c37b-4eff-a2f1-77e7aada321c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502356796 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3502356796
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.148085752
Short name T171
Test name
Test status
Simulation time 251048598 ps
CPU time 4.7 seconds
Started Aug 18 05:52:08 PM PDT 24
Finished Aug 18 05:52:13 PM PDT 24
Peak memory 211072 kb
Host smart-246572f3-72bd-4eed-a391-e75c5dcfb285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148085752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.148085752
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.794161704
Short name T249
Test name
Test status
Simulation time 8343709049 ps
CPU time 129.49 seconds
Started Aug 18 05:52:06 PM PDT 24
Finished Aug 18 05:54:16 PM PDT 24
Peak memory 237676 kb
Host smart-24060299-583c-4f60-866a-0d7423a45af1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794161704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.794161704
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3675766033
Short name T29
Test name
Test status
Simulation time 3541994029 ps
CPU time 10.53 seconds
Started Aug 18 05:52:10 PM PDT 24
Finished Aug 18 05:52:21 PM PDT 24
Peak memory 211760 kb
Host smart-b3ce4b8f-b477-4e99-902d-70467ad3db85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675766033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3675766033
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3628427761
Short name T277
Test name
Test status
Simulation time 385535124 ps
CPU time 5.1 seconds
Started Aug 18 05:52:06 PM PDT 24
Finished Aug 18 05:52:11 PM PDT 24
Peak memory 211068 kb
Host smart-f11e88ea-eb06-4441-b595-b9142adb57f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3628427761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3628427761
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2861422932
Short name T13
Test name
Test status
Simulation time 220879220 ps
CPU time 12.4 seconds
Started Aug 18 05:52:05 PM PDT 24
Finished Aug 18 05:52:18 PM PDT 24
Peak memory 214028 kb
Host smart-b6121ec8-d571-4bae-99b2-39fe27a6789a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861422932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2861422932
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3420045827
Short name T290
Test name
Test status
Simulation time 4316817538 ps
CPU time 65.35 seconds
Started Aug 18 05:52:12 PM PDT 24
Finished Aug 18 05:53:17 PM PDT 24
Peak memory 221348 kb
Host smart-33c0b019-3c36-456e-84ff-a8cf99c1269f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420045827 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3420045827
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.988309963
Short name T190
Test name
Test status
Simulation time 111702243 ps
CPU time 4.08 seconds
Started Aug 18 05:52:14 PM PDT 24
Finished Aug 18 05:52:18 PM PDT 24
Peak memory 211068 kb
Host smart-94608c9a-c591-45de-b29e-2b41ccd6a23e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988309963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.988309963
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3656786751
Short name T165
Test name
Test status
Simulation time 51743242809 ps
CPU time 223.93 seconds
Started Aug 18 05:52:15 PM PDT 24
Finished Aug 18 05:55:59 PM PDT 24
Peak memory 228376 kb
Host smart-439747a5-39d6-47f7-8285-237d1c23e300
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656786751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3656786751
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3551781097
Short name T88
Test name
Test status
Simulation time 250570722 ps
CPU time 10.7 seconds
Started Aug 18 05:52:09 PM PDT 24
Finished Aug 18 05:52:19 PM PDT 24
Peak memory 211068 kb
Host smart-0a88bfd0-4b83-4ca1-bd9c-6d93a5c739db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551781097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3551781097
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.601087802
Short name T1
Test name
Test status
Simulation time 1200912737 ps
CPU time 5.8 seconds
Started Aug 18 05:52:07 PM PDT 24
Finished Aug 18 05:52:12 PM PDT 24
Peak memory 211068 kb
Host smart-32a64b51-c9a7-486f-b17e-0f04b6dd5ea7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601087802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.601087802
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3141811653
Short name T341
Test name
Test status
Simulation time 221445285 ps
CPU time 5.27 seconds
Started Aug 18 05:52:10 PM PDT 24
Finished Aug 18 05:52:15 PM PDT 24
Peak memory 212332 kb
Host smart-c28efdae-b968-476c-8ce1-925428a5386d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141811653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3141811653
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2614102953
Short name T152
Test name
Test status
Simulation time 3911540696 ps
CPU time 33.37 seconds
Started Aug 18 05:52:12 PM PDT 24
Finished Aug 18 05:52:46 PM PDT 24
Peak memory 220420 kb
Host smart-3c024bd1-422d-4b8a-a949-7a624c9bd8d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614102953 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2614102953
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3444342743
Short name T141
Test name
Test status
Simulation time 438840991 ps
CPU time 4.05 seconds
Started Aug 18 05:52:14 PM PDT 24
Finished Aug 18 05:52:19 PM PDT 24
Peak memory 211052 kb
Host smart-8fb6e801-9e70-45ba-96de-b6995ca1d12b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444342743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3444342743
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1570846118
Short name T38
Test name
Test status
Simulation time 1821450451 ps
CPU time 102.38 seconds
Started Aug 18 05:52:13 PM PDT 24
Finished Aug 18 05:53:55 PM PDT 24
Peak memory 239032 kb
Host smart-3375c5a2-7cf5-4b5b-bc17-c8e9e4ba90b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570846118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1570846118
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1593871935
Short name T276
Test name
Test status
Simulation time 347916666 ps
CPU time 9.1 seconds
Started Aug 18 05:52:11 PM PDT 24
Finished Aug 18 05:52:20 PM PDT 24
Peak memory 211528 kb
Host smart-ad914b9c-f16c-409a-9a47-af83d96df487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593871935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1593871935
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3424856912
Short name T311
Test name
Test status
Simulation time 145535904 ps
CPU time 5.91 seconds
Started Aug 18 05:52:09 PM PDT 24
Finished Aug 18 05:52:15 PM PDT 24
Peak memory 210980 kb
Host smart-2b4190a5-3f19-4c4e-84e7-5ffd1bb07af1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3424856912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3424856912
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2810522442
Short name T213
Test name
Test status
Simulation time 308925636 ps
CPU time 15.05 seconds
Started Aug 18 05:52:12 PM PDT 24
Finished Aug 18 05:52:28 PM PDT 24
Peak memory 213952 kb
Host smart-71a6b8c0-324b-4f02-bf63-793eb6260b1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810522442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2810522442
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.370995037
Short name T11
Test name
Test status
Simulation time 2510001909 ps
CPU time 52.83 seconds
Started Aug 18 05:52:07 PM PDT 24
Finished Aug 18 05:53:00 PM PDT 24
Peak memory 219816 kb
Host smart-750f76f3-3399-4080-8fe4-94261677dd30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370995037 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.370995037
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1239542714
Short name T131
Test name
Test status
Simulation time 347485779 ps
CPU time 4.06 seconds
Started Aug 18 05:52:07 PM PDT 24
Finished Aug 18 05:52:11 PM PDT 24
Peak memory 211084 kb
Host smart-08dcacaa-5f56-449e-9b84-1c3ff45d4481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239542714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1239542714
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2341943305
Short name T284
Test name
Test status
Simulation time 4872246390 ps
CPU time 220.89 seconds
Started Aug 18 05:52:21 PM PDT 24
Finished Aug 18 05:56:02 PM PDT 24
Peak memory 237628 kb
Host smart-30c5e284-7004-4e00-bbe7-8ab3b8bd96a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341943305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2341943305
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3519564761
Short name T33
Test name
Test status
Simulation time 173745393 ps
CPU time 8.85 seconds
Started Aug 18 05:52:07 PM PDT 24
Finished Aug 18 05:52:16 PM PDT 24
Peak memory 211100 kb
Host smart-27566aef-d66d-43ab-95de-fce47e7be20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519564761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3519564761
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2469338538
Short name T328
Test name
Test status
Simulation time 605338484 ps
CPU time 5.92 seconds
Started Aug 18 05:52:13 PM PDT 24
Finished Aug 18 05:52:19 PM PDT 24
Peak memory 211040 kb
Host smart-05c6a903-12bd-4577-b761-32fc8b340b05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2469338538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2469338538
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.573079073
Short name T186
Test name
Test status
Simulation time 361431275 ps
CPU time 9.52 seconds
Started Aug 18 05:52:22 PM PDT 24
Finished Aug 18 05:52:31 PM PDT 24
Peak memory 213564 kb
Host smart-bbf8c252-a217-4126-8132-052acc4719de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573079073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.573079073
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3270331439
Short name T51
Test name
Test status
Simulation time 3226133428 ps
CPU time 66.28 seconds
Started Aug 18 05:52:13 PM PDT 24
Finished Aug 18 05:53:20 PM PDT 24
Peak memory 221496 kb
Host smart-1dc2365d-1c5b-4660-904c-7573b5053723
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270331439 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3270331439
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3320286041
Short name T224
Test name
Test status
Simulation time 2480484335 ps
CPU time 4.87 seconds
Started Aug 18 05:52:12 PM PDT 24
Finished Aug 18 05:52:16 PM PDT 24
Peak memory 211128 kb
Host smart-6e75aab4-3bd0-46c1-b84a-3b3c80c69450
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320286041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3320286041
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1571077580
Short name T258
Test name
Test status
Simulation time 2702114023 ps
CPU time 58.71 seconds
Started Aug 18 05:52:07 PM PDT 24
Finished Aug 18 05:53:06 PM PDT 24
Peak memory 211420 kb
Host smart-0829d3b5-e515-49e8-96f3-53b5779b9280
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571077580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1571077580
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1910597741
Short name T163
Test name
Test status
Simulation time 305060537 ps
CPU time 9.13 seconds
Started Aug 18 05:52:12 PM PDT 24
Finished Aug 18 05:52:22 PM PDT 24
Peak memory 211448 kb
Host smart-2549e26b-4f2c-473a-b843-3bf243fa6f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910597741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1910597741
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2867684038
Short name T203
Test name
Test status
Simulation time 381585119 ps
CPU time 5.29 seconds
Started Aug 18 05:52:11 PM PDT 24
Finished Aug 18 05:52:16 PM PDT 24
Peak memory 211044 kb
Host smart-dc8d66b5-d14e-4c6c-9769-e0b94240d477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2867684038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2867684038
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3945228740
Short name T222
Test name
Test status
Simulation time 1105468657 ps
CPU time 17.69 seconds
Started Aug 18 05:52:19 PM PDT 24
Finished Aug 18 05:52:37 PM PDT 24
Peak memory 213920 kb
Host smart-f75ff3e0-b41a-49ee-935f-52e4599dff36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945228740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3945228740
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2672909388
Short name T140
Test name
Test status
Simulation time 1598736150 ps
CPU time 38.08 seconds
Started Aug 18 05:52:11 PM PDT 24
Finished Aug 18 05:52:49 PM PDT 24
Peak memory 219240 kb
Host smart-dfd07739-8ed7-4985-8573-902a24e4911e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672909388 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2672909388
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3973059534
Short name T92
Test name
Test status
Simulation time 175165751 ps
CPU time 3.97 seconds
Started Aug 18 05:52:13 PM PDT 24
Finished Aug 18 05:52:17 PM PDT 24
Peak memory 211088 kb
Host smart-e4f7c19f-fbbc-4377-a5d5-b1ccf2104bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973059534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3973059534
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3960776685
Short name T347
Test name
Test status
Simulation time 23980693428 ps
CPU time 121.49 seconds
Started Aug 18 05:52:11 PM PDT 24
Finished Aug 18 05:54:13 PM PDT 24
Peak memory 233544 kb
Host smart-48aa887b-b140-4c46-9a92-b58bd4e16435
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960776685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3960776685
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1344566823
Short name T248
Test name
Test status
Simulation time 257742983 ps
CPU time 11.18 seconds
Started Aug 18 05:52:13 PM PDT 24
Finished Aug 18 05:52:24 PM PDT 24
Peak memory 211096 kb
Host smart-5240b9db-5a55-4261-a646-2529ed5846fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344566823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1344566823
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2027503865
Short name T195
Test name
Test status
Simulation time 639764503 ps
CPU time 5.81 seconds
Started Aug 18 05:52:08 PM PDT 24
Finished Aug 18 05:52:14 PM PDT 24
Peak memory 211108 kb
Host smart-7e098f0e-9108-46a7-806a-1432a1632def
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2027503865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2027503865
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.769390811
Short name T344
Test name
Test status
Simulation time 333930361 ps
CPU time 11.62 seconds
Started Aug 18 05:52:10 PM PDT 24
Finished Aug 18 05:52:21 PM PDT 24
Peak memory 211540 kb
Host smart-bcb5eaaa-11e6-4974-84af-4426db1191cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769390811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.769390811
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1063567527
Short name T206
Test name
Test status
Simulation time 4264891125 ps
CPU time 96.46 seconds
Started Aug 18 05:52:16 PM PDT 24
Finished Aug 18 05:53:52 PM PDT 24
Peak memory 221840 kb
Host smart-9a0a4ca0-6942-4e73-804b-8162adeb962d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063567527 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1063567527
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3747628900
Short name T312
Test name
Test status
Simulation time 131315993 ps
CPU time 4.86 seconds
Started Aug 18 05:52:21 PM PDT 24
Finished Aug 18 05:52:26 PM PDT 24
Peak memory 211044 kb
Host smart-eea135f0-9ee9-4826-8e66-7d1329914cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747628900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3747628900
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2070554269
Short name T194
Test name
Test status
Simulation time 1431586991 ps
CPU time 87.39 seconds
Started Aug 18 05:52:16 PM PDT 24
Finished Aug 18 05:53:43 PM PDT 24
Peak memory 227972 kb
Host smart-fdd05339-8232-40dc-96d7-712d8285859d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070554269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2070554269
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3443514408
Short name T299
Test name
Test status
Simulation time 168654071 ps
CPU time 9.1 seconds
Started Aug 18 05:52:14 PM PDT 24
Finished Aug 18 05:52:23 PM PDT 24
Peak memory 211592 kb
Host smart-c807333b-fe3e-484a-9f51-7a9de6017d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443514408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3443514408
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4142650140
Short name T285
Test name
Test status
Simulation time 560325887 ps
CPU time 5.95 seconds
Started Aug 18 05:52:15 PM PDT 24
Finished Aug 18 05:52:21 PM PDT 24
Peak memory 211044 kb
Host smart-1a32aa66-11b1-4ca2-b4aa-5b285e340ee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142650140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4142650140
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.4225555475
Short name T119
Test name
Test status
Simulation time 219865861 ps
CPU time 8.35 seconds
Started Aug 18 05:52:18 PM PDT 24
Finished Aug 18 05:52:26 PM PDT 24
Peak memory 210980 kb
Host smart-0efb4fbe-46b4-4be5-8e2b-d93b9e666874
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225555475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.4225555475
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3772154840
Short name T316
Test name
Test status
Simulation time 16462512990 ps
CPU time 57.3 seconds
Started Aug 18 05:52:21 PM PDT 24
Finished Aug 18 05:53:19 PM PDT 24
Peak memory 221452 kb
Host smart-82a128e9-7238-4282-ac09-98f5888ede41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772154840 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3772154840
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1799545258
Short name T218
Test name
Test status
Simulation time 496896052 ps
CPU time 4.75 seconds
Started Aug 18 05:52:18 PM PDT 24
Finished Aug 18 05:52:23 PM PDT 24
Peak memory 211092 kb
Host smart-c2950b42-f55a-4729-846d-9cd08da4c9ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799545258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1799545258
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1961406257
Short name T253
Test name
Test status
Simulation time 1672702416 ps
CPU time 101.69 seconds
Started Aug 18 05:52:13 PM PDT 24
Finished Aug 18 05:53:55 PM PDT 24
Peak memory 212232 kb
Host smart-8f7e3e94-bd51-44d6-a784-2aad21957a6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961406257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1961406257
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1727251215
Short name T204
Test name
Test status
Simulation time 253114251 ps
CPU time 10.5 seconds
Started Aug 18 05:52:26 PM PDT 24
Finished Aug 18 05:52:37 PM PDT 24
Peak memory 211428 kb
Host smart-07576aed-bcc0-4de5-a21e-dee2895d22d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727251215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1727251215
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.817925356
Short name T124
Test name
Test status
Simulation time 134374394 ps
CPU time 5.16 seconds
Started Aug 18 05:52:17 PM PDT 24
Finished Aug 18 05:52:22 PM PDT 24
Peak memory 211084 kb
Host smart-c2e23e5f-4534-4f0d-8b58-8726337bd043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=817925356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.817925356
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3417275491
Short name T207
Test name
Test status
Simulation time 302939058 ps
CPU time 13.34 seconds
Started Aug 18 05:52:13 PM PDT 24
Finished Aug 18 05:52:27 PM PDT 24
Peak memory 213608 kb
Host smart-b2546422-3dbc-496c-b52f-7c726fdf38b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417275491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3417275491
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3332484875
Short name T48
Test name
Test status
Simulation time 2217040823 ps
CPU time 42.88 seconds
Started Aug 18 05:52:14 PM PDT 24
Finished Aug 18 05:52:57 PM PDT 24
Peak memory 220488 kb
Host smart-d8f8d6e1-ab15-4991-83cd-a2857bbcad61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332484875 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3332484875
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4169976407
Short name T87
Test name
Test status
Simulation time 127041219 ps
CPU time 4.83 seconds
Started Aug 18 05:52:13 PM PDT 24
Finished Aug 18 05:52:18 PM PDT 24
Peak memory 211048 kb
Host smart-c42362a0-d1e0-42a1-84b6-5eb59067e7b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169976407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4169976407
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3192204975
Short name T40
Test name
Test status
Simulation time 2863189463 ps
CPU time 131.43 seconds
Started Aug 18 05:52:20 PM PDT 24
Finished Aug 18 05:54:31 PM PDT 24
Peak memory 236908 kb
Host smart-ce4d45da-a0e5-462a-84f0-c7e38fcb7914
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192204975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3192204975
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4173892028
Short name T43
Test name
Test status
Simulation time 177192408 ps
CPU time 8.99 seconds
Started Aug 18 05:52:17 PM PDT 24
Finished Aug 18 05:52:26 PM PDT 24
Peak memory 211484 kb
Host smart-d344ad89-c5c0-4cc4-826d-55638078126d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173892028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4173892028
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.272696178
Short name T336
Test name
Test status
Simulation time 402390570 ps
CPU time 5.65 seconds
Started Aug 18 05:52:18 PM PDT 24
Finished Aug 18 05:52:24 PM PDT 24
Peak memory 211108 kb
Host smart-aa0716b3-2151-4aca-b64f-ce20c141171b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=272696178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.272696178
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3597304471
Short name T320
Test name
Test status
Simulation time 268756235 ps
CPU time 12.55 seconds
Started Aug 18 05:52:15 PM PDT 24
Finished Aug 18 05:52:28 PM PDT 24
Peak memory 214996 kb
Host smart-3ed831bf-7a75-4d5e-ad16-c7b2079771ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597304471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3597304471
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.37093952
Short name T117
Test name
Test status
Simulation time 3811180286 ps
CPU time 223.9 seconds
Started Aug 18 05:52:18 PM PDT 24
Finished Aug 18 05:56:02 PM PDT 24
Peak memory 222040 kb
Host smart-d8d14b3d-2b0f-459d-b92d-9e9f62859148
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37093952 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.37093952
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3589444407
Short name T7
Test name
Test status
Simulation time 127055285 ps
CPU time 4.97 seconds
Started Aug 18 05:51:37 PM PDT 24
Finished Aug 18 05:51:42 PM PDT 24
Peak memory 211060 kb
Host smart-72cd4de2-9fa7-4a11-92c9-4ee30a9fdc87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589444407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3589444407
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.363403551
Short name T329
Test name
Test status
Simulation time 58195074173 ps
CPU time 141.39 seconds
Started Aug 18 05:51:38 PM PDT 24
Finished Aug 18 05:54:00 PM PDT 24
Peak memory 233592 kb
Host smart-45bcbc23-3781-488d-ba18-834d172ac352
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363403551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.363403551
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4283020603
Short name T151
Test name
Test status
Simulation time 500136381 ps
CPU time 10.55 seconds
Started Aug 18 05:51:37 PM PDT 24
Finished Aug 18 05:51:48 PM PDT 24
Peak memory 211028 kb
Host smart-c2ceac81-5ed1-4dc5-a634-d3aa0a54e5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283020603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4283020603
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2907321631
Short name T32
Test name
Test status
Simulation time 378758068 ps
CPU time 5.27 seconds
Started Aug 18 05:51:39 PM PDT 24
Finished Aug 18 05:51:44 PM PDT 24
Peak memory 210964 kb
Host smart-49de9ff0-752d-4bdb-92e9-c91cf325e7b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2907321631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2907321631
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2346083899
Short name T24
Test name
Test status
Simulation time 759350331 ps
CPU time 50.76 seconds
Started Aug 18 05:51:36 PM PDT 24
Finished Aug 18 05:52:27 PM PDT 24
Peak memory 236728 kb
Host smart-b8724a28-912d-4ff5-b7a0-79d73ae5af36
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346083899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2346083899
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3001973578
Short name T58
Test name
Test status
Simulation time 181917282 ps
CPU time 5.31 seconds
Started Aug 18 05:51:37 PM PDT 24
Finished Aug 18 05:51:43 PM PDT 24
Peak memory 211348 kb
Host smart-ff894738-dedc-48df-8f5f-19d12c829df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001973578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3001973578
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.621303422
Short name T301
Test name
Test status
Simulation time 404024052 ps
CPU time 12.51 seconds
Started Aug 18 05:51:37 PM PDT 24
Finished Aug 18 05:51:49 PM PDT 24
Peak memory 213932 kb
Host smart-86aa1e0e-c7dd-4de5-a126-6d1bbb134906
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621303422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.621303422
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3926046384
Short name T323
Test name
Test status
Simulation time 11021568766 ps
CPU time 124.47 seconds
Started Aug 18 05:51:38 PM PDT 24
Finished Aug 18 05:53:43 PM PDT 24
Peak memory 231432 kb
Host smart-c3fde8a8-1398-423b-8137-33ac3845d0bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926046384 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3926046384
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3602409048
Short name T132
Test name
Test status
Simulation time 333191024 ps
CPU time 4.05 seconds
Started Aug 18 05:52:15 PM PDT 24
Finished Aug 18 05:52:19 PM PDT 24
Peak memory 211088 kb
Host smart-7aa57a8f-623c-409b-aa18-b2265646bde5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602409048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3602409048
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2348417090
Short name T137
Test name
Test status
Simulation time 175972946 ps
CPU time 9.6 seconds
Started Aug 18 05:52:14 PM PDT 24
Finished Aug 18 05:52:24 PM PDT 24
Peak memory 211092 kb
Host smart-63cf8feb-856d-4ec2-965e-2c6f80eb5e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348417090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2348417090
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2766620462
Short name T241
Test name
Test status
Simulation time 199163943 ps
CPU time 5.6 seconds
Started Aug 18 05:52:15 PM PDT 24
Finished Aug 18 05:52:21 PM PDT 24
Peak memory 210992 kb
Host smart-2af62a9b-ce3b-4e2f-adc7-f26443cfd44e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2766620462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2766620462
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1609756246
Short name T265
Test name
Test status
Simulation time 221263251 ps
CPU time 10.7 seconds
Started Aug 18 05:52:20 PM PDT 24
Finished Aug 18 05:52:31 PM PDT 24
Peak memory 213732 kb
Host smart-28a0cf39-f52c-414b-80e6-747e06f1f8f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609756246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1609756246
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2656563592
Short name T250
Test name
Test status
Simulation time 12456529184 ps
CPU time 239.23 seconds
Started Aug 18 05:52:16 PM PDT 24
Finished Aug 18 05:56:15 PM PDT 24
Peak memory 223100 kb
Host smart-982a6b3f-a560-4ff8-b37b-6d6e3ec827a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656563592 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2656563592
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3894457847
Short name T212
Test name
Test status
Simulation time 168851683 ps
CPU time 4.19 seconds
Started Aug 18 05:52:13 PM PDT 24
Finished Aug 18 05:52:17 PM PDT 24
Peak memory 211088 kb
Host smart-07f9c421-7a4b-4c49-af07-6c0c26e5bdea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894457847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3894457847
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1613786355
Short name T116
Test name
Test status
Simulation time 7225318506 ps
CPU time 78.98 seconds
Started Aug 18 05:52:16 PM PDT 24
Finished Aug 18 05:53:35 PM PDT 24
Peak memory 236976 kb
Host smart-457361fe-7077-4511-80a1-08e50a976680
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613786355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1613786355
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3449171605
Short name T147
Test name
Test status
Simulation time 1376887243 ps
CPU time 10.48 seconds
Started Aug 18 05:52:14 PM PDT 24
Finished Aug 18 05:52:24 PM PDT 24
Peak memory 211020 kb
Host smart-0d94cda1-8819-420e-bad2-28915c0a1ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449171605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3449171605
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.190713870
Short name T237
Test name
Test status
Simulation time 136183992 ps
CPU time 6.33 seconds
Started Aug 18 05:52:20 PM PDT 24
Finished Aug 18 05:52:26 PM PDT 24
Peak memory 211064 kb
Host smart-95008ffb-735c-4109-b70b-dcb8021e00fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=190713870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.190713870
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.776954495
Short name T315
Test name
Test status
Simulation time 388066056 ps
CPU time 9.84 seconds
Started Aug 18 05:52:15 PM PDT 24
Finished Aug 18 05:52:25 PM PDT 24
Peak memory 210976 kb
Host smart-6d941ca5-42cd-4d77-a8a7-6ee428006182
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776954495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.776954495
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1767099744
Short name T50
Test name
Test status
Simulation time 45009354432 ps
CPU time 264.77 seconds
Started Aug 18 05:52:12 PM PDT 24
Finished Aug 18 05:56:37 PM PDT 24
Peak memory 235660 kb
Host smart-09137a11-ac4a-4973-b239-679e66b2f68f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767099744 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1767099744
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1332477401
Short name T243
Test name
Test status
Simulation time 463900824 ps
CPU time 4.87 seconds
Started Aug 18 05:52:13 PM PDT 24
Finished Aug 18 05:52:18 PM PDT 24
Peak memory 211072 kb
Host smart-bc97de90-ba9d-4ef4-9b36-69fb7c16937d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332477401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1332477401
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.980509851
Short name T271
Test name
Test status
Simulation time 2589001666 ps
CPU time 107.31 seconds
Started Aug 18 05:52:18 PM PDT 24
Finished Aug 18 05:54:05 PM PDT 24
Peak memory 212484 kb
Host smart-0ded3f3d-29fa-41c4-8d41-363310dae1cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980509851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.980509851
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2618077215
Short name T209
Test name
Test status
Simulation time 410968602 ps
CPU time 10.37 seconds
Started Aug 18 05:52:15 PM PDT 24
Finished Aug 18 05:52:25 PM PDT 24
Peak memory 211484 kb
Host smart-b7aad401-73cf-4711-a21e-3f72bed67ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618077215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2618077215
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2448293818
Short name T136
Test name
Test status
Simulation time 551580909 ps
CPU time 5.99 seconds
Started Aug 18 05:52:15 PM PDT 24
Finished Aug 18 05:52:21 PM PDT 24
Peak memory 211076 kb
Host smart-f81d3727-298a-4ed0-a6dc-7311fbfdf3e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2448293818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2448293818
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1538336238
Short name T5
Test name
Test status
Simulation time 1072613387 ps
CPU time 11.82 seconds
Started Aug 18 05:52:12 PM PDT 24
Finished Aug 18 05:52:24 PM PDT 24
Peak memory 214204 kb
Host smart-51f72241-86af-4b38-87b4-2f8cb830deec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538336238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1538336238
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1792605045
Short name T14
Test name
Test status
Simulation time 7219952528 ps
CPU time 64.25 seconds
Started Aug 18 05:52:17 PM PDT 24
Finished Aug 18 05:53:21 PM PDT 24
Peak memory 221964 kb
Host smart-e73be612-85d9-40b2-b15f-e053297ebece
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792605045 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1792605045
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2797277338
Short name T128
Test name
Test status
Simulation time 351691430 ps
CPU time 3.95 seconds
Started Aug 18 05:52:30 PM PDT 24
Finished Aug 18 05:52:34 PM PDT 24
Peak memory 211088 kb
Host smart-4cb4b86f-cc19-4125-8381-579c66ecf58e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797277338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2797277338
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1293822235
Short name T169
Test name
Test status
Simulation time 6271639258 ps
CPU time 72.32 seconds
Started Aug 18 05:52:25 PM PDT 24
Finished Aug 18 05:53:38 PM PDT 24
Peak memory 212392 kb
Host smart-c360a02b-6286-4175-8dfa-06c6cf3356eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293822235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1293822235
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4145962755
Short name T245
Test name
Test status
Simulation time 1311172934 ps
CPU time 11.02 seconds
Started Aug 18 05:52:26 PM PDT 24
Finished Aug 18 05:52:37 PM PDT 24
Peak memory 211472 kb
Host smart-cd408bf2-ab3c-401d-8d69-87f20fb96624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145962755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4145962755
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1840098536
Short name T143
Test name
Test status
Simulation time 139499793 ps
CPU time 6.39 seconds
Started Aug 18 05:52:17 PM PDT 24
Finished Aug 18 05:52:23 PM PDT 24
Peak memory 211076 kb
Host smart-063c52a2-0554-4502-9184-ddd4eb87aa2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1840098536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1840098536
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2438381429
Short name T70
Test name
Test status
Simulation time 900274587 ps
CPU time 16.86 seconds
Started Aug 18 05:52:22 PM PDT 24
Finished Aug 18 05:52:39 PM PDT 24
Peak memory 214588 kb
Host smart-a9254ff8-e945-437b-987f-eb3592d2776a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438381429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2438381429
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1771281769
Short name T307
Test name
Test status
Simulation time 14548872421 ps
CPU time 221.71 seconds
Started Aug 18 05:52:26 PM PDT 24
Finished Aug 18 05:56:08 PM PDT 24
Peak memory 223800 kb
Host smart-d0dc3526-737b-413d-b116-f30e79a1e1a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771281769 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1771281769
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2216737356
Short name T338
Test name
Test status
Simulation time 175605209 ps
CPU time 4 seconds
Started Aug 18 05:52:28 PM PDT 24
Finished Aug 18 05:52:32 PM PDT 24
Peak memory 210956 kb
Host smart-43b52bb2-f21b-4cdf-900b-5d564f918852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216737356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2216737356
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2552089922
Short name T34
Test name
Test status
Simulation time 1853924658 ps
CPU time 106.2 seconds
Started Aug 18 05:52:23 PM PDT 24
Finished Aug 18 05:54:09 PM PDT 24
Peak memory 236260 kb
Host smart-081e9a17-db8d-4633-b77b-2e6057854c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552089922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2552089922
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3161932027
Short name T273
Test name
Test status
Simulation time 252258654 ps
CPU time 10.56 seconds
Started Aug 18 05:52:24 PM PDT 24
Finished Aug 18 05:52:35 PM PDT 24
Peak memory 211464 kb
Host smart-246eaac6-6cd7-4b35-85f8-0f3f5612b41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161932027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3161932027
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.558932007
Short name T268
Test name
Test status
Simulation time 143923194 ps
CPU time 6.17 seconds
Started Aug 18 05:52:26 PM PDT 24
Finished Aug 18 05:52:32 PM PDT 24
Peak memory 211100 kb
Host smart-87a866b1-1b82-44f8-b2ff-1518d75e992a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558932007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.558932007
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4107852295
Short name T234
Test name
Test status
Simulation time 841497269 ps
CPU time 15.92 seconds
Started Aug 18 05:52:24 PM PDT 24
Finished Aug 18 05:52:40 PM PDT 24
Peak memory 214544 kb
Host smart-abca13fd-94e9-4c65-9e37-9a400da9bcb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107852295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4107852295
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2013572255
Short name T262
Test name
Test status
Simulation time 3169255407 ps
CPU time 123.74 seconds
Started Aug 18 05:52:21 PM PDT 24
Finished Aug 18 05:54:25 PM PDT 24
Peak memory 222952 kb
Host smart-d54a3b04-e563-4bb9-8e24-5eefa4a8752c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013572255 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2013572255
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2585393592
Short name T282
Test name
Test status
Simulation time 334002452 ps
CPU time 3.97 seconds
Started Aug 18 05:52:23 PM PDT 24
Finished Aug 18 05:52:27 PM PDT 24
Peak memory 211096 kb
Host smart-fab8763b-1e9e-4e21-b50b-a1d7b8ec2dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585393592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2585393592
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3774337461
Short name T205
Test name
Test status
Simulation time 4109873319 ps
CPU time 77.4 seconds
Started Aug 18 05:52:27 PM PDT 24
Finished Aug 18 05:53:45 PM PDT 24
Peak memory 237620 kb
Host smart-58f5f12b-f63a-4d31-9cd5-62337f7c0acb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774337461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3774337461
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2364840233
Short name T46
Test name
Test status
Simulation time 923336808 ps
CPU time 10.86 seconds
Started Aug 18 05:52:25 PM PDT 24
Finished Aug 18 05:52:36 PM PDT 24
Peak memory 211604 kb
Host smart-135748ef-7f7e-4f31-95f1-79428b1b5d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364840233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2364840233
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.816052327
Short name T146
Test name
Test status
Simulation time 211726181 ps
CPU time 5.88 seconds
Started Aug 18 05:52:26 PM PDT 24
Finished Aug 18 05:52:32 PM PDT 24
Peak memory 210996 kb
Host smart-fa98da05-8006-4633-be6e-c6f8d396bd20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=816052327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.816052327
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1744385121
Short name T221
Test name
Test status
Simulation time 434997583 ps
CPU time 19.49 seconds
Started Aug 18 05:52:21 PM PDT 24
Finished Aug 18 05:52:41 PM PDT 24
Peak memory 214272 kb
Host smart-2066b099-4291-48f9-93db-08b512c32d61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744385121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1744385121
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3245065009
Short name T226
Test name
Test status
Simulation time 14500988866 ps
CPU time 133.13 seconds
Started Aug 18 05:52:26 PM PDT 24
Finished Aug 18 05:54:39 PM PDT 24
Peak memory 232824 kb
Host smart-b261ed44-c76f-415c-a395-baee97e92b14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245065009 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3245065009
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2411123446
Short name T269
Test name
Test status
Simulation time 174804028 ps
CPU time 4.16 seconds
Started Aug 18 05:52:21 PM PDT 24
Finished Aug 18 05:52:25 PM PDT 24
Peak memory 211056 kb
Host smart-def1f126-4d34-4e98-b861-fc86ecd538a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411123446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2411123446
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4264436604
Short name T39
Test name
Test status
Simulation time 3427010321 ps
CPU time 163.66 seconds
Started Aug 18 05:52:30 PM PDT 24
Finished Aug 18 05:55:13 PM PDT 24
Peak memory 236932 kb
Host smart-8aa2c234-405a-4eed-808a-722a3ce778a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264436604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4264436604
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4148101290
Short name T306
Test name
Test status
Simulation time 262491253 ps
CPU time 10.97 seconds
Started Aug 18 05:52:27 PM PDT 24
Finished Aug 18 05:52:38 PM PDT 24
Peak memory 211096 kb
Host smart-05fb61ef-0341-47a7-9738-fd2969cc7483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148101290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4148101290
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.57251380
Short name T252
Test name
Test status
Simulation time 138830135 ps
CPU time 6.06 seconds
Started Aug 18 05:52:25 PM PDT 24
Finished Aug 18 05:52:31 PM PDT 24
Peak memory 211100 kb
Host smart-167bfdfb-cbcf-4c77-b12e-8fd777934c9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57251380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.57251380
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2390917791
Short name T325
Test name
Test status
Simulation time 496379143 ps
CPU time 11.2 seconds
Started Aug 18 05:52:26 PM PDT 24
Finished Aug 18 05:52:38 PM PDT 24
Peak memory 214148 kb
Host smart-131be418-8a88-47fa-a358-3f43cb26137f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390917791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2390917791
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1998869454
Short name T199
Test name
Test status
Simulation time 956229554 ps
CPU time 4.81 seconds
Started Aug 18 05:52:27 PM PDT 24
Finished Aug 18 05:52:32 PM PDT 24
Peak memory 211060 kb
Host smart-ca340479-16d9-46b3-9e40-bb356edb6752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998869454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1998869454
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3719750009
Short name T173
Test name
Test status
Simulation time 12373104757 ps
CPU time 129.99 seconds
Started Aug 18 05:52:22 PM PDT 24
Finished Aug 18 05:54:32 PM PDT 24
Peak memory 228312 kb
Host smart-e1c16e0e-f4e8-4709-ac6d-0c2c46475257
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719750009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3719750009
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2266789749
Short name T300
Test name
Test status
Simulation time 660757482 ps
CPU time 10.38 seconds
Started Aug 18 05:52:27 PM PDT 24
Finished Aug 18 05:52:37 PM PDT 24
Peak memory 211496 kb
Host smart-05b0c361-54f2-4df7-aa5f-f8b6ce11c291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266789749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2266789749
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3458940560
Short name T90
Test name
Test status
Simulation time 846205183 ps
CPU time 5.46 seconds
Started Aug 18 05:52:26 PM PDT 24
Finished Aug 18 05:52:32 PM PDT 24
Peak memory 210992 kb
Host smart-98802914-41b8-4b96-86dc-f31166f0ed0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458940560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3458940560
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3429558642
Short name T71
Test name
Test status
Simulation time 1485024897 ps
CPU time 11.21 seconds
Started Aug 18 05:52:29 PM PDT 24
Finished Aug 18 05:52:41 PM PDT 24
Peak memory 212132 kb
Host smart-4838ec1e-3615-4932-97ed-f33c651e197c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429558642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3429558642
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.16248814
Short name T159
Test name
Test status
Simulation time 752119720 ps
CPU time 4.33 seconds
Started Aug 18 05:52:21 PM PDT 24
Finished Aug 18 05:52:25 PM PDT 24
Peak memory 211000 kb
Host smart-0d5c1336-3a13-4928-8569-c1c1dffe13e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16248814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.16248814
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.464420313
Short name T260
Test name
Test status
Simulation time 4082820788 ps
CPU time 102.92 seconds
Started Aug 18 05:52:28 PM PDT 24
Finished Aug 18 05:54:11 PM PDT 24
Peak memory 228304 kb
Host smart-586c3627-e066-436a-9a5c-a81df1bdf2e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464420313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.464420313
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.918113086
Short name T135
Test name
Test status
Simulation time 243488917 ps
CPU time 8.88 seconds
Started Aug 18 05:52:26 PM PDT 24
Finished Aug 18 05:52:35 PM PDT 24
Peak memory 211596 kb
Host smart-0fa341f3-4167-4421-9555-a5bad202758f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918113086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.918113086
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3390105011
Short name T295
Test name
Test status
Simulation time 533188092 ps
CPU time 5.96 seconds
Started Aug 18 05:52:22 PM PDT 24
Finished Aug 18 05:52:28 PM PDT 24
Peak memory 211020 kb
Host smart-c8a7e253-867e-4982-8e20-265db1cfe5a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3390105011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3390105011
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1823075816
Short name T197
Test name
Test status
Simulation time 777710815 ps
CPU time 20.15 seconds
Started Aug 18 05:52:28 PM PDT 24
Finished Aug 18 05:52:48 PM PDT 24
Peak memory 215484 kb
Host smart-e75dede6-3e6b-4b5e-850c-7ddc138aac36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823075816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1823075816
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.297541154
Short name T44
Test name
Test status
Simulation time 7418132563 ps
CPU time 62.11 seconds
Started Aug 18 05:52:20 PM PDT 24
Finished Aug 18 05:53:22 PM PDT 24
Peak memory 221728 kb
Host smart-c1037c6c-beb0-4185-af4e-ee77c5bfc3d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297541154 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.297541154
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1015052863
Short name T214
Test name
Test status
Simulation time 85848491 ps
CPU time 4.13 seconds
Started Aug 18 05:52:25 PM PDT 24
Finished Aug 18 05:52:30 PM PDT 24
Peak memory 211004 kb
Host smart-690e01a9-ee04-4b86-9955-07cbfe42ccee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015052863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1015052863
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4200477124
Short name T233
Test name
Test status
Simulation time 7856195756 ps
CPU time 45.06 seconds
Started Aug 18 05:52:25 PM PDT 24
Finished Aug 18 05:53:10 PM PDT 24
Peak memory 228408 kb
Host smart-9036ccc0-6c54-4d42-ac02-0ddbd5123652
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200477124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.4200477124
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1333165063
Short name T264
Test name
Test status
Simulation time 337706474 ps
CPU time 8.85 seconds
Started Aug 18 05:52:28 PM PDT 24
Finished Aug 18 05:52:37 PM PDT 24
Peak memory 211416 kb
Host smart-ece97b43-7a55-4633-9ca0-63e8c3d0c34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333165063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1333165063
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1780536439
Short name T99
Test name
Test status
Simulation time 548461734 ps
CPU time 5.85 seconds
Started Aug 18 05:52:24 PM PDT 24
Finished Aug 18 05:52:30 PM PDT 24
Peak memory 210992 kb
Host smart-b2c60f92-50e1-4a1a-9250-22d561aa32ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1780536439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1780536439
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1266520999
Short name T193
Test name
Test status
Simulation time 643068152 ps
CPU time 8.63 seconds
Started Aug 18 05:52:27 PM PDT 24
Finished Aug 18 05:52:35 PM PDT 24
Peak memory 211340 kb
Host smart-55a248c7-afb3-4f0c-b908-076912b0e4c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266520999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1266520999
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.773988396
Short name T188
Test name
Test status
Simulation time 20847160886 ps
CPU time 117.99 seconds
Started Aug 18 05:52:23 PM PDT 24
Finished Aug 18 05:54:21 PM PDT 24
Peak memory 234800 kb
Host smart-a357e5ef-c3cd-4aa4-9b89-19b69cde7d4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773988396 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.773988396
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1114124322
Short name T330
Test name
Test status
Simulation time 261454125 ps
CPU time 4.87 seconds
Started Aug 18 05:51:44 PM PDT 24
Finished Aug 18 05:51:49 PM PDT 24
Peak memory 211092 kb
Host smart-efe20754-c05a-471a-b7fd-8c76cb0fbfd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114124322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1114124322
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.198273621
Short name T337
Test name
Test status
Simulation time 40921593711 ps
CPU time 157.6 seconds
Started Aug 18 05:51:38 PM PDT 24
Finished Aug 18 05:54:15 PM PDT 24
Peak memory 211568 kb
Host smart-68fbf72f-520e-480b-ab8e-c9840e556322
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198273621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.198273621
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1685552169
Short name T168
Test name
Test status
Simulation time 1038184045 ps
CPU time 10.71 seconds
Started Aug 18 05:51:45 PM PDT 24
Finished Aug 18 05:51:56 PM PDT 24
Peak memory 211556 kb
Host smart-abfffc85-cec1-4819-87c1-3d70d990f23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685552169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1685552169
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2113277591
Short name T308
Test name
Test status
Simulation time 138194610 ps
CPU time 6.08 seconds
Started Aug 18 05:51:34 PM PDT 24
Finished Aug 18 05:51:41 PM PDT 24
Peak memory 210996 kb
Host smart-79f725f3-e198-4d78-8b85-3433ecc02917
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2113277591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2113277591
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3921394171
Short name T202
Test name
Test status
Simulation time 529702877 ps
CPU time 6.44 seconds
Started Aug 18 05:51:54 PM PDT 24
Finished Aug 18 05:52:01 PM PDT 24
Peak memory 211376 kb
Host smart-772638af-821d-435b-850d-9d19fa19ecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921394171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3921394171
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1102847020
Short name T297
Test name
Test status
Simulation time 1073613708 ps
CPU time 14.45 seconds
Started Aug 18 05:51:35 PM PDT 24
Finished Aug 18 05:51:50 PM PDT 24
Peak memory 213932 kb
Host smart-8e602d4e-1352-4221-a99d-fdacce667a36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102847020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1102847020
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3324796304
Short name T211
Test name
Test status
Simulation time 3890539537 ps
CPU time 244.33 seconds
Started Aug 18 05:51:50 PM PDT 24
Finished Aug 18 05:55:54 PM PDT 24
Peak memory 221624 kb
Host smart-9f38ccd0-2058-4a52-9f4c-179242dd895d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324796304 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3324796304
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.584724786
Short name T156
Test name
Test status
Simulation time 2582082033 ps
CPU time 90.14 seconds
Started Aug 18 05:51:44 PM PDT 24
Finished Aug 18 05:53:14 PM PDT 24
Peak memory 228404 kb
Host smart-a90b9229-9788-4aaf-a146-91b55cee9ce5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584724786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.584724786
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1457653430
Short name T181
Test name
Test status
Simulation time 250970273 ps
CPU time 10.85 seconds
Started Aug 18 05:51:48 PM PDT 24
Finished Aug 18 05:51:59 PM PDT 24
Peak memory 211524 kb
Host smart-f5241202-d140-457b-bf3b-8016adf46645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457653430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1457653430
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.100653573
Short name T198
Test name
Test status
Simulation time 97746169 ps
CPU time 5.71 seconds
Started Aug 18 05:51:57 PM PDT 24
Finished Aug 18 05:52:03 PM PDT 24
Peak memory 211112 kb
Host smart-78a86bf4-951f-46fc-91b7-177ec152a037
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100653573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.100653573
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2707150293
Short name T31
Test name
Test status
Simulation time 213233692 ps
CPU time 5.55 seconds
Started Aug 18 05:51:45 PM PDT 24
Finished Aug 18 05:51:50 PM PDT 24
Peak memory 212328 kb
Host smart-9943233c-77f2-437b-bed9-0eda9b5b3737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707150293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2707150293
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2263048976
Short name T160
Test name
Test status
Simulation time 593603429 ps
CPU time 12.69 seconds
Started Aug 18 05:51:56 PM PDT 24
Finished Aug 18 05:52:09 PM PDT 24
Peak memory 214040 kb
Host smart-55539b85-e375-456e-ad5f-e631aead214b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263048976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2263048976
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1253007360
Short name T8
Test name
Test status
Simulation time 4813290948 ps
CPU time 45.85 seconds
Started Aug 18 05:51:56 PM PDT 24
Finished Aug 18 05:52:42 PM PDT 24
Peak memory 221584 kb
Host smart-f575e42d-d946-4c11-81be-9b8639fc7627
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253007360 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1253007360
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1607544377
Short name T232
Test name
Test status
Simulation time 126797897 ps
CPU time 4.87 seconds
Started Aug 18 05:51:56 PM PDT 24
Finished Aug 18 05:52:01 PM PDT 24
Peak memory 211088 kb
Host smart-c11de500-d265-4345-81e0-969c186f9374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607544377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1607544377
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2125484473
Short name T272
Test name
Test status
Simulation time 1784609999 ps
CPU time 79.59 seconds
Started Aug 18 05:51:51 PM PDT 24
Finished Aug 18 05:53:11 PM PDT 24
Peak memory 236608 kb
Host smart-44665897-3cb7-42c3-80f9-7360d4cfb65a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125484473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2125484473
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.165213503
Short name T23
Test name
Test status
Simulation time 998631729 ps
CPU time 10.86 seconds
Started Aug 18 05:51:45 PM PDT 24
Finished Aug 18 05:51:56 PM PDT 24
Peak memory 211028 kb
Host smart-26672d15-4eea-4571-b1ad-566f36c0c777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165213503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.165213503
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2121175501
Short name T283
Test name
Test status
Simulation time 543093990 ps
CPU time 6.29 seconds
Started Aug 18 05:51:48 PM PDT 24
Finished Aug 18 05:51:54 PM PDT 24
Peak memory 211076 kb
Host smart-2ac93b35-1126-48b9-b847-0fc1ad0429a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2121175501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2121175501
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3688065038
Short name T139
Test name
Test status
Simulation time 273796528 ps
CPU time 5.97 seconds
Started Aug 18 05:51:48 PM PDT 24
Finished Aug 18 05:51:54 PM PDT 24
Peak memory 211292 kb
Host smart-9b486426-c46b-46a5-9f8a-2642c5254d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688065038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3688065038
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1923115877
Short name T122
Test name
Test status
Simulation time 254420899 ps
CPU time 12.57 seconds
Started Aug 18 05:51:44 PM PDT 24
Finished Aug 18 05:51:56 PM PDT 24
Peak memory 213324 kb
Host smart-27e88097-f017-424e-aa80-b59b2b30992b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923115877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1923115877
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.890094709
Short name T255
Test name
Test status
Simulation time 9690459464 ps
CPU time 96.94 seconds
Started Aug 18 05:51:46 PM PDT 24
Finished Aug 18 05:53:23 PM PDT 24
Peak memory 223520 kb
Host smart-7e2a61ad-1dd4-44bb-a3b8-7cda83656616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890094709 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.890094709
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2935646382
Short name T157
Test name
Test status
Simulation time 87171730 ps
CPU time 3.92 seconds
Started Aug 18 05:51:44 PM PDT 24
Finished Aug 18 05:51:48 PM PDT 24
Peak memory 211096 kb
Host smart-ab9c2b33-1a9b-4a27-bb2a-95c3d8ad203e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935646382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2935646382
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3073096746
Short name T59
Test name
Test status
Simulation time 195112909 ps
CPU time 5.4 seconds
Started Aug 18 05:51:51 PM PDT 24
Finished Aug 18 05:51:57 PM PDT 24
Peak memory 211096 kb
Host smart-9a09255b-1321-43fb-b69c-8a8d74339b35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3073096746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3073096746
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2699752603
Short name T91
Test name
Test status
Simulation time 95134708 ps
CPU time 5.47 seconds
Started Aug 18 05:51:57 PM PDT 24
Finished Aug 18 05:52:03 PM PDT 24
Peak memory 211940 kb
Host smart-475ab497-cd25-4835-b2bc-2b4c58c5842f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699752603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2699752603
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.526024851
Short name T175
Test name
Test status
Simulation time 396439450 ps
CPU time 20.87 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:52:23 PM PDT 24
Peak memory 216240 kb
Host smart-39885532-451b-4f75-96a3-c47f4f8f24f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526024851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.526024851
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.637249036
Short name T200
Test name
Test status
Simulation time 86871000 ps
CPU time 4.07 seconds
Started Aug 18 05:51:45 PM PDT 24
Finished Aug 18 05:51:49 PM PDT 24
Peak memory 211088 kb
Host smart-ac33cf8d-e648-4a99-856e-9ca4dd73372c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637249036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.637249036
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3306569374
Short name T189
Test name
Test status
Simulation time 2512552918 ps
CPU time 114.47 seconds
Started Aug 18 05:51:47 PM PDT 24
Finished Aug 18 05:53:41 PM PDT 24
Peak memory 228412 kb
Host smart-f3885d67-32ff-4f2a-8141-0a8e4e848d71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306569374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3306569374
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.29100321
Short name T144
Test name
Test status
Simulation time 3348343549 ps
CPU time 9.23 seconds
Started Aug 18 05:51:46 PM PDT 24
Finished Aug 18 05:51:56 PM PDT 24
Peak memory 211528 kb
Host smart-7b2d4a14-a21f-469b-a0af-fd9f0153832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29100321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.29100321
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2245081427
Short name T346
Test name
Test status
Simulation time 97286238 ps
CPU time 5.21 seconds
Started Aug 18 05:51:45 PM PDT 24
Finished Aug 18 05:51:51 PM PDT 24
Peak memory 211064 kb
Host smart-f6bdd64c-faf4-44af-b97d-d2c7c5c9c60f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2245081427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2245081427
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3099122097
Short name T166
Test name
Test status
Simulation time 94549228 ps
CPU time 5.54 seconds
Started Aug 18 05:51:52 PM PDT 24
Finished Aug 18 05:51:58 PM PDT 24
Peak memory 211108 kb
Host smart-4c8ef4ae-682f-428a-9caa-abee4d8fadb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099122097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3099122097
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2526791959
Short name T72
Test name
Test status
Simulation time 1809152142 ps
CPU time 18.59 seconds
Started Aug 18 05:51:57 PM PDT 24
Finished Aug 18 05:52:16 PM PDT 24
Peak memory 212752 kb
Host smart-09ae4350-e005-49ba-9ab9-5ec7046d4630
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526791959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2526791959
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1321921704
Short name T47
Test name
Test status
Simulation time 4268917815 ps
CPU time 84.39 seconds
Started Aug 18 05:52:02 PM PDT 24
Finished Aug 18 05:53:27 PM PDT 24
Peak memory 222984 kb
Host smart-07cb1abb-6c9f-477c-a165-1dd7ea9f9844
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321921704 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1321921704
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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