Total Module Definition Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.29	98.94	91.49	97.63	100.00	97.63	98.08

Total modules in report: 43

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NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
rom_ctrl_scrambled_rom	87.50	75.00					100.00
prim_generic_rom	88.89	66.67				100.00	100.00
prim_count	90.00			90.00
prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )	90.00			90.00
prim_count ( parameter Width=3,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )	90.00			90.00
tlul_adapter_sram	91.80	97.22	80.31			89.66	100.00
prim_fifo_sync	92.01	100.00	68.06			100.00	100.00
prim_fifo_sync	100.00						100.00
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )	84.38	100.00	68.75
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )	100.00					100.00
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )	93.06	100.00	79.17			100.00
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )	78.12	100.00	56.25
tlul_rsp_intg_gen	94.44	88.89					100.00
tlul_rsp_intg_gen	100.00						100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )	66.67	66.67
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=0 )	100.00	100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )	100.00	100.00
rom_ctrl	94.99	100.00	98.28	97.26		100.00	79.41
rom_ctrl_mux	95.24	100.00	85.71			100.00
prim_fifo_sync_cnt	97.10	100.00	91.30			100.00
rom_ctrl_fsm	98.67	100.00	96.36		100.00	96.97	100.00
tlul_adapter_reg	98.91	100.00	95.65			100.00	100.00
rom_ctrl_compare	99.53	100.00	97.67		100.00	100.00	100.00
rom_ctrl_regs_csr_assert_fpv	100.00						100.00
tlul_data_integ_dec	100.00	100.00
prim_sparse_fsm_flop	100.00	100.00					100.00
tlul_cmd_intg_chk	100.00	100.00					100.00
rom_ctrl_counter	100.00	100.00	100.00			100.00	100.00
prim_alert_sender	100.00			100.00
rom_ctrl_regs_reg_top	100.00	100.00	100.00			100.00	100.00
prim_mubi4_sender	100.00	100.00					100.00
tlul_assert	100.00	100.00				100.00	100.00
prim_onehot_check	100.00			100.00
prim_subreg	100.00	100.00	100.00			100.00
prim_subreg	100.00	100.00				100.00
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 )	100.00		100.00
prim_subreg ( parameter DW=32,SwAccess=1,RESVAL=0,Mubi=0 )	100.00		100.00
prim_secded_inv_39_32_dec	100.00			100.00
prim_generic_buf	100.00	100.00
prim_subreg_arb	100.00	100.00
prim_rom_adv	100.00	100.00				100.00	100.00
prim_subreg_ext	100.00	100.00
prim_secded_inv_39_32_enc	100.00	100.00
tlul_sram_byte	100.00	100.00					100.00
tlul_err	100.00	100.00	100.00			100.00	100.00
prim_subst_perm	100.00	100.00
prim_secded_inv_64_57_enc	100.00	100.00
prim_secded_inv_64_57_dec	100.00			100.00
prim_prince	100.00			100.00
prim_generic_flop	100.00	100.00				100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
prim_flop
tb
prim_rom
prim_sec_anchor_buf