Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

606111

1

T3

184

T4

304

T5

23

full_word

377917

1

T1

4

T2

4

T3

16

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	983708	1			T1	4		T2	4		T3	200
auto[TlIntgErrCmd]	85	1			T52	3		T53	1		T54	4
auto[TlIntgErrData]	117	1			T52	3		T53	6		T54	7
auto[TlIntgErrBoth]	118	1			T52	4		T53	3		T54	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178103

1

T1

4

T2

4

T3

200

auto[1]

805925

1

T7

13713

T11

13874

T16

20734

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	86951	1			T3	184		T4	304		T5	23
auto[TlIntgErrNone]	partial	auto[1]	518869	1			T7	9038		T11	8571		T16	13250
auto[TlIntgErrNone]	full_word	auto[0]	91015	1			T1	4		T2	4		T3	16
auto[TlIntgErrNone]	full_word	auto[1]	286873	1			T7	4675		T11	5303		T16	7484
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T52	1		T53	1		T54	2
auto[TlIntgErrCmd]	partial	auto[1]	38	1			T52	2		T54	2		T102	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T109	1		T110	2		T111	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T109	1		T100	1		T103	2
auto[TlIntgErrData]	partial	auto[0]	44	1			T52	1		T53	4		T54	2
auto[TlIntgErrData]	partial	auto[1]	62	1			T52	2		T53	2		T54	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T54	1		T110	2		T103	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T112	1		T100	1		T110	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T52	2		T53	1		T54	1
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T52	2		T53	1		T54	7
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T53	1		T54	1		T113	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T102	1		T100	2		T114	1