| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.53 | 96.89 | 92.42 | 97.67 | 100.00 | 98.62 | 98.05 | 99.06 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 64.66 | 64.66 | 92.58 | 92.58 | 68.96 | 68.96 | 51.98 | 51.98 | 40.00 | 40.00 | 89.31 | 89.31 | 93.85 | 93.85 | 15.93 | 15.93 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1797055063 |
| 78.55 | 13.89 | 92.94 | 0.36 | 75.56 | 6.60 | 75.10 | 23.12 | 40.00 | 0.00 | 91.03 | 1.72 | 95.35 | 1.50 | 79.86 | 63.93 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3490125418 |
| 84.09 | 5.54 | 93.54 | 0.60 | 79.78 | 4.21 | 84.12 | 9.03 | 60.00 | 20.00 | 93.79 | 2.76 | 95.65 | 0.30 | 81.73 | 1.87 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2584974432 |
| 88.74 | 4.66 | 93.54 | 0.00 | 81.88 | 2.11 | 87.45 | 3.33 | 86.67 | 26.67 | 94.14 | 0.34 | 95.80 | 0.15 | 81.73 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1518640649 |
| 91.83 | 3.08 | 96.53 | 2.99 | 88.06 | 6.18 | 94.90 | 7.45 | 86.67 | 0.00 | 95.52 | 1.38 | 96.10 | 0.30 | 85.01 | 3.28 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3383596789 |
| 93.04 | 1.21 | 96.53 | 0.00 | 88.48 | 0.42 | 95.92 | 1.02 | 93.33 | 6.67 | 95.86 | 0.34 | 96.10 | 0.00 | 85.01 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1254547417 |
| 94.18 | 1.15 | 96.65 | 0.12 | 88.90 | 0.42 | 95.92 | 0.00 | 100.00 | 6.67 | 96.21 | 0.34 | 96.10 | 0.00 | 85.48 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.238345774 |
| 95.30 | 1.12 | 96.89 | 0.24 | 89.61 | 0.70 | 95.92 | 0.00 | 100.00 | 0.00 | 97.24 | 1.03 | 96.10 | 0.00 | 91.33 | 5.85 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3039702769 |
| 95.92 | 0.62 | 96.89 | 0.00 | 89.75 | 0.14 | 96.83 | 0.90 | 100.00 | 0.00 | 97.24 | 0.00 | 96.10 | 0.00 | 94.61 | 3.28 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2058828622 |
| 96.28 | 0.37 | 96.89 | 0.00 | 90.45 | 0.70 | 96.88 | 0.05 | 100.00 | 0.00 | 97.59 | 0.34 | 96.40 | 0.30 | 95.78 | 1.17 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.2240131812 |
| 96.59 | 0.31 | 96.89 | 0.00 | 90.87 | 0.42 | 97.20 | 0.33 | 100.00 | 0.00 | 98.28 | 0.69 | 96.40 | 0.00 | 96.49 | 0.70 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.1692996595 |
| 96.76 | 0.17 | 96.89 | 0.00 | 90.87 | 0.00 | 97.20 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.60 | 1.20 | 96.49 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1019518967 |
| 96.93 | 0.17 | 96.89 | 0.00 | 90.87 | 0.00 | 97.20 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.60 | 0.00 | 97.66 | 1.17 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.743856884 |
| 97.04 | 0.12 | 96.89 | 0.00 | 91.01 | 0.14 | 97.40 | 0.20 | 100.00 | 0.00 | 98.28 | 0.00 | 97.60 | 0.00 | 98.13 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.1105305581 |
| 97.15 | 0.11 | 96.89 | 0.00 | 91.43 | 0.42 | 97.40 | 0.00 | 100.00 | 0.00 | 98.62 | 0.34 | 97.60 | 0.00 | 98.13 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.4159020500 |
| 97.25 | 0.10 | 96.89 | 0.00 | 91.99 | 0.56 | 97.53 | 0.12 | 100.00 | 0.00 | 98.62 | 0.00 | 97.60 | 0.00 | 98.13 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.3934472565 |
| 97.32 | 0.07 | 96.89 | 0.00 | 91.99 | 0.00 | 97.53 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.60 | 0.00 | 98.59 | 0.47 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2462297409 |
| 97.36 | 0.04 | 96.89 | 0.00 | 91.99 | 0.00 | 97.67 | 0.15 | 100.00 | 0.00 | 98.62 | 0.00 | 97.75 | 0.15 | 98.59 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.908791701 |
| 97.40 | 0.04 | 96.89 | 0.00 | 92.13 | 0.14 | 97.67 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.15 | 98.59 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2262460392 |
| 97.44 | 0.04 | 96.89 | 0.00 | 92.42 | 0.28 | 97.67 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.00 | 98.59 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.503310139 |
| 97.48 | 0.03 | 96.89 | 0.00 | 92.42 | 0.00 | 97.67 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.00 | 98.83 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1109891991 |
| 97.51 | 0.03 | 96.89 | 0.00 | 92.42 | 0.00 | 97.67 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.00 | 99.06 | 0.23 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3196914526 |
| 97.53 | 0.02 | 96.89 | 0.00 | 92.42 | 0.00 | 97.67 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 98.05 | 0.15 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1489405520 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2001135179 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4196585528 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1701403030 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1043756411 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3588731796 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1502162095 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2482778369 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2367659546 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2442030100 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2850950134 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.717319847 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3113980794 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.126898999 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3368847002 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3750457600 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1229484718 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.241695219 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4202765682 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1220652172 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2866740421 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2385839392 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2527558414 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.871011128 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2196940202 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.321497922 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2220753171 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.863589055 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2710547179 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3337918705 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.292098495 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1538811836 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2355451943 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.764587520 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3842195975 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.32847918 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2225214249 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.905898421 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.577182981 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1645355196 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2849401037 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3883502476 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.704327839 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.277937432 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3114683746 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2932873166 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1575704409 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3330230571 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2612555004 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3814009066 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.747375991 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4109881750 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3455572611 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2423764493 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1841843960 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1596831858 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3377503395 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2979439812 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.264086364 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1084410936 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.731480627 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.636393379 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2067122036 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.152924856 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.885347950 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4009682839 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.66043839 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2256731350 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.799777522 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1621361907 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2692018835 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1192242335 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1589573773 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.834094769 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2048436365 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2455651540 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3189366384 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1963732602 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2341091649 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2371331492 |
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| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2835533253 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.873492423 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.1094154123 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.553143010 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.4191008292 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.395998385 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.682286657 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2763565084 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.1927642393 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4054259683 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3424237367 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.2463125560 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.3772240366 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2653165020 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.3667603787 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.922314694 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.702830235 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.3126577480 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.585013372 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.218100672 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1308796815 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1282725340 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.1549058097 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3848221870 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1081914495 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1161194316 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.2314017966 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3007140749 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.3713472909 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.3963020189 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.1371973351 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.191338842 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.695023178 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1417833933 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.3250431557 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.784112896 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.258556096 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2030560122 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1017707485 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3557819856 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3886695144 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.2124541219 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.2061259004 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1812160893 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.6242627 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2566872187 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.2167775249 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.1093976617 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.2633606353 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3635603435 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.2375664203 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3894887579 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.209736366 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.417308534 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.3409746878 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.4271100635 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2539987025 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2887921357 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1468165234 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.816013164 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3640709847 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.1933335282 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.375916898 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.192350606 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.230784419 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.2952368207 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.3530474603 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.157614285 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.3955782298 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3828144291 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2417979122 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.728350989 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1335725917 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.2820126617 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.2910407142 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1308227578 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3206855813 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.295361685 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3409437339 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.2026800302 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.3396848333 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3748798240 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1009511494 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2637347853 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2344183101 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1456158000 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3615572021 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.3769593008 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.1576280137 |
| /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2903917576 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.3934472565 | Aug 28 09:25:16 PM UTC 24 | Aug 28 09:25:23 PM UTC 24 | 520479870 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.2424382456 | Aug 28 09:25:14 PM UTC 24 | Aug 28 09:25:24 PM UTC 24 | 532913751 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1227872588 | Aug 28 09:25:15 PM UTC 24 | Aug 28 09:25:25 PM UTC 24 | 539155624 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3048818792 | Aug 28 09:25:16 PM UTC 24 | Aug 28 09:25:26 PM UTC 24 | 197224878 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.1474104652 | Aug 28 09:25:16 PM UTC 24 | Aug 28 09:25:26 PM UTC 24 | 102083024 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3254037355 | Aug 28 09:25:21 PM UTC 24 | Aug 28 09:25:26 PM UTC 24 | 92062257 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.546047011 | Aug 28 09:25:23 PM UTC 24 | Aug 28 09:25:32 PM UTC 24 | 157969745 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1254547417 | Aug 28 09:25:18 PM UTC 24 | Aug 28 09:25:32 PM UTC 24 | 173848058 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1797055063 | Aug 28 09:25:15 PM UTC 24 | Aug 28 09:25:33 PM UTC 24 | 1136207578 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.2928532716 | Aug 28 09:25:15 PM UTC 24 | Aug 28 09:25:33 PM UTC 24 | 251017149 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2058828622 | Aug 28 09:25:25 PM UTC 24 | Aug 28 09:25:35 PM UTC 24 | 570282056 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.317173632 | Aug 28 09:25:30 PM UTC 24 | Aug 28 09:25:37 PM UTC 24 | 378034415 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1903013507 | Aug 28 09:25:16 PM UTC 24 | Aug 28 09:25:38 PM UTC 24 | 228137381 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.3039699418 | Aug 28 09:25:32 PM UTC 24 | Aug 28 09:25:43 PM UTC 24 | 527822818 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.472506307 | Aug 28 09:25:33 PM UTC 24 | Aug 28 09:25:44 PM UTC 24 | 141621295 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2584974432 | Aug 28 09:25:26 PM UTC 24 | Aug 28 09:25:44 PM UTC 24 | 927042051 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2763975052 | Aug 28 09:25:34 PM UTC 24 | Aug 28 09:25:44 PM UTC 24 | 329496220 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.221607414 | Aug 28 09:25:38 PM UTC 24 | Aug 28 09:25:45 PM UTC 24 | 922185769 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.167439053 | Aug 28 09:25:39 PM UTC 24 | Aug 28 09:25:45 PM UTC 24 | 456815827 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.1443464275 | Aug 28 09:25:33 PM UTC 24 | Aug 28 09:25:46 PM UTC 24 | 396328594 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.3991112066 | Aug 28 09:25:40 PM UTC 24 | Aug 28 09:25:50 PM UTC 24 | 97751360 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.1692996595 | Aug 28 09:25:23 PM UTC 24 | Aug 28 09:25:50 PM UTC 24 | 2700880142 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.977389492 | Aug 28 09:25:39 PM UTC 24 | Aug 28 09:25:52 PM UTC 24 | 1633017312 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2878488845 | Aug 28 09:25:46 PM UTC 24 | Aug 28 09:25:53 PM UTC 24 | 88044654 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.816013164 | Aug 28 09:25:46 PM UTC 24 | Aug 28 09:25:55 PM UTC 24 | 372631891 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3640709847 | Aug 28 09:25:46 PM UTC 24 | Aug 28 09:25:56 PM UTC 24 | 365785099 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2539987025 | Aug 28 09:25:52 PM UTC 24 | Aug 28 09:26:00 PM UTC 24 | 320431543 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.3922285461 | Aug 28 09:25:45 PM UTC 24 | Aug 28 09:26:00 PM UTC 24 | 1512887034 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.157614285 | Aug 28 09:25:53 PM UTC 24 | Aug 28 09:26:03 PM UTC 24 | 311586142 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.3530474603 | Aug 28 09:25:54 PM UTC 24 | Aug 28 09:26:04 PM UTC 24 | 140814176 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1468165234 | Aug 28 09:25:50 PM UTC 24 | Aug 28 09:26:06 PM UTC 24 | 999186828 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.192350606 | Aug 28 09:26:01 PM UTC 24 | Aug 28 09:26:08 PM UTC 24 | 519407433 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.2952368207 | Aug 28 09:25:57 PM UTC 24 | Aug 28 09:26:09 PM UTC 24 | 669435272 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.3955782298 | Aug 28 09:25:53 PM UTC 24 | Aug 28 09:26:10 PM UTC 24 | 213137477 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.3726209458 | Aug 28 09:25:18 PM UTC 24 | Aug 28 09:26:11 PM UTC 24 | 688108739 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.1933335282 | Aug 28 09:25:46 PM UTC 24 | Aug 28 09:26:13 PM UTC 24 | 2301238051 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.2910407142 | Aug 28 09:26:02 PM UTC 24 | Aug 28 09:26:14 PM UTC 24 | 2042784147 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.2820126617 | Aug 28 09:26:05 PM UTC 24 | Aug 28 09:26:14 PM UTC 24 | 476853364 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2417979122 | Aug 28 09:26:09 PM UTC 24 | Aug 28 09:26:16 PM UTC 24 | 253126710 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3383596789 | Aug 28 09:25:26 PM UTC 24 | Aug 28 09:26:19 PM UTC 24 | 1491389367 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.2026800302 | Aug 28 09:26:14 PM UTC 24 | Aug 28 09:26:21 PM UTC 24 | 274597789 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.3396848333 | Aug 28 09:26:10 PM UTC 24 | Aug 28 09:26:21 PM UTC 24 | 1001703004 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3206855813 | Aug 28 09:26:17 PM UTC 24 | Aug 28 09:26:24 PM UTC 24 | 497935296 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1335725917 | Aug 28 09:26:09 PM UTC 24 | Aug 28 09:26:24 PM UTC 24 | 1131959124 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.3769593008 | Aug 28 09:26:20 PM UTC 24 | Aug 28 09:26:27 PM UTC 24 | 587033269 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3409437339 | Aug 28 09:26:15 PM UTC 24 | Aug 28 09:26:31 PM UTC 24 | 168753921 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.908791701 | Aug 28 09:26:04 PM UTC 24 | Aug 28 09:26:31 PM UTC 24 | 1795913886 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3615572021 | Aug 28 09:26:22 PM UTC 24 | Aug 28 09:26:32 PM UTC 24 | 518992287 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2637347853 | Aug 28 09:26:27 PM UTC 24 | Aug 28 09:26:36 PM UTC 24 | 126539453 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.4292358593 | Aug 28 09:26:31 PM UTC 24 | Aug 28 09:26:38 PM UTC 24 | 191696374 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1456158000 | Aug 28 09:26:25 PM UTC 24 | Aug 28 09:26:41 PM UTC 24 | 2275593041 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.2240131812 | Aug 28 09:25:36 PM UTC 24 | Aug 28 09:26:42 PM UTC 24 | 726505854 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.1576280137 | Aug 28 09:26:22 PM UTC 24 | Aug 28 09:26:43 PM UTC 24 | 205103306 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3748798240 | Aug 28 09:26:13 PM UTC 24 | Aug 28 09:26:44 PM UTC 24 | 420131712 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.2431195310 | Aug 28 09:26:42 PM UTC 24 | Aug 28 09:26:47 PM UTC 24 | 519523013 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.142769465 | Aug 28 09:26:37 PM UTC 24 | Aug 28 09:26:52 PM UTC 24 | 2771997501 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.2460293247 | Aug 28 09:26:43 PM UTC 24 | Aug 28 09:26:53 PM UTC 24 | 146809661 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.1105305581 | Aug 28 09:26:31 PM UTC 24 | Aug 28 09:26:53 PM UTC 24 | 1210285022 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.3129864415 | Aug 28 09:26:48 PM UTC 24 | Aug 28 09:26:55 PM UTC 24 | 482471709 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.122046996 | Aug 28 09:26:45 PM UTC 24 | Aug 28 09:26:57 PM UTC 24 | 351472620 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.2041204691 | Aug 28 09:26:52 PM UTC 24 | Aug 28 09:27:02 PM UTC 24 | 550667776 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3725676666 | Aug 28 09:26:42 PM UTC 24 | Aug 28 09:27:03 PM UTC 24 | 620749031 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.102113588 | Aug 28 09:26:56 PM UTC 24 | Aug 28 09:27:04 PM UTC 24 | 334343012 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3490125418 | Aug 28 09:25:15 PM UTC 24 | Aug 28 09:27:05 PM UTC 24 | 2069162466 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.241224377 | Aug 28 09:26:57 PM UTC 24 | Aug 28 09:27:05 PM UTC 24 | 461215426 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.2152073035 | Aug 28 09:26:58 PM UTC 24 | Aug 28 09:27:07 PM UTC 24 | 133123525 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1454244378 | Aug 28 09:27:04 PM UTC 24 | Aug 28 09:27:10 PM UTC 24 | 417122538 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3567130683 | Aug 28 09:26:53 PM UTC 24 | Aug 28 09:27:10 PM UTC 24 | 1039618934 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.1914516018 | Aug 28 09:26:48 PM UTC 24 | Aug 28 09:27:12 PM UTC 24 | 4073684356 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1518640649 | Aug 28 09:25:26 PM UTC 24 | Aug 28 09:27:13 PM UTC 24 | 4732036797 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2903917576 | Aug 28 09:26:25 PM UTC 24 | Aug 28 09:27:14 PM UTC 24 | 3994668630 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.3459143004 | Aug 28 09:27:06 PM UTC 24 | Aug 28 09:27:17 PM UTC 24 | 97963818 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.3146797940 | Aug 28 09:27:11 PM UTC 24 | Aug 28 09:27:19 PM UTC 24 | 171546791 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.409163517 | Aug 28 09:27:23 PM UTC 24 | Aug 28 09:27:33 PM UTC 24 | 659541627 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.178254865 | Aug 28 09:27:03 PM UTC 24 | Aug 28 09:27:20 PM UTC 24 | 250898628 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.641213559 | Aug 28 09:27:13 PM UTC 24 | Aug 28 09:27:22 PM UTC 24 | 96366290 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.528305002 | Aug 28 09:27:05 PM UTC 24 | Aug 28 09:27:24 PM UTC 24 | 1822670540 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.887683235 | Aug 28 09:27:21 PM UTC 24 | Aug 28 09:27:28 PM UTC 24 | 130250327 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3697112225 | Aug 28 09:27:12 PM UTC 24 | Aug 28 09:27:28 PM UTC 24 | 547404256 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.3832848785 | Aug 28 09:25:45 PM UTC 24 | Aug 28 09:27:33 PM UTC 24 | 3091244139 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2887921357 | Aug 28 09:25:48 PM UTC 24 | Aug 28 09:27:33 PM UTC 24 | 1478906641 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.1011623788 | Aug 28 09:27:18 PM UTC 24 | Aug 28 09:27:33 PM UTC 24 | 694175325 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.2692081423 | Aug 28 09:27:08 PM UTC 24 | Aug 28 09:27:33 PM UTC 24 | 1009525541 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.1768640516 | Aug 28 09:27:33 PM UTC 24 | Aug 28 09:27:41 PM UTC 24 | 1565032371 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.1464167693 | Aug 28 09:25:27 PM UTC 24 | Aug 28 09:27:43 PM UTC 24 | 395006654 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.995585342 | Aug 28 09:27:34 PM UTC 24 | Aug 28 09:27:44 PM UTC 24 | 374632289 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.2555005968 | Aug 28 09:27:29 PM UTC 24 | Aug 28 09:27:44 PM UTC 24 | 498483088 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.2044648556 | Aug 28 09:27:21 PM UTC 24 | Aug 28 09:27:45 PM UTC 24 | 277714800 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.156793676 | Aug 28 09:25:16 PM UTC 24 | Aug 28 09:27:49 PM UTC 24 | 947704808 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1255627127 | Aug 28 09:27:34 PM UTC 24 | Aug 28 09:27:49 PM UTC 24 | 1088704409 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.534160871 | Aug 28 09:26:39 PM UTC 24 | Aug 28 09:27:52 PM UTC 24 | 1434597591 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.2305641534 | Aug 28 09:27:43 PM UTC 24 | Aug 28 09:27:52 PM UTC 24 | 693064298 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.3198558707 | Aug 28 09:27:45 PM UTC 24 | Aug 28 09:27:52 PM UTC 24 | 272539929 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1811196480 | Aug 28 09:27:34 PM UTC 24 | Aug 28 09:27:57 PM UTC 24 | 445123218 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.1924712552 | Aug 28 09:27:53 PM UTC 24 | Aug 28 09:28:00 PM UTC 24 | 89224102 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.735805512 | Aug 28 09:27:53 PM UTC 24 | Aug 28 09:28:02 PM UTC 24 | 393898848 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.1030907730 | Aug 28 09:27:50 PM UTC 24 | Aug 28 09:28:06 PM UTC 24 | 1656227595 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3163223931 | Aug 28 09:27:44 PM UTC 24 | Aug 28 09:28:11 PM UTC 24 | 590696298 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.519739736 | Aug 28 09:27:53 PM UTC 24 | Aug 28 09:28:13 PM UTC 24 | 515845322 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.1786724699 | Aug 28 09:28:06 PM UTC 24 | Aug 28 09:28:14 PM UTC 24 | 692910655 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.549719754 | Aug 28 09:25:44 PM UTC 24 | Aug 28 09:28:17 PM UTC 24 | 6376858652 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.3913280300 | Aug 28 09:28:01 PM UTC 24 | Aug 28 09:28:19 PM UTC 24 | 260748121 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1240281979 | Aug 28 09:25:18 PM UTC 24 | Aug 28 09:28:22 PM UTC 24 | 2217817621 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3867750757 | Aug 28 09:26:45 PM UTC 24 | Aug 28 09:28:22 PM UTC 24 | 1836282692 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.1394095785 | Aug 28 09:28:14 PM UTC 24 | Aug 28 09:28:23 PM UTC 24 | 281948421 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1991904250 | Aug 28 09:27:50 PM UTC 24 | Aug 28 09:28:24 PM UTC 24 | 1746502935 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1308227578 | Aug 28 09:26:09 PM UTC 24 | Aug 28 09:28:27 PM UTC 24 | 15657523993 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.1979709178 | Aug 28 09:29:23 PM UTC 24 | Aug 28 09:29:40 PM UTC 24 | 273592844 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1009511494 | Aug 28 09:26:16 PM UTC 24 | Aug 28 09:28:30 PM UTC 24 | 3432854753 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.56046332 | Aug 28 09:28:23 PM UTC 24 | Aug 28 09:28:31 PM UTC 24 | 495152739 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.1873679990 | Aug 28 09:28:17 PM UTC 24 | Aug 28 09:28:32 PM UTC 24 | 263871495 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3074420574 | Aug 28 09:28:24 PM UTC 24 | Aug 28 09:28:34 PM UTC 24 | 145246444 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2328087454 | Aug 28 09:28:12 PM UTC 24 | Aug 28 09:28:35 PM UTC 24 | 1677614502 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.1063192365 | Aug 28 09:28:28 PM UTC 24 | Aug 28 09:28:35 PM UTC 24 | 164770081 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.3351765709 | Aug 28 09:28:28 PM UTC 24 | Aug 28 09:28:41 PM UTC 24 | 262598008 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.832471217 | Aug 28 09:28:32 PM UTC 24 | Aug 28 09:28:42 PM UTC 24 | 193240375 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.21388174 | Aug 28 09:28:36 PM UTC 24 | Aug 28 09:28:44 PM UTC 24 | 336167758 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1088175904 | Aug 28 09:27:20 PM UTC 24 | Aug 28 09:28:45 PM UTC 24 | 6951811696 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.1872319401 | Aug 28 09:28:35 PM UTC 24 | Aug 28 09:28:53 PM UTC 24 | 258664173 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3013499174 | Aug 28 09:28:43 PM UTC 24 | Aug 28 09:28:53 PM UTC 24 | 1339958067 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1118087175 | Aug 28 09:28:46 PM UTC 24 | Aug 28 09:28:56 PM UTC 24 | 175509480 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.1962012980 | Aug 28 09:28:31 PM UTC 24 | Aug 28 09:28:59 PM UTC 24 | 297989271 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3076477934 | Aug 28 09:28:54 PM UTC 24 | Aug 28 09:29:01 PM UTC 24 | 171339206 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1721847052 | Aug 28 09:26:44 PM UTC 24 | Aug 28 09:29:01 PM UTC 24 | 4504430599 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3219804199 | Aug 28 09:25:45 PM UTC 24 | Aug 28 09:29:03 PM UTC 24 | 10862907645 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3546732220 | Aug 28 09:27:11 PM UTC 24 | Aug 28 09:29:05 PM UTC 24 | 7006617859 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1363797245 | Aug 28 09:26:52 PM UTC 24 | Aug 28 09:29:06 PM UTC 24 | 4703166803 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3770627995 | Aug 28 09:25:18 PM UTC 24 | Aug 28 09:29:09 PM UTC 24 | 6264496569 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.1614692534 | Aug 28 09:28:42 PM UTC 24 | Aug 28 09:29:10 PM UTC 24 | 292817938 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.375916898 | Aug 28 09:25:51 PM UTC 24 | Aug 28 09:29:10 PM UTC 24 | 13909579273 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.3954659835 | Aug 28 09:29:02 PM UTC 24 | Aug 28 09:29:10 PM UTC 24 | 587867984 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3064743964 | Aug 28 09:26:33 PM UTC 24 | Aug 28 09:29:11 PM UTC 24 | 3357097282 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.3596095103 | Aug 28 09:28:57 PM UTC 24 | Aug 28 09:29:11 PM UTC 24 | 1022693716 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.728350989 | Aug 28 09:26:07 PM UTC 24 | Aug 28 09:29:12 PM UTC 24 | 11613288695 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1338817632 | Aug 28 09:25:33 PM UTC 24 | Aug 28 09:29:13 PM UTC 24 | 6944223946 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.2919788579 | Aug 28 09:29:02 PM UTC 24 | Aug 28 09:29:14 PM UTC 24 | 544561461 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.3906162151 | Aug 28 09:29:03 PM UTC 24 | Aug 28 09:29:15 PM UTC 24 | 527833573 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.170003004 | Aug 28 09:28:24 PM UTC 24 | Aug 28 09:29:15 PM UTC 24 | 4224052592 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.1065722845 | Aug 28 09:29:00 PM UTC 24 | Aug 28 09:29:16 PM UTC 24 | 168524634 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.1496401555 | Aug 28 09:29:07 PM UTC 24 | Aug 28 09:29:20 PM UTC 24 | 1559674592 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3109241819 | Aug 28 09:29:13 PM UTC 24 | Aug 28 09:29:20 PM UTC 24 | 929127721 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1675951785 | Aug 28 09:29:12 PM UTC 24 | Aug 28 09:29:21 PM UTC 24 | 371556292 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3271330572 | Aug 28 09:29:11 PM UTC 24 | Aug 28 09:29:22 PM UTC 24 | 2047624634 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3172664970 | Aug 28 09:27:46 PM UTC 24 | Aug 28 09:29:26 PM UTC 24 | 7621900122 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.1522545687 | Aug 28 09:29:12 PM UTC 24 | Aug 28 09:29:26 PM UTC 24 | 335644973 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3123252285 | Aug 28 09:29:20 PM UTC 24 | Aug 28 09:29:28 PM UTC 24 | 349200476 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.1937700587 | Aug 28 09:28:57 PM UTC 24 | Aug 28 09:29:28 PM UTC 24 | 4563048289 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.2527279944 | Aug 28 09:29:12 PM UTC 24 | Aug 28 09:29:29 PM UTC 24 | 2777096413 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.2533135432 | Aug 28 09:29:15 PM UTC 24 | Aug 28 09:29:30 PM UTC 24 | 2086414441 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.4189732474 | Aug 28 09:29:16 PM UTC 24 | Aug 28 09:29:32 PM UTC 24 | 694987944 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.4229200537 | Aug 28 09:28:20 PM UTC 24 | Aug 28 09:29:34 PM UTC 24 | 2499699745 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1489405520 | Aug 28 09:29:22 PM UTC 24 | Aug 28 09:29:36 PM UTC 24 | 526377106 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.230784419 | Aug 28 09:25:56 PM UTC 24 | Aug 28 09:29:36 PM UTC 24 | 25199289641 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1157429178 | Aug 28 09:26:54 PM UTC 24 | Aug 28 09:29:37 PM UTC 24 | 4403518481 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.238345774 | Aug 28 09:27:34 PM UTC 24 | Aug 28 09:29:37 PM UTC 24 | 2043559763 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.674490079 | Aug 28 09:29:27 PM UTC 24 | Aug 28 09:29:39 PM UTC 24 | 495420447 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2344183101 | Aug 28 09:26:25 PM UTC 24 | Aug 28 09:29:39 PM UTC 24 | 10723184742 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.2856077321 | Aug 28 09:29:29 PM UTC 24 | Aug 28 09:29:39 PM UTC 24 | 337501901 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.3725792020 | Aug 28 09:29:14 PM UTC 24 | Aug 28 09:29:41 PM UTC 24 | 311518159 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.660657717 | Aug 28 09:29:34 PM UTC 24 | Aug 28 09:29:43 PM UTC 24 | 133001359 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3675031182 | Aug 28 09:29:30 PM UTC 24 | Aug 28 09:29:46 PM UTC 24 | 340822009 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3436265821 | Aug 28 09:29:21 PM UTC 24 | Aug 28 09:29:46 PM UTC 24 | 879264181 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.503310139 | Aug 28 09:25:15 PM UTC 24 | Aug 28 09:29:47 PM UTC 24 | 55197352698 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.852960346 | Aug 28 09:29:40 PM UTC 24 | Aug 28 09:29:48 PM UTC 24 | 132277749 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.3798475690 | Aug 28 09:29:37 PM UTC 24 | Aug 28 09:29:48 PM UTC 24 | 143178159 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.4007783499 | Aug 28 09:29:29 PM UTC 24 | Aug 28 09:29:48 PM UTC 24 | 851511637 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2929258913 | Aug 28 09:27:42 PM UTC 24 | Aug 28 09:29:50 PM UTC 24 | 3165017989 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4194189694 | Aug 28 09:27:06 PM UTC 24 | Aug 28 09:29:50 PM UTC 24 | 2657327779 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.1167009574 | Aug 28 09:29:41 PM UTC 24 | Aug 28 09:29:50 PM UTC 24 | 357135144 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1252793888 | Aug 28 09:27:29 PM UTC 24 | Aug 28 09:29:55 PM UTC 24 | 3412904308 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1517926537 | Aug 28 09:27:58 PM UTC 24 | Aug 28 09:29:55 PM UTC 24 | 1840066651 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.1670566693 | Aug 28 09:29:47 PM UTC 24 | Aug 28 09:29:55 PM UTC 24 | 130199648 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.2288041725 | Aug 28 09:29:38 PM UTC 24 | Aug 28 09:29:56 PM UTC 24 | 258808676 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1857258524 | Aug 28 09:28:15 PM UTC 24 | Aug 28 09:29:57 PM UTC 24 | 4485302865 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.772374636 | Aug 28 09:29:44 PM UTC 24 | Aug 28 09:29:57 PM UTC 24 | 1082820903 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.295361685 | Aug 28 09:26:15 PM UTC 24 | Aug 28 09:29:58 PM UTC 24 | 3673907066 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.768999848 | Aug 28 09:29:41 PM UTC 24 | Aug 28 09:29:58 PM UTC 24 | 303357410 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3311310247 | Aug 28 09:28:03 PM UTC 24 | Aug 28 09:29:58 PM UTC 24 | 19108875091 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2991478073 | Aug 28 09:29:49 PM UTC 24 | Aug 28 09:29:58 PM UTC 24 | 98182313 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.1757412989 | Aug 28 09:29:50 PM UTC 24 | Aug 28 09:29:59 PM UTC 24 | 128987356 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1677837580 | Aug 28 09:27:25 PM UTC 24 | Aug 28 09:29:59 PM UTC 24 | 2971071364 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.2553681247 | Aug 28 09:29:51 PM UTC 24 | Aug 28 09:30:02 PM UTC 24 | 144937892 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3342325502 | Aug 28 09:29:36 PM UTC 24 | Aug 28 09:30:03 PM UTC 24 | 11215135244 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.882685088 | Aug 28 09:29:56 PM UTC 24 | Aug 28 09:30:03 PM UTC 24 | 193251600 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1498144903 | Aug 28 09:27:02 PM UTC 24 | Aug 28 09:30:03 PM UTC 24 | 3063317466 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.2454793001 | Aug 28 09:29:49 PM UTC 24 | Aug 28 09:30:04 PM UTC 24 | 175591253 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2686315056 | Aug 28 09:29:58 PM UTC 24 | Aug 28 09:30:04 PM UTC 24 | 365054653 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.4010305124 | Aug 28 09:30:00 PM UTC 24 | Aug 28 09:30:08 PM UTC 24 | 692246224 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.401135693 | Aug 28 09:29:59 PM UTC 24 | Aug 28 09:30:09 PM UTC 24 | 277948996 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3593372346 | Aug 28 09:30:02 PM UTC 24 | Aug 28 09:30:09 PM UTC 24 | 277977429 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.78254308 | Aug 28 09:30:00 PM UTC 24 | Aug 28 09:30:09 PM UTC 24 | 293451111 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1079888084 | Aug 28 09:27:14 PM UTC 24 | Aug 28 09:30:10 PM UTC 24 | 34581103341 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1549178880 | Aug 28 09:28:25 PM UTC 24 | Aug 28 09:30:11 PM UTC 24 | 7914851198 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2256823634 | Aug 28 09:29:59 PM UTC 24 | Aug 28 09:30:11 PM UTC 24 | 1317030882 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.1286944236 | Aug 28 09:30:04 PM UTC 24 | Aug 28 09:30:12 PM UTC 24 | 347531931 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.691926463 | Aug 28 09:30:06 PM UTC 24 | Aug 28 09:30:13 PM UTC 24 | 97483833 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3828144291 | Aug 28 09:26:01 PM UTC 24 | Aug 28 09:30:13 PM UTC 24 | 6366671977 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2174558229 | Aug 28 09:28:54 PM UTC 24 | Aug 28 09:30:17 PM UTC 24 | 7507919135 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1920862350 | Aug 28 09:30:11 PM UTC 24 | Aug 28 09:30:18 PM UTC 24 | 175209272 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2527633302 | Aug 28 09:29:48 PM UTC 24 | Aug 28 09:30:18 PM UTC 24 | 429246980 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.3720796536 | Aug 28 09:30:03 PM UTC 24 | Aug 28 09:30:19 PM UTC 24 | 645377088 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.1421164369 | Aug 28 09:29:57 PM UTC 24 | Aug 28 09:30:20 PM UTC 24 | 987811023 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.791986766 | Aug 28 09:28:33 PM UTC 24 | Aug 28 09:30:20 PM UTC 24 | 9970940719 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2421314848 | Aug 28 09:30:11 PM UTC 24 | Aug 28 09:30:22 PM UTC 24 | 2096008695 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.3613312106 | Aug 28 09:30:12 PM UTC 24 | Aug 28 09:30:23 PM UTC 24 | 485076529 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.2873908437 | Aug 28 09:30:14 PM UTC 24 | Aug 28 09:30:23 PM UTC 24 | 132170088 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.3050477706 | Aug 28 09:30:10 PM UTC 24 | Aug 28 09:30:25 PM UTC 24 | 691937918 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1754519659 | Aug 28 09:29:10 PM UTC 24 | Aug 28 09:30:27 PM UTC 24 | 6520657516 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.1223225662 | Aug 28 09:30:18 PM UTC 24 | Aug 28 09:30:27 PM UTC 24 | 143607633 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1815416057 | Aug 28 09:29:58 PM UTC 24 | Aug 28 09:30:28 PM UTC 24 | 413080885 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.549506860 | Aug 28 09:30:22 PM UTC 24 | Aug 28 09:30:30 PM UTC 24 | 133252293 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2516966736 | Aug 28 09:30:13 PM UTC 24 | Aug 28 09:30:31 PM UTC 24 | 428816552 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.399480714 | Aug 28 09:30:24 PM UTC 24 | Aug 28 09:30:33 PM UTC 24 | 1793739306 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1939294942 | Aug 28 09:30:06 PM UTC 24 | Aug 28 09:30:35 PM UTC 24 | 396644214 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.459092285 | Aug 28 09:30:28 PM UTC 24 | Aug 28 09:30:35 PM UTC 24 | 88213256 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2351436769 | Aug 28 09:30:19 PM UTC 24 | Aug 28 09:30:37 PM UTC 24 | 250585651 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2855038786 | Aug 28 09:29:12 PM UTC 24 | Aug 28 09:30:37 PM UTC 24 | 2251934042 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.261420187 | Aug 28 09:30:17 PM UTC 24 | Aug 28 09:30:39 PM UTC 24 | 308539194 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.3989055465 | Aug 28 09:30:26 PM UTC 24 | Aug 28 09:30:39 PM UTC 24 | 492641297 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2814551396 | Aug 28 09:29:01 PM UTC 24 | Aug 28 09:30:39 PM UTC 24 | 8637270685 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.436161989 | Aug 28 09:30:31 PM UTC 24 | Aug 28 09:30:41 PM UTC 24 | 143418356 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.3457103387 | Aug 28 09:30:35 PM UTC 24 | Aug 28 09:30:43 PM UTC 24 | 1035969593 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3501670406 | Aug 28 09:28:45 PM UTC 24 | Aug 28 09:30:44 PM UTC 24 | 13613518091 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.887260821 | Aug 28 09:30:23 PM UTC 24 | Aug 28 09:30:44 PM UTC 24 | 274576423 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2378994335 | Aug 28 09:29:05 PM UTC 24 | Aug 28 09:30:45 PM UTC 24 | 14443665127 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.3279160069 | Aug 28 09:30:32 PM UTC 24 | Aug 28 09:30:47 PM UTC 24 | 251076595 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.1094154123 | Aug 28 09:30:40 PM UTC 24 | Aug 28 09:30:48 PM UTC 24 | 655064130 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.395998385 | Aug 28 09:30:38 PM UTC 24 | Aug 28 09:30:48 PM UTC 24 | 586987614 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.1927642393 | Aug 28 09:30:48 PM UTC 24 | Aug 28 09:30:56 PM UTC 24 | 570839373 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2835533253 | Aug 28 09:30:29 PM UTC 24 | Aug 28 09:30:50 PM UTC 24 | 566028045 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2810681286 | Aug 28 09:29:33 PM UTC 24 | Aug 28 09:30:50 PM UTC 24 | 1795149716 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.4191008292 | Aug 28 09:30:40 PM UTC 24 | Aug 28 09:30:51 PM UTC 24 | 695627385 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.2463125560 | Aug 28 09:30:44 PM UTC 24 | Aug 28 09:30:54 PM UTC 24 | 168010780 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.3126577480 | Aug 28 09:30:49 PM UTC 24 | Aug 28 09:30:59 PM UTC 24 | 399279341 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1677647938 | Aug 28 09:28:28 PM UTC 24 | Aug 28 09:31:00 PM UTC 24 | 3823801343 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.682286657 | Aug 28 09:30:36 PM UTC 24 | Aug 28 09:31:00 PM UTC 24 | 278326421 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.3667603787 | Aug 28 09:30:53 PM UTC 24 | Aug 28 09:31:01 PM UTC 24 | 1127938221 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.585013372 | Aug 28 09:30:48 PM UTC 24 | Aug 28 09:31:01 PM UTC 24 | 217402011 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3424237367 | Aug 28 09:30:45 PM UTC 24 | Aug 28 09:31:03 PM UTC 24 | 258634104 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.3772240366 | Aug 28 09:30:42 PM UTC 24 | Aug 28 09:31:05 PM UTC 24 | 1138216973 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1081914495 | Aug 28 09:30:56 PM UTC 24 | Aug 28 09:31:05 PM UTC 24 | 101217263 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3848221870 | Aug 28 09:30:58 PM UTC 24 | Aug 28 09:31:07 PM UTC 24 | 396502079 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.702830235 | Aug 28 09:30:50 PM UTC 24 | Aug 28 09:31:07 PM UTC 24 | 1131987419 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3647331777 | Aug 28 09:28:59 PM UTC 24 | Aug 28 09:31:09 PM UTC 24 | 10811412083 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1308796815 | Aug 28 09:31:02 PM UTC 24 | Aug 28 09:31:09 PM UTC 24 | 347788807 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.891493949 | Aug 28 09:29:47 PM UTC 24 | Aug 28 09:31:11 PM UTC 24 | 7120566825 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.3963020189 | Aug 28 09:31:04 PM UTC 24 | Aug 28 09:31:13 PM UTC 24 | 149403631 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1857424772 | Aug 28 09:30:03 PM UTC 24 | Aug 28 09:31:16 PM UTC 24 | 1539049996 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.2314017966 | Aug 28 09:31:08 PM UTC 24 | Aug 28 09:31:17 PM UTC 24 | 129502119 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.1549058097 | Aug 28 09:31:01 PM UTC 24 | Aug 28 09:31:19 PM UTC 24 | 3110283217 ps |
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