| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.51 | 96.89 | 92.28 | 97.67 | 100.00 | 98.62 | 98.05 | 99.06 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 63.53 | 63.53 | 92.11 | 92.11 | 73.46 | 73.46 | 46.30 | 46.30 | 40.00 | 40.00 | 88.97 | 88.97 | 93.55 | 93.55 | 10.30 | 10.30 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.1113864701 |
| 80.66 | 17.13 | 92.46 | 0.36 | 80.34 | 6.88 | 80.58 | 34.27 | 40.00 | 0.00 | 90.69 | 1.72 | 95.05 | 1.50 | 85.48 | 75.18 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1885650388 |
| 86.34 | 5.69 | 92.46 | 0.00 | 83.15 | 2.81 | 83.50 | 2.92 | 73.33 | 33.33 | 91.03 | 0.34 | 95.20 | 0.15 | 85.71 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.781620416 |
| 90.48 | 4.14 | 93.42 | 0.96 | 84.55 | 1.40 | 91.60 | 8.10 | 86.67 | 13.33 | 94.14 | 3.10 | 95.65 | 0.45 | 87.35 | 1.64 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3319114261 |
| 91.94 | 1.46 | 96.41 | 2.99 | 88.06 | 3.51 | 92.22 | 0.62 | 86.67 | 0.00 | 96.21 | 2.07 | 95.95 | 0.30 | 88.06 | 0.70 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1801285796 |
| 93.31 | 1.37 | 96.53 | 0.12 | 88.20 | 0.14 | 94.33 | 2.10 | 93.33 | 6.67 | 96.55 | 0.34 | 95.95 | 0.00 | 88.29 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4243172129 |
| 94.36 | 1.05 | 96.77 | 0.24 | 88.90 | 0.70 | 94.33 | 0.00 | 93.33 | 0.00 | 97.59 | 1.03 | 95.95 | 0.00 | 93.68 | 5.39 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.470172255 |
| 95.40 | 1.03 | 96.77 | 0.00 | 88.90 | 0.00 | 94.42 | 0.10 | 100.00 | 6.67 | 97.59 | 0.00 | 95.95 | 0.00 | 94.15 | 0.47 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1597078009 |
| 96.04 | 0.64 | 96.77 | 0.00 | 91.01 | 2.11 | 95.95 | 1.52 | 100.00 | 0.00 | 97.59 | 0.00 | 96.10 | 0.15 | 94.85 | 0.70 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.3990640754 |
| 96.30 | 0.26 | 96.77 | 0.00 | 91.57 | 0.56 | 96.22 | 0.28 | 100.00 | 0.00 | 97.59 | 0.00 | 96.40 | 0.30 | 95.55 | 0.70 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.4200927641 |
| 96.55 | 0.25 | 96.77 | 0.00 | 91.71 | 0.14 | 97.15 | 0.93 | 100.00 | 0.00 | 97.59 | 0.00 | 96.40 | 0.00 | 96.25 | 0.70 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.443278938 |
| 96.72 | 0.17 | 96.77 | 0.00 | 91.85 | 0.14 | 97.15 | 0.00 | 100.00 | 0.00 | 97.59 | 0.00 | 97.45 | 1.05 | 96.25 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1843193399 |
| 96.89 | 0.17 | 96.77 | 0.00 | 91.85 | 0.00 | 97.15 | 0.00 | 100.00 | 0.00 | 97.59 | 0.00 | 97.45 | 0.00 | 97.42 | 1.17 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2728614557 |
| 97.03 | 0.14 | 96.89 | 0.12 | 91.85 | 0.00 | 97.25 | 0.10 | 100.00 | 0.00 | 97.93 | 0.34 | 97.60 | 0.15 | 97.66 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1009989668 |
| 97.11 | 0.08 | 96.89 | 0.00 | 91.99 | 0.14 | 97.35 | 0.10 | 100.00 | 0.00 | 98.28 | 0.34 | 97.60 | 0.00 | 97.66 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2426605714 |
| 97.19 | 0.08 | 96.89 | 0.00 | 92.13 | 0.14 | 97.40 | 0.05 | 100.00 | 0.00 | 98.62 | 0.34 | 97.60 | 0.00 | 97.66 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.3426565621 |
| 97.25 | 0.07 | 96.89 | 0.00 | 92.13 | 0.00 | 97.40 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.60 | 0.00 | 98.13 | 0.47 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3668883249 |
| 97.30 | 0.04 | 96.89 | 0.00 | 92.13 | 0.00 | 97.40 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.30 | 98.13 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2623268818 |
| 97.33 | 0.03 | 96.89 | 0.00 | 92.13 | 0.00 | 97.40 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.00 | 98.36 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2608163238 |
| 97.36 | 0.03 | 96.89 | 0.00 | 92.13 | 0.00 | 97.40 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.00 | 98.59 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1708515590 |
| 97.40 | 0.03 | 96.89 | 0.00 | 92.13 | 0.00 | 97.40 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.00 | 98.83 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1198010033 |
| 97.43 | 0.03 | 96.89 | 0.00 | 92.13 | 0.00 | 97.40 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.00 | 99.06 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3018715684 |
| 97.46 | 0.03 | 96.89 | 0.00 | 92.13 | 0.00 | 97.60 | 0.20 | 100.00 | 0.00 | 98.62 | 0.00 | 97.90 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3183620473 |
| 97.48 | 0.02 | 96.89 | 0.00 | 92.13 | 0.00 | 97.60 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 98.05 | 0.15 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.2306016216 |
| 97.50 | 0.02 | 96.89 | 0.00 | 92.28 | 0.14 | 97.60 | 0.00 | 100.00 | 0.00 | 98.62 | 0.00 | 98.05 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.82927271 |
| 97.51 | 0.01 | 96.89 | 0.00 | 92.28 | 0.00 | 97.65 | 0.05 | 100.00 | 0.00 | 98.62 | 0.00 | 98.05 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.4199381698 |
| 97.51 | 0.01 | 96.89 | 0.00 | 92.28 | 0.00 | 97.67 | 0.03 | 100.00 | 0.00 | 98.62 | 0.00 | 98.05 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.2397813197 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.352546267 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3390125253 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3088782560 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2900355262 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2135802066 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1881033513 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2624399393 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1463915198 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1860598726 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1257733123 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.978785420 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2091234502 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3599244596 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3888664286 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2399675735 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1917854419 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1595327690 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1733901909 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2159396404 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2309200403 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2881615362 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1182200070 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2646515866 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3337352488 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2723599343 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.131289503 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2571960718 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.873907258 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3613273426 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.637871318 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4068554923 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3432307260 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.257844025 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1587337350 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4018659273 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1215926628 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4001960769 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3229674466 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2090724810 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1772516169 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3443074506 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1276222822 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.209828309 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1630174220 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1392019480 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2867706947 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3694872472 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.744862843 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1303843671 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1395039938 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.932340754 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2608891402 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4092836722 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1527433714 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1275491073 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1388782207 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1200419703 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1592762053 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1535856248 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4153102715 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1993100316 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2799568275 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3817859253 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2460550911 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.279049753 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1496146670 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3426177175 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.273194409 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2021588021 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.609254272 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2803034574 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1234826777 |
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| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3923007504 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.1546839488 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1961459650 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.4277284706 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.2876272501 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.4059906944 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1189582904 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3879243751 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2637581054 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.4179006530 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1291232921 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.2775652399 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.2002906536 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2444030885 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.445213651 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.2359435749 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.2596933370 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2643341267 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.3017799654 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.719488200 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.1583723508 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.952651211 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.2550439864 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.4061058622 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1226389092 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2903237119 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2762529249 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.1067218450 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.4241332901 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1123106855 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.3191659493 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1798594993 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.155390968 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.4071198389 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.797781807 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1815629847 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.1074798023 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2421498614 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.3837772235 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.4162169113 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.2011003492 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1710001336 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1597301008 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3997339180 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.712259599 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.3353345042 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.2254828281 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1498195058 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1651774706 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2414593084 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.2436827848 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.1472866077 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.759017350 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.4251453939 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.926014756 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1955789373 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.3711062075 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.1010959943 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.1427528079 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3846059160 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.625398772 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1503855109 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1900907281 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1584779432 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.1082796800 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2793258357 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2997505427 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2206977043 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.2197133726 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2807542795 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.3865463165 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.2759116473 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.1902220013 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.2267957916 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1334076772 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3930076790 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2004129344 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.640883554 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.2416019975 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1403972118 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3151106431 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1475218092 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.3678888626 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1274818156 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2069907152 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3123216785 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2109893530 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3179282609 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.966882924 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.2453556862 |
| /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3768813344 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.151215258 | Sep 09 07:18:10 AM UTC 24 | Sep 09 07:18:20 AM UTC 24 | 103766587 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1009989668 | Sep 09 07:18:13 AM UTC 24 | Sep 09 07:18:25 AM UTC 24 | 2098439372 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.866575162 | Sep 09 07:18:11 AM UTC 24 | Sep 09 07:18:27 AM UTC 24 | 164192786 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.2397813197 | Sep 09 07:18:21 AM UTC 24 | Sep 09 07:18:29 AM UTC 24 | 131966642 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.3169354012 | Sep 09 07:18:14 AM UTC 24 | Sep 09 07:18:30 AM UTC 24 | 176525453 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.1113864701 | Sep 09 07:18:22 AM UTC 24 | Sep 09 07:18:31 AM UTC 24 | 139527574 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.613088841 | Sep 09 07:18:24 AM UTC 24 | Sep 09 07:18:35 AM UTC 24 | 541231288 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.2429409286 | Sep 09 07:18:30 AM UTC 24 | Sep 09 07:18:38 AM UTC 24 | 285448643 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1326230287 | Sep 09 07:18:23 AM UTC 24 | Sep 09 07:18:40 AM UTC 24 | 806024112 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.2394940340 | Sep 09 07:18:31 AM UTC 24 | Sep 09 07:18:40 AM UTC 24 | 437327503 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1596930952 | Sep 09 07:18:32 AM UTC 24 | Sep 09 07:18:42 AM UTC 24 | 140961446 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3319114261 | Sep 09 07:18:27 AM UTC 24 | Sep 09 07:18:43 AM UTC 24 | 177381785 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3250533946 | Sep 09 07:18:32 AM UTC 24 | Sep 09 07:18:50 AM UTC 24 | 565117979 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.656909521 | Sep 09 07:18:40 AM UTC 24 | Sep 09 07:18:50 AM UTC 24 | 135644420 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.1713078621 | Sep 09 07:18:41 AM UTC 24 | Sep 09 07:18:51 AM UTC 24 | 97319137 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2426605714 | Sep 09 07:18:35 AM UTC 24 | Sep 09 07:18:51 AM UTC 24 | 335731908 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1801285796 | Sep 09 07:18:40 AM UTC 24 | Sep 09 07:18:52 AM UTC 24 | 768053931 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.2675880813 | Sep 09 07:18:52 AM UTC 24 | Sep 09 07:18:59 AM UTC 24 | 90201574 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.3500941461 | Sep 09 07:18:45 AM UTC 24 | Sep 09 07:18:59 AM UTC 24 | 999804663 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1887305550 | Sep 09 07:18:52 AM UTC 24 | Sep 09 07:19:02 AM UTC 24 | 95364430 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.3990640754 | Sep 09 07:18:40 AM UTC 24 | Sep 09 07:19:02 AM UTC 24 | 1215651191 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3923007504 | Sep 09 07:18:53 AM UTC 24 | Sep 09 07:19:03 AM UTC 24 | 427863465 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.3951972693 | Sep 09 07:18:56 AM UTC 24 | Sep 09 07:19:07 AM UTC 24 | 102978488 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.4154433006 | Sep 09 07:19:03 AM UTC 24 | Sep 09 07:19:12 AM UTC 24 | 127336332 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1584779432 | Sep 09 07:19:06 AM UTC 24 | Sep 09 07:19:13 AM UTC 24 | 367882489 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.1082796800 | Sep 09 07:19:03 AM UTC 24 | Sep 09 07:19:13 AM UTC 24 | 101923329 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.303847376 | Sep 09 07:19:00 AM UTC 24 | Sep 09 07:19:18 AM UTC 24 | 919975730 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.625398772 | Sep 09 07:19:13 AM UTC 24 | Sep 09 07:19:21 AM UTC 24 | 249885215 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.3865463165 | Sep 09 07:19:14 AM UTC 24 | Sep 09 07:19:22 AM UTC 24 | 141744598 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1900907281 | Sep 09 07:19:09 AM UTC 24 | Sep 09 07:19:26 AM UTC 24 | 510965632 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2807542795 | Sep 09 07:19:17 AM UTC 24 | Sep 09 07:19:27 AM UTC 24 | 189508800 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2997505427 | Sep 09 07:19:23 AM UTC 24 | Sep 09 07:19:31 AM UTC 24 | 262788453 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.2197133726 | Sep 09 07:19:20 AM UTC 24 | Sep 09 07:19:31 AM UTC 24 | 692558714 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3930076790 | Sep 09 07:19:24 AM UTC 24 | Sep 09 07:19:33 AM UTC 24 | 93973046 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.443278938 | Sep 09 07:19:03 AM UTC 24 | Sep 09 07:19:35 AM UTC 24 | 4539392913 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1334076772 | Sep 09 07:19:27 AM UTC 24 | Sep 09 07:19:37 AM UTC 24 | 557331070 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.1902220013 | Sep 09 07:19:31 AM UTC 24 | Sep 09 07:19:39 AM UTC 24 | 126571934 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2004129344 | Sep 09 07:19:26 AM UTC 24 | Sep 09 07:19:41 AM UTC 24 | 445795976 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.2759116473 | Sep 09 07:19:14 AM UTC 24 | Sep 09 07:19:41 AM UTC 24 | 1578466956 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.3678888626 | Sep 09 07:19:34 AM UTC 24 | Sep 09 07:19:45 AM UTC 24 | 267914259 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1475218092 | Sep 09 07:19:35 AM UTC 24 | Sep 09 07:19:46 AM UTC 24 | 589354661 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.2267957916 | Sep 09 07:19:30 AM UTC 24 | Sep 09 07:19:48 AM UTC 24 | 520223766 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.2416019975 | Sep 09 07:19:42 AM UTC 24 | Sep 09 07:19:49 AM UTC 24 | 175076911 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.966882924 | Sep 09 07:19:44 AM UTC 24 | Sep 09 07:19:54 AM UTC 24 | 785660630 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3151106431 | Sep 09 07:19:40 AM UTC 24 | Sep 09 07:19:56 AM UTC 24 | 695216572 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2069907152 | Sep 09 07:19:49 AM UTC 24 | Sep 09 07:19:57 AM UTC 24 | 347558918 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3179282609 | Sep 09 07:19:46 AM UTC 24 | Sep 09 07:19:57 AM UTC 24 | 608312544 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3183620473 | Sep 09 07:19:34 AM UTC 24 | Sep 09 07:20:01 AM UTC 24 | 308150689 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1369215354 | Sep 09 07:19:55 AM UTC 24 | Sep 09 07:20:06 AM UTC 24 | 140511830 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2109893530 | Sep 09 07:19:49 AM UTC 24 | Sep 09 07:20:07 AM UTC 24 | 266043878 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.426756855 | Sep 09 07:20:01 AM UTC 24 | Sep 09 07:20:09 AM UTC 24 | 1552899787 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.2714202892 | Sep 09 07:20:18 AM UTC 24 | Sep 09 07:20:36 AM UTC 24 | 2670251523 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.2453556862 | Sep 09 07:19:46 AM UTC 24 | Sep 09 07:20:12 AM UTC 24 | 817561194 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.2586419061 | Sep 09 07:19:57 AM UTC 24 | Sep 09 07:20:14 AM UTC 24 | 1039454301 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4243172129 | Sep 09 07:18:32 AM UTC 24 | Sep 09 07:20:15 AM UTC 24 | 8489606726 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1885650388 | Sep 09 07:18:16 AM UTC 24 | Sep 09 07:20:16 AM UTC 24 | 10338793397 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.3478719613 | Sep 09 07:20:11 AM UTC 24 | Sep 09 07:20:17 AM UTC 24 | 380708861 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.670102823 | Sep 09 07:20:06 AM UTC 24 | Sep 09 07:20:17 AM UTC 24 | 273732016 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2793258357 | Sep 09 07:19:12 AM UTC 24 | Sep 09 07:20:17 AM UTC 24 | 6297267263 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.4134804908 | Sep 09 07:19:53 AM UTC 24 | Sep 09 07:20:22 AM UTC 24 | 2135924899 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.453998056 | Sep 09 07:20:04 AM UTC 24 | Sep 09 07:20:22 AM UTC 24 | 2093156050 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.1615541683 | Sep 09 07:20:13 AM UTC 24 | Sep 09 07:20:23 AM UTC 24 | 194813971 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.781620416 | Sep 09 07:18:26 AM UTC 24 | Sep 09 07:20:24 AM UTC 24 | 8888672450 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.1171498622 | Sep 09 07:20:17 AM UTC 24 | Sep 09 07:20:24 AM UTC 24 | 85737860 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.1569726531 | Sep 09 07:20:13 AM UTC 24 | Sep 09 07:20:26 AM UTC 24 | 126991158 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.2786607024 | Sep 09 07:20:09 AM UTC 24 | Sep 09 07:20:26 AM UTC 24 | 997941848 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.4008896198 | Sep 09 07:20:16 AM UTC 24 | Sep 09 07:20:28 AM UTC 24 | 341225832 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.2518860830 | Sep 09 07:20:18 AM UTC 24 | Sep 09 07:20:28 AM UTC 24 | 183504605 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.4200927641 | Sep 09 07:18:17 AM UTC 24 | Sep 09 07:20:30 AM UTC 24 | 485651672 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.4194446381 | Sep 09 07:18:29 AM UTC 24 | Sep 09 07:20:36 AM UTC 24 | 782294728 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.578337073 | Sep 09 07:20:25 AM UTC 24 | Sep 09 07:20:37 AM UTC 24 | 515842487 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.3822506132 | Sep 09 07:20:23 AM UTC 24 | Sep 09 07:20:37 AM UTC 24 | 279287586 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.758416801 | Sep 09 07:18:13 AM UTC 24 | Sep 09 07:20:37 AM UTC 24 | 8732089027 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.2661743970 | Sep 09 07:20:27 AM UTC 24 | Sep 09 07:20:37 AM UTC 24 | 273959270 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.553665112 | Sep 09 07:20:30 AM UTC 24 | Sep 09 07:20:38 AM UTC 24 | 127403139 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.2847601910 | Sep 09 07:20:32 AM UTC 24 | Sep 09 07:20:40 AM UTC 24 | 542506601 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.4199381698 | Sep 09 07:20:28 AM UTC 24 | Sep 09 07:20:41 AM UTC 24 | 169901119 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.3252354855 | Sep 09 07:20:37 AM UTC 24 | Sep 09 07:20:43 AM UTC 24 | 520372617 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.119577817 | Sep 09 07:20:38 AM UTC 24 | Sep 09 07:20:46 AM UTC 24 | 165687746 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.3758449765 | Sep 09 07:19:02 AM UTC 24 | Sep 09 07:20:48 AM UTC 24 | 798531083 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.2040889124 | Sep 09 07:20:40 AM UTC 24 | Sep 09 07:20:47 AM UTC 24 | 169753296 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.4098015912 | Sep 09 07:20:42 AM UTC 24 | Sep 09 07:20:50 AM UTC 24 | 200633540 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.2962056013 | Sep 09 07:20:31 AM UTC 24 | Sep 09 07:20:51 AM UTC 24 | 437288238 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1379411888 | Sep 09 07:18:56 AM UTC 24 | Sep 09 07:20:51 AM UTC 24 | 1649636518 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1830542891 | Sep 09 07:20:38 AM UTC 24 | Sep 09 07:20:53 AM UTC 24 | 175460533 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3822485225 | Sep 09 07:20:37 AM UTC 24 | Sep 09 07:20:54 AM UTC 24 | 261700041 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.849200295 | Sep 09 07:20:48 AM UTC 24 | Sep 09 07:20:55 AM UTC 24 | 396375221 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.3748918075 | Sep 09 07:20:26 AM UTC 24 | Sep 09 07:20:55 AM UTC 24 | 1064857413 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1803641124 | Sep 09 07:20:41 AM UTC 24 | Sep 09 07:20:55 AM UTC 24 | 222937346 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.424371351 | Sep 09 07:18:52 AM UTC 24 | Sep 09 07:20:58 AM UTC 24 | 588354018 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2047819930 | Sep 09 07:18:40 AM UTC 24 | Sep 09 07:21:00 AM UTC 24 | 2352868168 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.3133534649 | Sep 09 07:20:47 AM UTC 24 | Sep 09 07:21:00 AM UTC 24 | 172764443 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.24766964 | Sep 09 07:20:51 AM UTC 24 | Sep 09 07:21:00 AM UTC 24 | 95362510 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.3358739533 | Sep 09 07:20:55 AM UTC 24 | Sep 09 07:21:01 AM UTC 24 | 500226610 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.4290537555 | Sep 09 07:20:37 AM UTC 24 | Sep 09 07:21:02 AM UTC 24 | 429524611 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.1086696285 | Sep 09 07:20:56 AM UTC 24 | Sep 09 07:21:03 AM UTC 24 | 400730777 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.361742301 | Sep 09 07:20:59 AM UTC 24 | Sep 09 07:21:06 AM UTC 24 | 127527541 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3123216785 | Sep 09 07:19:47 AM UTC 24 | Sep 09 07:21:06 AM UTC 24 | 1109741863 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.2236139364 | Sep 09 07:20:59 AM UTC 24 | Sep 09 07:21:08 AM UTC 24 | 554018105 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.3426565621 | Sep 09 07:20:52 AM UTC 24 | Sep 09 07:21:08 AM UTC 24 | 229402184 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.1763607881 | Sep 09 07:20:49 AM UTC 24 | Sep 09 07:21:09 AM UTC 24 | 1391436615 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2875112940 | Sep 09 07:22:12 AM UTC 24 | Sep 09 07:22:22 AM UTC 24 | 1216744271 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.1486038437 | Sep 09 07:21:02 AM UTC 24 | Sep 09 07:21:09 AM UTC 24 | 85834597 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2875552205 | Sep 09 07:20:56 AM UTC 24 | Sep 09 07:21:10 AM UTC 24 | 662819484 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.1999239869 | Sep 09 07:21:00 AM UTC 24 | Sep 09 07:21:11 AM UTC 24 | 1185488188 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.3546846176 | Sep 09 07:20:56 AM UTC 24 | Sep 09 07:21:11 AM UTC 24 | 251993945 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3232996964 | Sep 09 07:21:05 AM UTC 24 | Sep 09 07:21:13 AM UTC 24 | 96578083 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2632986876 | Sep 09 07:18:43 AM UTC 24 | Sep 09 07:21:15 AM UTC 24 | 3532007792 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.145892783 | Sep 09 07:20:08 AM UTC 24 | Sep 09 07:21:15 AM UTC 24 | 1133905730 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.98425709 | Sep 09 07:21:09 AM UTC 24 | Sep 09 07:21:17 AM UTC 24 | 132604348 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.974767894 | Sep 09 07:20:59 AM UTC 24 | Sep 09 07:21:18 AM UTC 24 | 221970608 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.545434852 | Sep 09 07:21:07 AM UTC 24 | Sep 09 07:21:19 AM UTC 24 | 510242426 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.2502735484 | Sep 09 07:21:12 AM UTC 24 | Sep 09 07:21:19 AM UTC 24 | 87971390 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.352384831 | Sep 09 07:21:10 AM UTC 24 | Sep 09 07:21:20 AM UTC 24 | 260300393 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.501524633 | Sep 09 07:21:04 AM UTC 24 | Sep 09 07:21:20 AM UTC 24 | 265281933 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.4096357378 | Sep 09 07:21:11 AM UTC 24 | Sep 09 07:21:22 AM UTC 24 | 725066013 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.464096590 | Sep 09 07:21:15 AM UTC 24 | Sep 09 07:21:25 AM UTC 24 | 378349701 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2052667973 | Sep 09 07:21:10 AM UTC 24 | Sep 09 07:21:26 AM UTC 24 | 748262768 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.365101354 | Sep 09 07:21:14 AM UTC 24 | Sep 09 07:21:27 AM UTC 24 | 199029983 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.1088230986 | Sep 09 07:21:20 AM UTC 24 | Sep 09 07:21:28 AM UTC 24 | 523557112 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.2865018873 | Sep 09 07:21:21 AM UTC 24 | Sep 09 07:21:29 AM UTC 24 | 99236189 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2206977043 | Sep 09 07:19:19 AM UTC 24 | Sep 09 07:21:30 AM UTC 24 | 1760856943 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.3549153268 | Sep 09 07:21:26 AM UTC 24 | Sep 09 07:21:33 AM UTC 24 | 129630298 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1597078009 | Sep 09 07:19:28 AM UTC 24 | Sep 09 07:21:33 AM UTC 24 | 14657699747 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.9965272 | Sep 09 07:18:28 AM UTC 24 | Sep 09 07:21:34 AM UTC 24 | 13994348954 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.2117103064 | Sep 09 07:21:17 AM UTC 24 | Sep 09 07:21:34 AM UTC 24 | 1038224886 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.1697562049 | Sep 09 07:21:20 AM UTC 24 | Sep 09 07:21:35 AM UTC 24 | 606136375 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.702138514 | Sep 09 07:21:21 AM UTC 24 | Sep 09 07:21:38 AM UTC 24 | 509811235 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.3408976041 | Sep 09 07:21:27 AM UTC 24 | Sep 09 07:21:39 AM UTC 24 | 122666223 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.3034018946 | Sep 09 07:21:28 AM UTC 24 | Sep 09 07:21:39 AM UTC 24 | 542358562 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3072686594 | Sep 09 07:21:33 AM UTC 24 | Sep 09 07:21:42 AM UTC 24 | 271853217 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2453181344 | Sep 09 07:21:35 AM UTC 24 | Sep 09 07:21:45 AM UTC 24 | 541620060 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.4183797468 | Sep 09 07:21:33 AM UTC 24 | Sep 09 07:21:45 AM UTC 24 | 510010137 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.2439133861 | Sep 09 07:21:40 AM UTC 24 | Sep 09 07:21:46 AM UTC 24 | 247269758 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.224401653 | Sep 09 07:21:30 AM UTC 24 | Sep 09 07:21:46 AM UTC 24 | 674041304 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1503855109 | Sep 09 07:19:08 AM UTC 24 | Sep 09 07:21:49 AM UTC 24 | 3037910297 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.2247019774 | Sep 09 07:21:43 AM UTC 24 | Sep 09 07:21:52 AM UTC 24 | 372150682 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.2598954073 | Sep 09 07:21:37 AM UTC 24 | Sep 09 07:21:53 AM UTC 24 | 693429045 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.1282413101 | Sep 09 07:21:46 AM UTC 24 | Sep 09 07:21:54 AM UTC 24 | 924462395 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2404069376 | Sep 09 07:21:46 AM UTC 24 | Sep 09 07:21:54 AM UTC 24 | 94381257 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.1772911115 | Sep 09 07:21:40 AM UTC 24 | Sep 09 07:21:57 AM UTC 24 | 808194542 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.2432333847 | Sep 09 07:21:44 AM UTC 24 | Sep 09 07:21:58 AM UTC 24 | 172121275 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1403972118 | Sep 09 07:19:39 AM UTC 24 | Sep 09 07:21:59 AM UTC 24 | 2106452128 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.1359213912 | Sep 09 07:21:54 AM UTC 24 | Sep 09 07:22:00 AM UTC 24 | 132886110 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2902741885 | Sep 09 07:19:58 AM UTC 24 | Sep 09 07:22:00 AM UTC 24 | 3120991633 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.2561127104 | Sep 09 07:21:55 AM UTC 24 | Sep 09 07:22:03 AM UTC 24 | 269807600 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.2610877608 | Sep 09 07:21:50 AM UTC 24 | Sep 09 07:22:03 AM UTC 24 | 2081624959 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.4232728278 | Sep 09 07:21:46 AM UTC 24 | Sep 09 07:22:06 AM UTC 24 | 604418409 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.3981911683 | Sep 09 07:21:59 AM UTC 24 | Sep 09 07:22:07 AM UTC 24 | 89408015 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.3254446576 | Sep 09 07:22:01 AM UTC 24 | Sep 09 07:22:11 AM UTC 24 | 99230360 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3636741877 | Sep 09 07:21:57 AM UTC 24 | Sep 09 07:22:13 AM UTC 24 | 1903895441 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.1756612713 | Sep 09 07:22:00 AM UTC 24 | Sep 09 07:22:13 AM UTC 24 | 160525692 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1274818156 | Sep 09 07:19:42 AM UTC 24 | Sep 09 07:22:13 AM UTC 24 | 2233895996 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.2796977350 | Sep 09 07:22:08 AM UTC 24 | Sep 09 07:22:15 AM UTC 24 | 494744251 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2448010724 | Sep 09 07:21:55 AM UTC 24 | Sep 09 07:22:15 AM UTC 24 | 403858174 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.640883554 | Sep 09 07:19:31 AM UTC 24 | Sep 09 07:22:18 AM UTC 24 | 13333063051 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3612226851 | Sep 09 07:20:23 AM UTC 24 | Sep 09 07:22:19 AM UTC 24 | 7071360140 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.1751036999 | Sep 09 07:22:04 AM UTC 24 | Sep 09 07:22:21 AM UTC 24 | 251500687 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.250785195 | Sep 09 07:21:10 AM UTC 24 | Sep 09 07:22:21 AM UTC 24 | 1028227824 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3969574525 | Sep 09 07:22:16 AM UTC 24 | Sep 09 07:22:23 AM UTC 24 | 521958655 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1728347222 | Sep 09 07:21:12 AM UTC 24 | Sep 09 07:22:23 AM UTC 24 | 6186024182 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1226389092 | Sep 09 07:23:27 AM UTC 24 | Sep 09 07:23:35 AM UTC 24 | 497719775 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.1738537298 | Sep 09 07:22:08 AM UTC 24 | Sep 09 07:22:25 AM UTC 24 | 1093963288 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.4206046489 | Sep 09 07:22:14 AM UTC 24 | Sep 09 07:22:26 AM UTC 24 | 1463582374 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.939235381 | Sep 09 07:22:18 AM UTC 24 | Sep 09 07:22:27 AM UTC 24 | 353640491 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.55924271 | Sep 09 07:20:51 AM UTC 24 | Sep 09 07:22:28 AM UTC 24 | 1227850183 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.866598998 | Sep 09 07:22:23 AM UTC 24 | Sep 09 07:22:30 AM UTC 24 | 172108861 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3342167508 | Sep 09 07:21:45 AM UTC 24 | Sep 09 07:22:31 AM UTC 24 | 1082833634 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.1631274589 | Sep 09 07:22:24 AM UTC 24 | Sep 09 07:22:32 AM UTC 24 | 274017402 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1753469966 | Sep 09 07:20:27 AM UTC 24 | Sep 09 07:22:33 AM UTC 24 | 14560077245 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3232974955 | Sep 09 07:20:47 AM UTC 24 | Sep 09 07:22:35 AM UTC 24 | 8256850510 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.1438698495 | Sep 09 07:22:23 AM UTC 24 | Sep 09 07:22:35 AM UTC 24 | 554157366 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.1583723508 | Sep 09 07:23:17 AM UTC 24 | Sep 09 07:23:34 AM UTC 24 | 287477114 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.1617058115 | Sep 09 07:22:16 AM UTC 24 | Sep 09 07:22:35 AM UTC 24 | 1187693502 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.445213651 | Sep 09 07:23:12 AM UTC 24 | Sep 09 07:23:29 AM UTC 24 | 756776898 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2130710098 | Sep 09 07:22:28 AM UTC 24 | Sep 09 07:22:36 AM UTC 24 | 516010925 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.175392673 | Sep 09 07:22:21 AM UTC 24 | Sep 09 07:22:37 AM UTC 24 | 258169612 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3025089359 | Sep 09 07:20:38 AM UTC 24 | Sep 09 07:22:38 AM UTC 24 | 2910438942 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2879408113 | Sep 09 07:22:27 AM UTC 24 | Sep 09 07:22:39 AM UTC 24 | 722599321 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.1633544693 | Sep 09 07:22:33 AM UTC 24 | Sep 09 07:22:41 AM UTC 24 | 259450502 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2861214168 | Sep 09 07:21:43 AM UTC 24 | Sep 09 07:22:41 AM UTC 24 | 1067825714 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.2648504038 | Sep 09 07:22:31 AM UTC 24 | Sep 09 07:22:42 AM UTC 24 | 139207924 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1178140763 | Sep 09 07:19:56 AM UTC 24 | Sep 09 07:22:42 AM UTC 24 | 2360812549 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.2672614637 | Sep 09 07:22:37 AM UTC 24 | Sep 09 07:22:44 AM UTC 24 | 226162607 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.676321162 | Sep 09 07:22:39 AM UTC 24 | Sep 09 07:22:46 AM UTC 24 | 99043434 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.2526142623 | Sep 09 07:22:34 AM UTC 24 | Sep 09 07:22:46 AM UTC 24 | 131345413 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.2261487054 | Sep 09 07:22:36 AM UTC 24 | Sep 09 07:22:46 AM UTC 24 | 640796695 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.3855276489 | Sep 09 07:22:32 AM UTC 24 | Sep 09 07:22:47 AM UTC 24 | 179011258 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.760972604 | Sep 09 07:18:39 AM UTC 24 | Sep 09 07:22:48 AM UTC 24 | 24966923502 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.437600263 | Sep 09 07:22:37 AM UTC 24 | Sep 09 07:22:48 AM UTC 24 | 1036192566 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.197863140 | Sep 09 07:21:01 AM UTC 24 | Sep 09 07:22:49 AM UTC 24 | 1882467058 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2808832190 | Sep 09 07:20:33 AM UTC 24 | Sep 09 07:22:49 AM UTC 24 | 3356668504 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.2567549404 | Sep 09 07:22:29 AM UTC 24 | Sep 09 07:22:51 AM UTC 24 | 298634015 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.558350334 | Sep 09 07:21:31 AM UTC 24 | Sep 09 07:22:51 AM UTC 24 | 4319235308 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.750971685 | Sep 09 07:22:43 AM UTC 24 | Sep 09 07:22:51 AM UTC 24 | 495233691 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.2775652399 | Sep 09 07:23:04 AM UTC 24 | Sep 09 07:23:38 AM UTC 24 | 552402312 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2136755554 | Sep 09 07:21:20 AM UTC 24 | Sep 09 07:22:51 AM UTC 24 | 1839926925 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.2620997899 | Sep 09 07:22:42 AM UTC 24 | Sep 09 07:22:54 AM UTC 24 | 700543446 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3928292809 | Sep 09 07:22:48 AM UTC 24 | Sep 09 07:22:54 AM UTC 24 | 522465257 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.2903412379 | Sep 09 07:22:45 AM UTC 24 | Sep 09 07:22:55 AM UTC 24 | 96752558 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.1685690691 | Sep 09 07:22:49 AM UTC 24 | Sep 09 07:22:58 AM UTC 24 | 269388718 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.3092253415 | Sep 09 07:22:51 AM UTC 24 | Sep 09 07:22:59 AM UTC 24 | 130586871 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1428593252 | Sep 09 07:20:11 AM UTC 24 | Sep 09 07:23:00 AM UTC 24 | 2693517360 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.3422060634 | Sep 09 07:22:38 AM UTC 24 | Sep 09 07:23:02 AM UTC 24 | 295063550 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.1811941731 | Sep 09 07:22:55 AM UTC 24 | Sep 09 07:23:03 AM UTC 24 | 362484976 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.2306016216 | Sep 09 07:22:52 AM UTC 24 | Sep 09 07:23:03 AM UTC 24 | 1897158852 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2561125132 | Sep 09 07:22:46 AM UTC 24 | Sep 09 07:23:04 AM UTC 24 | 518818950 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2797953960 | Sep 09 07:22:50 AM UTC 24 | Sep 09 07:23:04 AM UTC 24 | 699132862 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2168187222 | Sep 09 07:22:43 AM UTC 24 | Sep 09 07:23:05 AM UTC 24 | 432334262 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.3367955858 | Sep 09 07:22:48 AM UTC 24 | Sep 09 07:23:07 AM UTC 24 | 766631093 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.844927049 | Sep 09 07:22:52 AM UTC 24 | Sep 09 07:23:07 AM UTC 24 | 133679289 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.2876272501 | Sep 09 07:22:59 AM UTC 24 | Sep 09 07:23:08 AM UTC 24 | 100587974 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3907325076 | Sep 09 07:20:15 AM UTC 24 | Sep 09 07:23:08 AM UTC 24 | 13846316711 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.1262973833 | Sep 09 07:22:52 AM UTC 24 | Sep 09 07:23:10 AM UTC 24 | 3565600031 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2312913024 | Sep 09 07:20:17 AM UTC 24 | Sep 09 07:23:12 AM UTC 24 | 19120294512 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.219865129 | Sep 09 07:21:07 AM UTC 24 | Sep 09 07:23:12 AM UTC 24 | 1683265918 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.1546839488 | Sep 09 07:23:04 AM UTC 24 | Sep 09 07:23:12 AM UTC 24 | 2478004906 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.4059906944 | Sep 09 07:22:55 AM UTC 24 | Sep 09 07:23:13 AM UTC 24 | 1127074722 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3879243751 | Sep 09 07:23:08 AM UTC 24 | Sep 09 07:23:14 AM UTC 24 | 88334511 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1291232921 | Sep 09 07:23:05 AM UTC 24 | Sep 09 07:23:15 AM UTC 24 | 139787928 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.4277284706 | Sep 09 07:23:01 AM UTC 24 | Sep 09 07:23:16 AM UTC 24 | 441538522 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.2359435749 | Sep 09 07:23:09 AM UTC 24 | Sep 09 07:23:18 AM UTC 24 | 562827615 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.2002906536 | Sep 09 07:23:13 AM UTC 24 | Sep 09 07:23:20 AM UTC 24 | 566643768 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.4179006530 | Sep 09 07:23:06 AM UTC 24 | Sep 09 07:23:20 AM UTC 24 | 265161703 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2556343205 | Sep 09 07:22:42 AM UTC 24 | Sep 09 07:23:22 AM UTC 24 | 888859130 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2344194299 | Sep 09 07:21:50 AM UTC 24 | Sep 09 07:23:23 AM UTC 24 | 7650636937 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.952651211 | Sep 09 07:23:15 AM UTC 24 | Sep 09 07:23:25 AM UTC 24 | 142206194 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3768813344 | Sep 09 07:19:49 AM UTC 24 | Sep 09 07:23:26 AM UTC 24 | 8124027084 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2876399896 | Sep 09 07:21:16 AM UTC 24 | Sep 09 07:23:26 AM UTC 24 | 16327778640 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.3017799654 | Sep 09 07:23:21 AM UTC 24 | Sep 09 07:23:27 AM UTC 24 | 247026423 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.2596933370 | Sep 09 07:23:08 AM UTC 24 | Sep 09 07:23:27 AM UTC 24 | 826004494 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.797781807 | Sep 09 07:23:27 AM UTC 24 | Sep 09 07:23:39 AM UTC 24 | 631013562 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.2550439864 | Sep 09 07:23:14 AM UTC 24 | Sep 09 07:23:29 AM UTC 24 | 887858056 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2555404454 | Sep 09 07:21:28 AM UTC 24 | Sep 09 07:23:31 AM UTC 24 | 5369223176 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.4241332901 | Sep 09 07:23:21 AM UTC 24 | Sep 09 07:23:42 AM UTC 24 | 2064687262 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.1067218450 | Sep 09 07:23:23 AM UTC 24 | Sep 09 07:23:33 AM UTC 24 | 98752700 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2070698240 | Sep 09 07:21:21 AM UTC 24 | Sep 09 07:23:33 AM UTC 24 | 15531686974 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.704500857 | Sep 09 07:22:04 AM UTC 24 | Sep 09 07:23:36 AM UTC 24 | 1489533216 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.4071198389 | Sep 09 07:23:27 AM UTC 24 | Sep 09 07:23:37 AM UTC 24 | 99219563 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2430094631 | Sep 09 07:21:58 AM UTC 24 | Sep 09 07:23:38 AM UTC 24 | 1753143463 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2965466890 | Sep 09 07:21:09 AM UTC 24 | Sep 09 07:23:41 AM UTC 24 | 8629950343 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.4061058622 | Sep 09 07:23:19 AM UTC 24 | Sep 09 07:23:41 AM UTC 24 | 1061169176 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.3191659493 | Sep 09 07:23:34 AM UTC 24 | Sep 09 07:23:42 AM UTC 24 | 587675807 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2692531598 | Sep 09 07:21:36 AM UTC 24 | Sep 09 07:23:43 AM UTC 24 | 7505276257 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2762529249 | Sep 09 07:23:26 AM UTC 24 | Sep 09 07:23:44 AM UTC 24 | 508585653 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.4150001535 | Sep 09 07:21:53 AM UTC 24 | Sep 09 07:23:45 AM UTC 24 | 2782969459 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.4162169113 | Sep 09 07:23:35 AM UTC 24 | Sep 09 07:23:45 AM UTC 24 | 141965890 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.155390968 | Sep 09 07:23:30 AM UTC 24 | Sep 09 07:23:46 AM UTC 24 | 489821023 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.1074798023 | Sep 09 07:23:39 AM UTC 24 | Sep 09 07:23:46 AM UTC 24 | 1042060965 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.448052325 | Sep 09 07:22:37 AM UTC 24 | Sep 09 07:23:46 AM UTC 24 | 3075692957 ps |
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