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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.42 96.89 92.13 97.67 100.00 98.28 97.90 99.06


Total test records in report: 460
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T300 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.319399258 Sep 11 04:57:00 AM UTC 24 Sep 11 04:57:13 AM UTC 24 693532389 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.544722810 Sep 11 04:57:05 AM UTC 24 Sep 11 04:57:13 AM UTC 24 531673955 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.2116520068 Sep 11 04:56:51 AM UTC 24 Sep 11 04:57:14 AM UTC 24 884784010 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.1049924508 Sep 11 04:57:10 AM UTC 24 Sep 11 04:57:18 AM UTC 24 516471971 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2510118620 Sep 11 04:57:02 AM UTC 24 Sep 11 04:57:20 AM UTC 24 964767290 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3568847331 Sep 11 04:57:11 AM UTC 24 Sep 11 04:57:20 AM UTC 24 163520343 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.112630535 Sep 11 04:57:14 AM UTC 24 Sep 11 04:57:20 AM UTC 24 358930378 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3963274119 Sep 11 04:55:57 AM UTC 24 Sep 11 04:57:21 AM UTC 24 1395588502 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2426848069 Sep 11 04:55:32 AM UTC 24 Sep 11 04:57:21 AM UTC 24 10661479672 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2109750676 Sep 11 04:57:12 AM UTC 24 Sep 11 04:57:22 AM UTC 24 285338046 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.2574849171 Sep 11 04:57:09 AM UTC 24 Sep 11 04:57:26 AM UTC 24 1038150023 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.1798464298 Sep 11 04:57:14 AM UTC 24 Sep 11 04:57:26 AM UTC 24 2074329914 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.479173326 Sep 11 04:57:18 AM UTC 24 Sep 11 04:57:27 AM UTC 24 98992820 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.2037930112 Sep 11 04:57:16 AM UTC 24 Sep 11 04:57:28 AM UTC 24 1251087013 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3876285540 Sep 11 04:56:58 AM UTC 24 Sep 11 04:57:28 AM UTC 24 530844281 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3030398135 Sep 11 04:57:22 AM UTC 24 Sep 11 04:57:29 AM UTC 24 169320116 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.2714731577 Sep 11 04:57:23 AM UTC 24 Sep 11 04:57:33 AM UTC 24 136593240 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3775746882 Sep 11 04:57:21 AM UTC 24 Sep 11 04:57:34 AM UTC 24 1507502138 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3861058712 Sep 11 04:54:51 AM UTC 24 Sep 11 04:57:34 AM UTC 24 2098003780 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1154635392 Sep 11 04:57:29 AM UTC 24 Sep 11 04:57:37 AM UTC 24 87460111 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1763733181 Sep 11 04:57:23 AM UTC 24 Sep 11 04:57:37 AM UTC 24 1203348922 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2598765299 Sep 11 04:56:03 AM UTC 24 Sep 11 04:57:38 AM UTC 24 2203423522 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2945231404 Sep 11 04:57:30 AM UTC 24 Sep 11 04:57:39 AM UTC 24 103928901 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1084104138 Sep 11 04:57:27 AM UTC 24 Sep 11 04:57:42 AM UTC 24 260838337 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2048031108 Sep 11 04:56:09 AM UTC 24 Sep 11 04:57:42 AM UTC 24 10288996500 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2656603310 Sep 11 04:55:35 AM UTC 24 Sep 11 04:57:44 AM UTC 24 9201370676 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.657733995 Sep 11 04:57:37 AM UTC 24 Sep 11 04:57:45 AM UTC 24 349565647 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.3623484688 Sep 11 04:57:34 AM UTC 24 Sep 11 04:57:51 AM UTC 24 1025706147 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.3368676311 Sep 11 04:57:30 AM UTC 24 Sep 11 04:57:51 AM UTC 24 2077986055 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1043026221 Sep 11 04:55:17 AM UTC 24 Sep 11 04:57:57 AM UTC 24 8496936581 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.544906155 Sep 11 04:55:54 AM UTC 24 Sep 11 04:58:08 AM UTC 24 2941061689 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1984077261 Sep 11 04:55:47 AM UTC 24 Sep 11 04:58:09 AM UTC 24 14986183454 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3347201073 Sep 11 04:56:05 AM UTC 24 Sep 11 04:58:11 AM UTC 24 7303837507 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2658304978 Sep 11 04:57:14 AM UTC 24 Sep 11 04:58:11 AM UTC 24 968946340 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1628824751 Sep 11 04:53:21 AM UTC 24 Sep 11 04:58:21 AM UTC 24 18492068104 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2167681924 Sep 11 04:56:47 AM UTC 24 Sep 11 04:58:22 AM UTC 24 1759065506 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.380420822 Sep 11 04:55:52 AM UTC 24 Sep 11 04:58:22 AM UTC 24 1958681636 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1400568232 Sep 11 04:56:22 AM UTC 24 Sep 11 04:58:22 AM UTC 24 2966037244 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1342896136 Sep 11 04:54:34 AM UTC 24 Sep 11 04:58:24 AM UTC 24 63683963173 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3755581179 Sep 11 04:55:43 AM UTC 24 Sep 11 04:58:27 AM UTC 24 4517584921 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3433360844 Sep 11 04:57:01 AM UTC 24 Sep 11 04:58:30 AM UTC 24 3567716916 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3873651965 Sep 11 04:57:35 AM UTC 24 Sep 11 04:58:48 AM UTC 24 1579827266 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1586950682 Sep 11 04:55:25 AM UTC 24 Sep 11 04:58:50 AM UTC 24 14447908930 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.676210454 Sep 11 04:56:17 AM UTC 24 Sep 11 04:58:53 AM UTC 24 9911617038 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4174101197 Sep 11 04:57:20 AM UTC 24 Sep 11 04:58:54 AM UTC 24 6545019203 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2723225141 Sep 11 04:56:54 AM UTC 24 Sep 11 04:59:01 AM UTC 24 3117968382 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2701063494 Sep 11 04:56:29 AM UTC 24 Sep 11 04:59:08 AM UTC 24 2820009933 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3402489390 Sep 11 04:56:12 AM UTC 24 Sep 11 04:59:08 AM UTC 24 6086469664 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2134049413 Sep 11 04:56:43 AM UTC 24 Sep 11 04:59:12 AM UTC 24 92105712551 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.45526618 Sep 11 04:56:34 AM UTC 24 Sep 11 04:59:14 AM UTC 24 3942449936 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1055848108 Sep 11 04:57:13 AM UTC 24 Sep 11 04:59:20 AM UTC 24 9069271612 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3574847523 Sep 11 04:57:06 AM UTC 24 Sep 11 04:59:24 AM UTC 24 2162039978 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2697400922 Sep 11 04:57:10 AM UTC 24 Sep 11 04:59:28 AM UTC 24 3515651560 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1056977025 Sep 11 04:56:40 AM UTC 24 Sep 11 04:59:30 AM UTC 24 19858697836 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3081874368 Sep 11 04:57:00 AM UTC 24 Sep 11 04:59:44 AM UTC 24 13392605307 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2910159413 Sep 11 04:56:54 AM UTC 24 Sep 11 04:59:45 AM UTC 24 2505547899 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2287768200 Sep 11 04:57:27 AM UTC 24 Sep 11 04:59:48 AM UTC 24 23834598762 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.523991212 Sep 11 04:57:28 AM UTC 24 Sep 11 05:00:16 AM UTC 24 9950932759 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1501661625 Sep 11 04:57:34 AM UTC 24 Sep 11 05:00:31 AM UTC 24 3171819624 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3181214225 Sep 11 04:56:30 AM UTC 24 Sep 11 05:00:36 AM UTC 24 7268223868 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.128399969 Sep 11 04:57:22 AM UTC 24 Sep 11 05:01:41 AM UTC 24 17873149885 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1212548953 Sep 11 04:56:34 AM UTC 24 Sep 11 05:01:56 AM UTC 24 4352331886 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2252872673 Sep 11 04:55:39 AM UTC 24 Sep 11 05:02:02 AM UTC 24 21187713583 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3747335421 Sep 11 04:56:24 AM UTC 24 Sep 11 05:02:33 AM UTC 24 20358029119 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.4002647908 Sep 11 04:56:49 AM UTC 24 Sep 11 05:02:48 AM UTC 24 38827970122 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2439327312 Sep 11 05:09:04 AM UTC 24 Sep 11 05:09:10 AM UTC 24 1553736305 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1325887259 Sep 11 05:09:04 AM UTC 24 Sep 11 05:09:11 AM UTC 24 515613917 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3275339960 Sep 11 05:09:04 AM UTC 24 Sep 11 05:09:11 AM UTC 24 499234122 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2872197989 Sep 11 05:09:04 AM UTC 24 Sep 11 05:09:11 AM UTC 24 130581150 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1439223355 Sep 11 05:09:04 AM UTC 24 Sep 11 05:09:11 AM UTC 24 847928727 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.467673659 Sep 11 05:09:05 AM UTC 24 Sep 11 05:09:12 AM UTC 24 98631999 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.797817364 Sep 11 05:09:04 AM UTC 24 Sep 11 05:09:12 AM UTC 24 2063785638 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2209255902 Sep 11 05:09:05 AM UTC 24 Sep 11 05:09:12 AM UTC 24 288185864 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4110831949 Sep 11 05:09:04 AM UTC 24 Sep 11 05:09:12 AM UTC 24 134159178 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1862730378 Sep 11 05:09:05 AM UTC 24 Sep 11 05:09:12 AM UTC 24 499605892 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.970970720 Sep 11 05:09:05 AM UTC 24 Sep 11 05:09:12 AM UTC 24 334071846 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.701042153 Sep 11 05:09:04 AM UTC 24 Sep 11 05:09:13 AM UTC 24 271926818 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2980177976 Sep 11 05:09:04 AM UTC 24 Sep 11 05:09:13 AM UTC 24 126488943 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1985491111 Sep 11 05:09:07 AM UTC 24 Sep 11 05:09:13 AM UTC 24 308716410 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2488366905 Sep 11 05:09:04 AM UTC 24 Sep 11 05:09:13 AM UTC 24 135356539 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1519056159 Sep 11 05:09:05 AM UTC 24 Sep 11 05:09:14 AM UTC 24 1254309620 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3077427433 Sep 11 05:09:08 AM UTC 24 Sep 11 05:09:17 AM UTC 24 333040545 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.710772008 Sep 11 05:09:13 AM UTC 24 Sep 11 05:09:18 AM UTC 24 639666995 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.646057592 Sep 11 05:09:13 AM UTC 24 Sep 11 05:09:18 AM UTC 24 217348924 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1027070140 Sep 11 05:09:13 AM UTC 24 Sep 11 05:09:19 AM UTC 24 87967643 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.414365568 Sep 11 05:09:13 AM UTC 24 Sep 11 05:09:19 AM UTC 24 125995742 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.177570723 Sep 11 05:09:11 AM UTC 24 Sep 11 05:09:19 AM UTC 24 853600986 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1400441196 Sep 11 05:09:13 AM UTC 24 Sep 11 05:09:20 AM UTC 24 359225513 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.587814819 Sep 11 05:09:14 AM UTC 24 Sep 11 05:09:20 AM UTC 24 126537594 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2952866819 Sep 11 05:09:14 AM UTC 24 Sep 11 05:09:20 AM UTC 24 131538101 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2963466793 Sep 11 05:09:13 AM UTC 24 Sep 11 05:09:21 AM UTC 24 133011305 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1068461444 Sep 11 05:09:14 AM UTC 24 Sep 11 05:09:21 AM UTC 24 546463692 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2954009879 Sep 11 05:09:11 AM UTC 24 Sep 11 05:09:21 AM UTC 24 250667497 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.296949196 Sep 11 05:09:14 AM UTC 24 Sep 11 05:09:21 AM UTC 24 311596035 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2595343027 Sep 11 05:09:14 AM UTC 24 Sep 11 05:09:22 AM UTC 24 436655243 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.89673098 Sep 11 05:09:16 AM UTC 24 Sep 11 05:09:22 AM UTC 24 172382373 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.333073189 Sep 11 05:09:14 AM UTC 24 Sep 11 05:09:22 AM UTC 24 518406871 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.591257522 Sep 11 05:09:15 AM UTC 24 Sep 11 05:09:22 AM UTC 24 87436997 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3997146244 Sep 11 05:09:16 AM UTC 24 Sep 11 05:09:22 AM UTC 24 521670909 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2614040351 Sep 11 05:09:17 AM UTC 24 Sep 11 05:09:22 AM UTC 24 88853560 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1887109646 Sep 11 05:09:14 AM UTC 24 Sep 11 05:09:22 AM UTC 24 499785862 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2217228269 Sep 11 05:09:15 AM UTC 24 Sep 11 05:09:23 AM UTC 24 458235585 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2109775311 Sep 11 05:09:17 AM UTC 24 Sep 11 05:09:23 AM UTC 24 347456442 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2569515036 Sep 11 05:09:04 AM UTC 24 Sep 11 05:09:23 AM UTC 24 368111913 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2880554344 Sep 11 05:09:14 AM UTC 24 Sep 11 05:09:24 AM UTC 24 325117029 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1128335111 Sep 11 05:09:14 AM UTC 24 Sep 11 05:09:24 AM UTC 24 250559738 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.601845390 Sep 11 05:09:19 AM UTC 24 Sep 11 05:09:24 AM UTC 24 172782232 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.334555240 Sep 11 05:09:18 AM UTC 24 Sep 11 05:09:25 AM UTC 24 127612328 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4153431175 Sep 11 05:09:19 AM UTC 24 Sep 11 05:09:26 AM UTC 24 597347051 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3090228489 Sep 11 05:09:17 AM UTC 24 Sep 11 05:09:27 AM UTC 24 132581663 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3727425970 Sep 11 05:09:21 AM UTC 24 Sep 11 05:09:28 AM UTC 24 1787917001 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2981275049 Sep 11 05:09:21 AM UTC 24 Sep 11 05:09:28 AM UTC 24 87333384 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.50922303 Sep 11 05:09:19 AM UTC 24 Sep 11 05:09:28 AM UTC 24 88902091 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4265834421 Sep 11 05:09:15 AM UTC 24 Sep 11 05:09:28 AM UTC 24 630787495 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.271716629 Sep 11 05:09:21 AM UTC 24 Sep 11 05:09:28 AM UTC 24 537801605 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3353520706 Sep 11 05:09:23 AM UTC 24 Sep 11 05:09:29 AM UTC 24 132541280 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1344899082 Sep 11 05:09:24 AM UTC 24 Sep 11 05:09:29 AM UTC 24 175339105 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2156709276 Sep 11 05:09:23 AM UTC 24 Sep 11 05:09:30 AM UTC 24 334513219 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.317162289 Sep 11 05:09:25 AM UTC 24 Sep 11 05:09:30 AM UTC 24 88918940 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3300370971 Sep 11 05:09:23 AM UTC 24 Sep 11 05:09:31 AM UTC 24 144994564 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3615305706 Sep 11 05:09:25 AM UTC 24 Sep 11 05:09:31 AM UTC 24 100786798 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4224211641 Sep 11 05:09:24 AM UTC 24 Sep 11 05:09:32 AM UTC 24 130403152 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2671120868 Sep 11 05:09:21 AM UTC 24 Sep 11 05:09:32 AM UTC 24 127204881 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3499663214 Sep 11 05:09:24 AM UTC 24 Sep 11 05:09:32 AM UTC 24 1323917832 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1779753636 Sep 11 05:09:25 AM UTC 24 Sep 11 05:09:33 AM UTC 24 2477215030 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.40372031 Sep 11 05:09:24 AM UTC 24 Sep 11 05:09:33 AM UTC 24 88200584 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2334783413 Sep 11 05:09:29 AM UTC 24 Sep 11 05:09:35 AM UTC 24 256595963 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1261757708 Sep 11 05:09:15 AM UTC 24 Sep 11 05:09:36 AM UTC 24 747699665 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1937551446 Sep 11 05:09:24 AM UTC 24 Sep 11 05:09:36 AM UTC 24 361286228 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.570069550 Sep 11 05:09:27 AM UTC 24 Sep 11 05:09:36 AM UTC 24 169080171 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.83359746 Sep 11 05:09:29 AM UTC 24 Sep 11 05:09:37 AM UTC 24 542411358 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3666717389 Sep 11 05:09:30 AM UTC 24 Sep 11 05:09:37 AM UTC 24 346308742 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3077144256 Sep 11 05:09:29 AM UTC 24 Sep 11 05:09:37 AM UTC 24 1566983423 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4132750897 Sep 11 05:09:31 AM UTC 24 Sep 11 05:09:38 AM UTC 24 130293415 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3482371205 Sep 11 05:09:33 AM UTC 24 Sep 11 05:09:39 AM UTC 24 89224880 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4154697425 Sep 11 05:09:33 AM UTC 24 Sep 11 05:09:39 AM UTC 24 369096162 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.65429574 Sep 11 05:09:11 AM UTC 24 Sep 11 05:09:39 AM UTC 24 570188291 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.948364260 Sep 11 05:09:33 AM UTC 24 Sep 11 05:09:40 AM UTC 24 829948642 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2757089340 Sep 11 05:09:31 AM UTC 24 Sep 11 05:09:40 AM UTC 24 504884057 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1853186944 Sep 11 05:09:04 AM UTC 24 Sep 11 05:09:40 AM UTC 24 1630847004 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.661630047 Sep 11 05:09:30 AM UTC 24 Sep 11 05:09:41 AM UTC 24 148036216 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1714277262 Sep 11 05:09:37 AM UTC 24 Sep 11 05:09:43 AM UTC 24 90245609 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2673895362 Sep 11 05:09:36 AM UTC 24 Sep 11 05:09:43 AM UTC 24 521431102 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.710676234 Sep 11 05:09:32 AM UTC 24 Sep 11 05:09:43 AM UTC 24 1392181113 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3011691603 Sep 11 05:09:37 AM UTC 24 Sep 11 05:09:43 AM UTC 24 361684705 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.225655785 Sep 11 05:09:38 AM UTC 24 Sep 11 05:09:45 AM UTC 24 87096877 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3159983836 Sep 11 05:09:36 AM UTC 24 Sep 11 05:09:45 AM UTC 24 118142843 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3373186322 Sep 11 05:09:39 AM UTC 24 Sep 11 05:09:46 AM UTC 24 142657093 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1415252438 Sep 11 05:09:23 AM UTC 24 Sep 11 05:09:46 AM UTC 24 537868322 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4065495046 Sep 11 05:09:21 AM UTC 24 Sep 11 05:09:46 AM UTC 24 537786945 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3718639408 Sep 11 05:09:14 AM UTC 24 Sep 11 05:09:47 AM UTC 24 3125632787 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3434731403 Sep 11 05:09:41 AM UTC 24 Sep 11 05:09:47 AM UTC 24 239056443 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3938664265 Sep 11 05:09:39 AM UTC 24 Sep 11 05:09:48 AM UTC 24 95226807 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1284457085 Sep 11 05:09:41 AM UTC 24 Sep 11 05:09:49 AM UTC 24 127398203 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.583396793 Sep 11 05:09:43 AM UTC 24 Sep 11 05:09:49 AM UTC 24 88417609 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1883349710 Sep 11 05:09:42 AM UTC 24 Sep 11 05:09:50 AM UTC 24 381160496 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4262464451 Sep 11 05:09:38 AM UTC 24 Sep 11 05:09:50 AM UTC 24 832493172 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1994294437 Sep 11 05:09:40 AM UTC 24 Sep 11 05:09:50 AM UTC 24 521046255 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1689188153 Sep 11 05:09:24 AM UTC 24 Sep 11 05:09:52 AM UTC 24 4889726279 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.230260652 Sep 11 05:09:42 AM UTC 24 Sep 11 05:09:52 AM UTC 24 851130888 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.907665085 Sep 11 05:09:44 AM UTC 24 Sep 11 05:09:52 AM UTC 24 291559008 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1843030533 Sep 11 05:09:47 AM UTC 24 Sep 11 05:09:53 AM UTC 24 91522079 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.878057772 Sep 11 05:09:19 AM UTC 24 Sep 11 05:09:54 AM UTC 24 6040657053 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.527907121 Sep 11 05:09:47 AM UTC 24 Sep 11 05:09:54 AM UTC 24 401647277 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2969868468 Sep 11 05:09:16 AM UTC 24 Sep 11 05:09:54 AM UTC 24 444174706 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.329570780 Sep 11 05:09:44 AM UTC 24 Sep 11 05:09:54 AM UTC 24 363282306 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.665614520 Sep 11 05:09:46 AM UTC 24 Sep 11 05:09:55 AM UTC 24 500704323 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1429751281 Sep 11 05:09:46 AM UTC 24 Sep 11 05:09:57 AM UTC 24 251575104 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.842970299 Sep 11 05:09:50 AM UTC 24 Sep 11 05:09:57 AM UTC 24 1656380803 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2994561243 Sep 11 05:09:26 AM UTC 24 Sep 11 05:09:58 AM UTC 24 1129602661 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.999996697 Sep 11 05:09:30 AM UTC 24 Sep 11 05:09:58 AM UTC 24 2164437428 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.210468733 Sep 11 05:09:51 AM UTC 24 Sep 11 05:09:58 AM UTC 24 89156204 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1000667685 Sep 11 05:09:50 AM UTC 24 Sep 11 05:09:58 AM UTC 24 142949500 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2348492783 Sep 11 05:09:49 AM UTC 24 Sep 11 05:09:59 AM UTC 24 127838872 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3678833061 Sep 11 05:09:51 AM UTC 24 Sep 11 05:10:00 AM UTC 24 350403462 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4094158746 Sep 11 05:09:54 AM UTC 24 Sep 11 05:10:01 AM UTC 24 85533737 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.832910099 Sep 11 05:09:52 AM UTC 24 Sep 11 05:10:01 AM UTC 24 92455498 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.80974595 Sep 11 05:09:11 AM UTC 24 Sep 11 05:10:01 AM UTC 24 794600353 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2649786107 Sep 11 05:09:52 AM UTC 24 Sep 11 05:10:01 AM UTC 24 215282866 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3411943880 Sep 11 05:09:50 AM UTC 24 Sep 11 05:10:01 AM UTC 24 509485663 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1323447898 Sep 11 05:09:42 AM UTC 24 Sep 11 05:10:03 AM UTC 24 367782893 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3685008359 Sep 11 05:09:55 AM UTC 24 Sep 11 05:10:03 AM UTC 24 250727802 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4194512171 Sep 11 05:09:37 AM UTC 24 Sep 11 05:10:03 AM UTC 24 2092340856 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3955604868 Sep 11 05:09:56 AM UTC 24 Sep 11 05:10:04 AM UTC 24 143619089 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4014594540 Sep 11 05:09:54 AM UTC 24 Sep 11 05:10:06 AM UTC 24 546549538 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1058755939 Sep 11 05:09:34 AM UTC 24 Sep 11 05:10:08 AM UTC 24 3149282455 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3868790659 Sep 11 05:09:39 AM UTC 24 Sep 11 05:10:08 AM UTC 24 2211011399 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2486419064 Sep 11 05:09:44 AM UTC 24 Sep 11 05:10:09 AM UTC 24 717970705 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4199622571 Sep 11 05:09:47 AM UTC 24 Sep 11 05:10:10 AM UTC 24 1629822541 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3749796139 Sep 11 05:09:32 AM UTC 24 Sep 11 05:10:12 AM UTC 24 1269129408 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1287278640 Sep 11 05:09:29 AM UTC 24 Sep 11 05:10:14 AM UTC 24 631930161 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.7196521 Sep 11 05:09:36 AM UTC 24 Sep 11 05:10:16 AM UTC 24 567775273 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1985813208 Sep 11 05:09:30 AM UTC 24 Sep 11 05:10:19 AM UTC 24 304421990 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2045435591 Sep 11 05:09:32 AM UTC 24 Sep 11 05:10:20 AM UTC 24 1189610290 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2578792501 Sep 11 05:09:04 AM UTC 24 Sep 11 05:10:21 AM UTC 24 293696480 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2584179103 Sep 11 05:09:04 AM UTC 24 Sep 11 05:10:23 AM UTC 24 568597227 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3056155663 Sep 11 05:09:53 AM UTC 24 Sep 11 05:10:24 AM UTC 24 1083960279 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1216143138 Sep 11 05:09:51 AM UTC 24 Sep 11 05:10:28 AM UTC 24 1589051520 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3111441754 Sep 11 05:09:20 AM UTC 24 Sep 11 05:10:32 AM UTC 24 836022755 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2332453121 Sep 11 05:09:49 AM UTC 24 Sep 11 05:10:33 AM UTC 24 319399242 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.933129303 Sep 11 05:09:51 AM UTC 24 Sep 11 05:10:35 AM UTC 24 2470316763 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1329993519 Sep 11 05:09:25 AM UTC 24 Sep 11 05:10:38 AM UTC 24 1163653376 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.305187099 Sep 11 05:09:14 AM UTC 24 Sep 11 05:10:39 AM UTC 24 333315369 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4074120482 Sep 11 05:09:21 AM UTC 24 Sep 11 05:10:44 AM UTC 24 554574740 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3253951853 Sep 11 05:09:24 AM UTC 24 Sep 11 05:10:48 AM UTC 24 1407787137 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3999651382 Sep 11 05:09:38 AM UTC 24 Sep 11 05:10:52 AM UTC 24 472229393 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.293207791 Sep 11 05:09:42 AM UTC 24 Sep 11 05:10:58 AM UTC 24 1056439661 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1402077823 Sep 11 05:09:46 AM UTC 24 Sep 11 05:11:05 AM UTC 24 1140703047 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3776075927 Sep 11 05:09:41 AM UTC 24 Sep 11 05:11:06 AM UTC 24 760703385 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.522213387 Sep 11 05:09:54 AM UTC 24 Sep 11 05:11:18 AM UTC 24 888079553 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2932225118
Short name T8
Test name
Test status
Simulation time 224061092 ps
CPU time 12.48 seconds
Started Sep 11 04:51:11 AM UTC 24
Finished Sep 11 04:51:25 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293222511
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.2932225118
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1336905808
Short name T12
Test name
Test status
Simulation time 1683176211 ps
CPU time 97.73 seconds
Started Sep 11 04:51:21 AM UTC 24
Finished Sep 11 04:53:01 AM UTC 24
Peak memory 231056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1336905808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1336905808
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3625826688
Short name T7
Test name
Test status
Simulation time 169639125 ps
CPU time 9.56 seconds
Started Sep 11 04:51:11 AM UTC 24
Finished Sep 11 04:51:22 AM UTC 24
Peak memory 221476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625826688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3625826688
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2198817170
Short name T48
Test name
Test status
Simulation time 5855094548 ps
CPU time 139.1 seconds
Started Sep 11 04:51:34 AM UTC 24
Finished Sep 11 04:53:55 AM UTC 24
Peak memory 256412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198817170 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.2198817170
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1002236890
Short name T11
Test name
Test status
Simulation time 2766852863 ps
CPU time 39.39 seconds
Started Sep 11 04:51:27 AM UTC 24
Finished Sep 11 04:52:08 AM UTC 24
Peak memory 228816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1002236890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1002236890
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1856368250
Short name T14
Test name
Test status
Simulation time 4149529198 ps
CPU time 20.11 seconds
Started Sep 11 04:51:09 AM UTC 24
Finished Sep 11 04:51:30 AM UTC 24
Peak memory 225564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185636825
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.1856368250
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.80974595
Short name T67
Test name
Test status
Simulation time 794600353 ps
CPU time 47.78 seconds
Started Sep 11 05:09:11 AM UTC 24
Finished Sep 11 05:10:01 AM UTC 24
Peak memory 222280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80974595 -assert nopostproc +UVM_
TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.80974595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.689970851
Short name T53
Test name
Test status
Simulation time 5904319134 ps
CPU time 170.62 seconds
Started Sep 11 04:52:52 AM UTC 24
Finished Sep 11 04:55:45 AM UTC 24
Peak memory 233168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=689970851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.rom_ctrl_stress_all_with_rand_reset.689970851
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3468098958
Short name T49
Test name
Test status
Simulation time 9271954940 ps
CPU time 140.53 seconds
Started Sep 11 04:51:46 AM UTC 24
Finished Sep 11 04:54:10 AM UTC 24
Peak memory 256412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468098958 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.3468098958
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.232431032
Short name T18
Test name
Test status
Simulation time 317699882 ps
CPU time 17.53 seconds
Started Sep 11 04:52:12 AM UTC 24
Finished Sep 11 04:52:31 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232431032
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.232431032
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.4100241405
Short name T28
Test name
Test status
Simulation time 346285140 ps
CPU time 5.75 seconds
Started Sep 11 04:51:22 AM UTC 24
Finished Sep 11 04:51:29 AM UTC 24
Peak memory 221508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100241405 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4100241405
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.305187099
Short name T117
Test name
Test status
Simulation time 333315369 ps
CPU time 82.69 seconds
Started Sep 11 05:09:14 AM UTC 24
Finished Sep 11 05:10:39 AM UTC 24
Peak memory 224396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305187099 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.305187099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2288749427
Short name T40
Test name
Test status
Simulation time 909990829 ps
CPU time 140.33 seconds
Started Sep 11 04:51:10 AM UTC 24
Finished Sep 11 04:53:33 AM UTC 24
Peak memory 257516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288749427 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2288749427
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1325887259
Short name T72
Test name
Test status
Simulation time 515613917 ps
CPU time 5.52 seconds
Started Sep 11 05:09:04 AM UTC 24
Finished Sep 11 05:09:11 AM UTC 24
Peak memory 229528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325887259 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.1325887259
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1555597802
Short name T50
Test name
Test status
Simulation time 665408856 ps
CPU time 13.65 seconds
Started Sep 11 04:51:56 AM UTC 24
Finished Sep 11 04:52:11 AM UTC 24
Peak memory 221600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555597802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1555597802
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2640088060
Short name T21
Test name
Test status
Simulation time 1283902544 ps
CPU time 78.66 seconds
Started Sep 11 04:51:56 AM UTC 24
Finished Sep 11 04:53:16 AM UTC 24
Peak memory 243920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640088060 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.2640088060
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2745186055
Short name T31
Test name
Test status
Simulation time 1039916037 ps
CPU time 23.54 seconds
Started Sep 11 04:51:26 AM UTC 24
Finished Sep 11 04:51:51 AM UTC 24
Peak memory 221604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745186055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2745186055
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.3324367744
Short name T3
Test name
Test status
Simulation time 350941179 ps
CPU time 6.24 seconds
Started Sep 11 04:51:11 AM UTC 24
Finished Sep 11 04:51:18 AM UTC 24
Peak memory 221316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324367744 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3324367744
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2578792501
Short name T115
Test name
Test status
Simulation time 293696480 ps
CPU time 74.55 seconds
Started Sep 11 05:09:04 AM UTC 24
Finished Sep 11 05:10:21 AM UTC 24
Peak memory 224532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578792501 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.2578792501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.999996697
Short name T98
Test name
Test status
Simulation time 2164437428 ps
CPU time 27.02 seconds
Started Sep 11 05:09:30 AM UTC 24
Finished Sep 11 05:09:58 AM UTC 24
Peak memory 222440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999996697 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.999996697
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2569515036
Short name T89
Test name
Test status
Simulation time 368111913 ps
CPU time 18.41 seconds
Started Sep 11 05:09:04 AM UTC 24
Finished Sep 11 05:09:23 AM UTC 24
Peak memory 222304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569515036 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.2569515036
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3181214225
Short name T16
Test name
Test status
Simulation time 7268223868 ps
CPU time 241.96 seconds
Started Sep 11 04:56:30 AM UTC 24
Finished Sep 11 05:00:36 AM UTC 24
Peak memory 232912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3181214225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.rom_ctrl_stress_all_with_rand_reset.3181214225
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.2634031497
Short name T70
Test name
Test status
Simulation time 227411858 ps
CPU time 18.43 seconds
Started Sep 11 04:52:32 AM UTC 24
Finished Sep 11 04:52:51 AM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263403149
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.2634031497
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.3037592835
Short name T32
Test name
Test status
Simulation time 1380864879 ps
CPU time 28.28 seconds
Started Sep 11 04:51:25 AM UTC 24
Finished Sep 11 04:51:55 AM UTC 24
Peak memory 225560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303759283
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.3037592835
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4110831949
Short name T367
Test name
Test status
Simulation time 134159178 ps
CPU time 7.19 seconds
Started Sep 11 05:09:04 AM UTC 24
Finished Sep 11 05:09:12 AM UTC 24
Peak memory 229760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110831949 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.4110831949
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.701042153
Short name T369
Test name
Test status
Simulation time 271926818 ps
CPU time 7.71 seconds
Started Sep 11 05:09:04 AM UTC 24
Finished Sep 11 05:09:13 AM UTC 24
Peak memory 221772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701042153 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.701042153
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1439223355
Short name T73
Test name
Test status
Simulation time 847928727 ps
CPU time 6.21 seconds
Started Sep 11 05:09:04 AM UTC 24
Finished Sep 11 05:09:11 AM UTC 24
Peak memory 229828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1439223355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
om_ctrl_csr_mem_rw_with_rand_reset.1439223355
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.797817364
Short name T107
Test name
Test status
Simulation time 2063785638 ps
CPU time 6.53 seconds
Started Sep 11 05:09:04 AM UTC 24
Finished Sep 11 05:09:12 AM UTC 24
Peak memory 229692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797817364 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.797817364
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3275339960
Short name T363
Test name
Test status
Simulation time 499234122 ps
CPU time 5.62 seconds
Started Sep 11 05:09:04 AM UTC 24
Finished Sep 11 05:09:11 AM UTC 24
Peak memory 222164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275339960 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.3275339960
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2872197989
Short name T364
Test name
Test status
Simulation time 130581150 ps
CPU time 5.83 seconds
Started Sep 11 05:09:04 AM UTC 24
Finished Sep 11 05:09:11 AM UTC 24
Peak memory 222280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872197989 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.2872197989
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2439327312
Short name T71
Test name
Test status
Simulation time 1553736305 ps
CPU time 5.29 seconds
Started Sep 11 05:09:04 AM UTC 24
Finished Sep 11 05:09:10 AM UTC 24
Peak memory 222404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439327312 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.2439327312
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2980177976
Short name T370
Test name
Test status
Simulation time 126488943 ps
CPU time 8.11 seconds
Started Sep 11 05:09:04 AM UTC 24
Finished Sep 11 05:09:13 AM UTC 24
Peak memory 229560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980177976 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2980177976
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2584179103
Short name T116
Test name
Test status
Simulation time 568597227 ps
CPU time 77.62 seconds
Started Sep 11 05:09:04 AM UTC 24
Finished Sep 11 05:10:23 AM UTC 24
Peak memory 224404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584179103 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.2584179103
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1985491111
Short name T79
Test name
Test status
Simulation time 308716410 ps
CPU time 4.77 seconds
Started Sep 11 05:09:07 AM UTC 24
Finished Sep 11 05:09:13 AM UTC 24
Peak memory 222404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985491111 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.1985491111
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.467673659
Short name T365
Test name
Test status
Simulation time 98631999 ps
CPU time 5.15 seconds
Started Sep 11 05:09:05 AM UTC 24
Finished Sep 11 05:09:12 AM UTC 24
Peak memory 222416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467673659 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.467673659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1519056159
Short name T108
Test name
Test status
Simulation time 1254309620 ps
CPU time 7.31 seconds
Started Sep 11 05:09:05 AM UTC 24
Finished Sep 11 05:09:14 AM UTC 24
Peak memory 222340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519056159 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.1519056159
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.177570723
Short name T375
Test name
Test status
Simulation time 853600986 ps
CPU time 6.29 seconds
Started Sep 11 05:09:11 AM UTC 24
Finished Sep 11 05:09:19 AM UTC 24
Peak memory 229680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=177570723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.ro
m_ctrl_csr_mem_rw_with_rand_reset.177570723
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.970970720
Short name T78
Test name
Test status
Simulation time 334071846 ps
CPU time 6.19 seconds
Started Sep 11 05:09:05 AM UTC 24
Finished Sep 11 05:09:12 AM UTC 24
Peak memory 222348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970970720 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.970970720
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1862730378
Short name T368
Test name
Test status
Simulation time 499605892 ps
CPU time 6.13 seconds
Started Sep 11 05:09:05 AM UTC 24
Finished Sep 11 05:09:12 AM UTC 24
Peak memory 222164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862730378 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.1862730378
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2209255902
Short name T366
Test name
Test status
Simulation time 288185864 ps
CPU time 5.59 seconds
Started Sep 11 05:09:05 AM UTC 24
Finished Sep 11 05:09:12 AM UTC 24
Peak memory 222280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209255902 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.2209255902
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1853186944
Short name T94
Test name
Test status
Simulation time 1630847004 ps
CPU time 34.99 seconds
Started Sep 11 05:09:04 AM UTC 24
Finished Sep 11 05:09:40 AM UTC 24
Peak memory 222376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853186944 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.1853186944
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3077427433
Short name T102
Test name
Test status
Simulation time 333040545 ps
CPU time 7.45 seconds
Started Sep 11 05:09:08 AM UTC 24
Finished Sep 11 05:09:17 AM UTC 24
Peak memory 222340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077427433 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.3077427433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2488366905
Short name T371
Test name
Test status
Simulation time 135356539 ps
CPU time 8.27 seconds
Started Sep 11 05:09:04 AM UTC 24
Finished Sep 11 05:09:13 AM UTC 24
Peak memory 228456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488366905 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2488366905
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2757089340
Short name T410
Test name
Test status
Simulation time 504884057 ps
CPU time 8.25 seconds
Started Sep 11 05:09:31 AM UTC 24
Finished Sep 11 05:09:40 AM UTC 24
Peak memory 229828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2757089340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rom_ctrl_csr_mem_rw_with_rand_reset.2757089340
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3666717389
Short name T403
Test name
Test status
Simulation time 346308742 ps
CPU time 5.94 seconds
Started Sep 11 05:09:30 AM UTC 24
Finished Sep 11 05:09:37 AM UTC 24
Peak memory 222344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666717389 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3666717389
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4132750897
Short name T405
Test name
Test status
Simulation time 130293415 ps
CPU time 6.03 seconds
Started Sep 11 05:09:31 AM UTC 24
Finished Sep 11 05:09:38 AM UTC 24
Peak memory 222328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132750897 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.4132750897
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.661630047
Short name T411
Test name
Test status
Simulation time 148036216 ps
CPU time 9.8 seconds
Started Sep 11 05:09:30 AM UTC 24
Finished Sep 11 05:09:41 AM UTC 24
Peak memory 226476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661630047 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.661630047
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1985813208
Short name T114
Test name
Test status
Simulation time 304421990 ps
CPU time 47.21 seconds
Started Sep 11 05:09:30 AM UTC 24
Finished Sep 11 05:10:19 AM UTC 24
Peak memory 222352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985813208 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.1985813208
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4154697425
Short name T407
Test name
Test status
Simulation time 369096162 ps
CPU time 4.82 seconds
Started Sep 11 05:09:33 AM UTC 24
Finished Sep 11 05:09:39 AM UTC 24
Peak memory 229764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4154697425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
rom_ctrl_csr_mem_rw_with_rand_reset.4154697425
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3482371205
Short name T406
Test name
Test status
Simulation time 89224880 ps
CPU time 4.25 seconds
Started Sep 11 05:09:33 AM UTC 24
Finished Sep 11 05:09:39 AM UTC 24
Peak memory 222200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482371205 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3482371205
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3749796139
Short name T452
Test name
Test status
Simulation time 1269129408 ps
CPU time 38.75 seconds
Started Sep 11 05:09:32 AM UTC 24
Finished Sep 11 05:10:12 AM UTC 24
Peak memory 222380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749796139 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.3749796139
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.948364260
Short name T409
Test name
Test status
Simulation time 829948642 ps
CPU time 5.18 seconds
Started Sep 11 05:09:33 AM UTC 24
Finished Sep 11 05:09:40 AM UTC 24
Peak memory 222352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948364260 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.948364260
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.710676234
Short name T414
Test name
Test status
Simulation time 1392181113 ps
CPU time 9.67 seconds
Started Sep 11 05:09:32 AM UTC 24
Finished Sep 11 05:09:43 AM UTC 24
Peak memory 228524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710676234 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.710676234
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2045435591
Short name T112
Test name
Test status
Simulation time 1189610290 ps
CPU time 45.65 seconds
Started Sep 11 05:09:32 AM UTC 24
Finished Sep 11 05:10:20 AM UTC 24
Peak memory 224400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045435591 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.2045435591
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3011691603
Short name T415
Test name
Test status
Simulation time 361684705 ps
CPU time 5.34 seconds
Started Sep 11 05:09:37 AM UTC 24
Finished Sep 11 05:09:43 AM UTC 24
Peak memory 229768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3011691603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rom_ctrl_csr_mem_rw_with_rand_reset.3011691603
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2673895362
Short name T413
Test name
Test status
Simulation time 521431102 ps
CPU time 6.06 seconds
Started Sep 11 05:09:36 AM UTC 24
Finished Sep 11 05:09:43 AM UTC 24
Peak memory 229764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673895362 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2673895362
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1058755939
Short name T448
Test name
Test status
Simulation time 3149282455 ps
CPU time 31.77 seconds
Started Sep 11 05:09:34 AM UTC 24
Finished Sep 11 05:10:08 AM UTC 24
Peak memory 222448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058755939 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.1058755939
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1714277262
Short name T412
Test name
Test status
Simulation time 90245609 ps
CPU time 4.86 seconds
Started Sep 11 05:09:37 AM UTC 24
Finished Sep 11 05:09:43 AM UTC 24
Peak memory 229740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714277262 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.1714277262
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3159983836
Short name T416
Test name
Test status
Simulation time 118142843 ps
CPU time 8.73 seconds
Started Sep 11 05:09:36 AM UTC 24
Finished Sep 11 05:09:45 AM UTC 24
Peak memory 226400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159983836 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3159983836
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.7196521
Short name T118
Test name
Test status
Simulation time 567775273 ps
CPU time 38.96 seconds
Started Sep 11 05:09:36 AM UTC 24
Finished Sep 11 05:10:16 AM UTC 24
Peak memory 222352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7196521 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.7196521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3938664265
Short name T419
Test name
Test status
Simulation time 95226807 ps
CPU time 7.65 seconds
Started Sep 11 05:09:39 AM UTC 24
Finished Sep 11 05:09:48 AM UTC 24
Peak memory 229740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3938664265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
rom_ctrl_csr_mem_rw_with_rand_reset.3938664265
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.225655785
Short name T100
Test name
Test status
Simulation time 87096877 ps
CPU time 6.12 seconds
Started Sep 11 05:09:38 AM UTC 24
Finished Sep 11 05:09:45 AM UTC 24
Peak memory 222272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225655785 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.225655785
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4194512171
Short name T445
Test name
Test status
Simulation time 2092340856 ps
CPU time 25.35 seconds
Started Sep 11 05:09:37 AM UTC 24
Finished Sep 11 05:10:03 AM UTC 24
Peak memory 222384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194512171 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.4194512171
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3373186322
Short name T417
Test name
Test status
Simulation time 142657093 ps
CPU time 5.34 seconds
Started Sep 11 05:09:39 AM UTC 24
Finished Sep 11 05:09:46 AM UTC 24
Peak memory 227752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373186322 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.3373186322
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4262464451
Short name T423
Test name
Test status
Simulation time 832493172 ps
CPU time 10.88 seconds
Started Sep 11 05:09:38 AM UTC 24
Finished Sep 11 05:09:50 AM UTC 24
Peak memory 226400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262464451 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.4262464451
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3999651382
Short name T120
Test name
Test status
Simulation time 472229393 ps
CPU time 71.9 seconds
Started Sep 11 05:09:38 AM UTC 24
Finished Sep 11 05:10:52 AM UTC 24
Peak memory 224328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999651382 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.3999651382
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.230260652
Short name T426
Test name
Test status
Simulation time 851130888 ps
CPU time 9.03 seconds
Started Sep 11 05:09:42 AM UTC 24
Finished Sep 11 05:09:52 AM UTC 24
Peak memory 229956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=230260652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.r
om_ctrl_csr_mem_rw_with_rand_reset.230260652
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1284457085
Short name T420
Test name
Test status
Simulation time 127398203 ps
CPU time 7.23 seconds
Started Sep 11 05:09:41 AM UTC 24
Finished Sep 11 05:09:49 AM UTC 24
Peak memory 222344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284457085 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1284457085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3868790659
Short name T449
Test name
Test status
Simulation time 2211011399 ps
CPU time 27.8 seconds
Started Sep 11 05:09:39 AM UTC 24
Finished Sep 11 05:10:08 AM UTC 24
Peak memory 222380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868790659 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.3868790659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3434731403
Short name T418
Test name
Test status
Simulation time 239056443 ps
CPU time 5.6 seconds
Started Sep 11 05:09:41 AM UTC 24
Finished Sep 11 05:09:47 AM UTC 24
Peak memory 229244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434731403 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.3434731403
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1994294437
Short name T424
Test name
Test status
Simulation time 521046255 ps
CPU time 8.96 seconds
Started Sep 11 05:09:40 AM UTC 24
Finished Sep 11 05:09:50 AM UTC 24
Peak memory 228520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994294437 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1994294437
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3776075927
Short name T460
Test name
Test status
Simulation time 760703385 ps
CPU time 83.8 seconds
Started Sep 11 05:09:41 AM UTC 24
Finished Sep 11 05:11:06 AM UTC 24
Peak memory 224464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776075927 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.3776075927
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.329570780
Short name T430
Test name
Test status
Simulation time 363282306 ps
CPU time 8.91 seconds
Started Sep 11 05:09:44 AM UTC 24
Finished Sep 11 05:09:54 AM UTC 24
Peak memory 229756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=329570780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.r
om_ctrl_csr_mem_rw_with_rand_reset.329570780
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.583396793
Short name T421
Test name
Test status
Simulation time 88417609 ps
CPU time 4.95 seconds
Started Sep 11 05:09:43 AM UTC 24
Finished Sep 11 05:09:49 AM UTC 24
Peak memory 222272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583396793 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.583396793
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1323447898
Short name T443
Test name
Test status
Simulation time 367782893 ps
CPU time 19.6 seconds
Started Sep 11 05:09:42 AM UTC 24
Finished Sep 11 05:10:03 AM UTC 24
Peak memory 222384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323447898 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.1323447898
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.907665085
Short name T427
Test name
Test status
Simulation time 291559008 ps
CPU time 7.22 seconds
Started Sep 11 05:09:44 AM UTC 24
Finished Sep 11 05:09:52 AM UTC 24
Peak memory 222288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907665085 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.907665085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1883349710
Short name T422
Test name
Test status
Simulation time 381160496 ps
CPU time 6.68 seconds
Started Sep 11 05:09:42 AM UTC 24
Finished Sep 11 05:09:50 AM UTC 24
Peak memory 228580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883349710 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1883349710
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.293207791
Short name T458
Test name
Test status
Simulation time 1056439661 ps
CPU time 74.49 seconds
Started Sep 11 05:09:42 AM UTC 24
Finished Sep 11 05:10:58 AM UTC 24
Peak memory 224320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293207791 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.293207791
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.527907121
Short name T429
Test name
Test status
Simulation time 401647277 ps
CPU time 5.43 seconds
Started Sep 11 05:09:47 AM UTC 24
Finished Sep 11 05:09:54 AM UTC 24
Peak memory 229760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=527907121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.r
om_ctrl_csr_mem_rw_with_rand_reset.527907121
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.665614520
Short name T431
Test name
Test status
Simulation time 500704323 ps
CPU time 7.17 seconds
Started Sep 11 05:09:46 AM UTC 24
Finished Sep 11 05:09:55 AM UTC 24
Peak memory 222280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665614520 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.665614520
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2486419064
Short name T450
Test name
Test status
Simulation time 717970705 ps
CPU time 23.46 seconds
Started Sep 11 05:09:44 AM UTC 24
Finished Sep 11 05:10:09 AM UTC 24
Peak memory 222448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486419064 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.2486419064
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1843030533
Short name T428
Test name
Test status
Simulation time 91522079 ps
CPU time 4.93 seconds
Started Sep 11 05:09:47 AM UTC 24
Finished Sep 11 05:09:53 AM UTC 24
Peak memory 222344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843030533 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.1843030533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1429751281
Short name T432
Test name
Test status
Simulation time 251575104 ps
CPU time 9.41 seconds
Started Sep 11 05:09:46 AM UTC 24
Finished Sep 11 05:09:57 AM UTC 24
Peak memory 228524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429751281 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1429751281
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1402077823
Short name T459
Test name
Test status
Simulation time 1140703047 ps
CPU time 76.93 seconds
Started Sep 11 05:09:46 AM UTC 24
Finished Sep 11 05:11:05 AM UTC 24
Peak memory 224400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402077823 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.1402077823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3411943880
Short name T442
Test name
Test status
Simulation time 509485663 ps
CPU time 10.61 seconds
Started Sep 11 05:09:50 AM UTC 24
Finished Sep 11 05:10:01 AM UTC 24
Peak memory 224392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3411943880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rom_ctrl_csr_mem_rw_with_rand_reset.3411943880
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.842970299
Short name T433
Test name
Test status
Simulation time 1656380803 ps
CPU time 6.45 seconds
Started Sep 11 05:09:50 AM UTC 24
Finished Sep 11 05:09:57 AM UTC 24
Peak memory 222408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842970299 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.842970299
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4199622571
Short name T451
Test name
Test status
Simulation time 1629822541 ps
CPU time 21.35 seconds
Started Sep 11 05:09:47 AM UTC 24
Finished Sep 11 05:10:10 AM UTC 24
Peak memory 222308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199622571 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.4199622571
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1000667685
Short name T436
Test name
Test status
Simulation time 142949500 ps
CPU time 7.47 seconds
Started Sep 11 05:09:50 AM UTC 24
Finished Sep 11 05:09:58 AM UTC 24
Peak memory 229768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000667685 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.1000667685
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2348492783
Short name T437
Test name
Test status
Simulation time 127838872 ps
CPU time 9.57 seconds
Started Sep 11 05:09:49 AM UTC 24
Finished Sep 11 05:09:59 AM UTC 24
Peak memory 226472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348492783 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2348492783
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2332453121
Short name T456
Test name
Test status
Simulation time 319399242 ps
CPU time 42.91 seconds
Started Sep 11 05:09:49 AM UTC 24
Finished Sep 11 05:10:33 AM UTC 24
Peak memory 224400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332453121 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.2332453121
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2649786107
Short name T441
Test name
Test status
Simulation time 215282866 ps
CPU time 7.6 seconds
Started Sep 11 05:09:52 AM UTC 24
Finished Sep 11 05:10:01 AM UTC 24
Peak memory 229740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2649786107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rom_ctrl_csr_mem_rw_with_rand_reset.2649786107
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.210468733
Short name T435
Test name
Test status
Simulation time 89156204 ps
CPU time 6.02 seconds
Started Sep 11 05:09:51 AM UTC 24
Finished Sep 11 05:09:58 AM UTC 24
Peak memory 222408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210468733 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.210468733
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1216143138
Short name T454
Test name
Test status
Simulation time 1589051520 ps
CPU time 35.94 seconds
Started Sep 11 05:09:51 AM UTC 24
Finished Sep 11 05:10:28 AM UTC 24
Peak memory 222380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216143138 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.1216143138
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.832910099
Short name T440
Test name
Test status
Simulation time 92455498 ps
CPU time 7.61 seconds
Started Sep 11 05:09:52 AM UTC 24
Finished Sep 11 05:10:01 AM UTC 24
Peak memory 222276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832910099 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.832910099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3678833061
Short name T438
Test name
Test status
Simulation time 350403462 ps
CPU time 7.58 seconds
Started Sep 11 05:09:51 AM UTC 24
Finished Sep 11 05:10:00 AM UTC 24
Peak memory 228524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678833061 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3678833061
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.933129303
Short name T457
Test name
Test status
Simulation time 2470316763 ps
CPU time 42.82 seconds
Started Sep 11 05:09:51 AM UTC 24
Finished Sep 11 05:10:35 AM UTC 24
Peak memory 222468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933129303 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.933129303
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3955604868
Short name T446
Test name
Test status
Simulation time 143619089 ps
CPU time 6.83 seconds
Started Sep 11 05:09:56 AM UTC 24
Finished Sep 11 05:10:04 AM UTC 24
Peak memory 229692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3955604868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rom_ctrl_csr_mem_rw_with_rand_reset.3955604868
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4094158746
Short name T439
Test name
Test status
Simulation time 85533737 ps
CPU time 5.15 seconds
Started Sep 11 05:09:54 AM UTC 24
Finished Sep 11 05:10:01 AM UTC 24
Peak memory 222344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094158746 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4094158746
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3056155663
Short name T453
Test name
Test status
Simulation time 1083960279 ps
CPU time 29.13 seconds
Started Sep 11 05:09:53 AM UTC 24
Finished Sep 11 05:10:24 AM UTC 24
Peak memory 222380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056155663 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.3056155663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3685008359
Short name T444
Test name
Test status
Simulation time 250727802 ps
CPU time 7.07 seconds
Started Sep 11 05:09:55 AM UTC 24
Finished Sep 11 05:10:03 AM UTC 24
Peak memory 222272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685008359 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.3685008359
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4014594540
Short name T447
Test name
Test status
Simulation time 546549538 ps
CPU time 10.3 seconds
Started Sep 11 05:09:54 AM UTC 24
Finished Sep 11 05:10:06 AM UTC 24
Peak memory 229864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014594540 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4014594540
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.522213387
Short name T122
Test name
Test status
Simulation time 888079553 ps
CPU time 81.78 seconds
Started Sep 11 05:09:54 AM UTC 24
Finished Sep 11 05:11:18 AM UTC 24
Peak memory 229888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522213387 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.522213387
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1027070140
Short name T80
Test name
Test status
Simulation time 87967643 ps
CPU time 4.41 seconds
Started Sep 11 05:09:13 AM UTC 24
Finished Sep 11 05:09:19 AM UTC 24
Peak memory 222276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027070140 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.1027070140
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2963466793
Short name T377
Test name
Test status
Simulation time 133011305 ps
CPU time 6.44 seconds
Started Sep 11 05:09:13 AM UTC 24
Finished Sep 11 05:09:21 AM UTC 24
Peak memory 222352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963466793 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.2963466793
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1400441196
Short name T81
Test name
Test status
Simulation time 359225513 ps
CPU time 5.98 seconds
Started Sep 11 05:09:13 AM UTC 24
Finished Sep 11 05:09:20 AM UTC 24
Peak memory 222272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400441196 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.1400441196
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1068461444
Short name T378
Test name
Test status
Simulation time 546463692 ps
CPU time 5.26 seconds
Started Sep 11 05:09:14 AM UTC 24
Finished Sep 11 05:09:21 AM UTC 24
Peak memory 229764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1068461444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r
om_ctrl_csr_mem_rw_with_rand_reset.1068461444
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.710772008
Short name T372
Test name
Test status
Simulation time 639666995 ps
CPU time 4.1 seconds
Started Sep 11 05:09:13 AM UTC 24
Finished Sep 11 05:09:18 AM UTC 24
Peak memory 222412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710772008 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.710772008
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.414365568
Short name T374
Test name
Test status
Simulation time 125995742 ps
CPU time 4.62 seconds
Started Sep 11 05:09:13 AM UTC 24
Finished Sep 11 05:09:19 AM UTC 24
Peak memory 222156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414365568 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.414365568
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.646057592
Short name T373
Test name
Test status
Simulation time 217348924 ps
CPU time 4.18 seconds
Started Sep 11 05:09:13 AM UTC 24
Finished Sep 11 05:09:18 AM UTC 24
Peak memory 222272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646057592 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.646057592
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.65429574
Short name T408
Test name
Test status
Simulation time 570188291 ps
CPU time 26.61 seconds
Started Sep 11 05:09:11 AM UTC 24
Finished Sep 11 05:09:39 AM UTC 24
Peak memory 222072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65429574 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.65429574
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1887109646
Short name T85
Test name
Test status
Simulation time 499785862 ps
CPU time 7.01 seconds
Started Sep 11 05:09:14 AM UTC 24
Finished Sep 11 05:09:22 AM UTC 24
Peak memory 222340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887109646 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.1887109646
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2954009879
Short name T379
Test name
Test status
Simulation time 250667497 ps
CPU time 7.85 seconds
Started Sep 11 05:09:11 AM UTC 24
Finished Sep 11 05:09:21 AM UTC 24
Peak memory 229804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954009879 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2954009879
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.587814819
Short name T109
Test name
Test status
Simulation time 126537594 ps
CPU time 4.37 seconds
Started Sep 11 05:09:14 AM UTC 24
Finished Sep 11 05:09:20 AM UTC 24
Peak memory 222416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587814819 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.587814819
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2595343027
Short name T381
Test name
Test status
Simulation time 436655243 ps
CPU time 5.85 seconds
Started Sep 11 05:09:14 AM UTC 24
Finished Sep 11 05:09:22 AM UTC 24
Peak memory 222352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595343027 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.2595343027
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2880554344
Short name T385
Test name
Test status
Simulation time 325117029 ps
CPU time 8.12 seconds
Started Sep 11 05:09:14 AM UTC 24
Finished Sep 11 05:09:24 AM UTC 24
Peak memory 229760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880554344 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.2880554344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2217228269
Short name T384
Test name
Test status
Simulation time 458235585 ps
CPU time 6 seconds
Started Sep 11 05:09:15 AM UTC 24
Finished Sep 11 05:09:23 AM UTC 24
Peak memory 229764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2217228269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
om_ctrl_csr_mem_rw_with_rand_reset.2217228269
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.333073189
Short name T82
Test name
Test status
Simulation time 518406871 ps
CPU time 6.39 seconds
Started Sep 11 05:09:14 AM UTC 24
Finished Sep 11 05:09:22 AM UTC 24
Peak memory 229768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333073189 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.333073189
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2952866819
Short name T376
Test name
Test status
Simulation time 131538101 ps
CPU time 4.89 seconds
Started Sep 11 05:09:14 AM UTC 24
Finished Sep 11 05:09:20 AM UTC 24
Peak memory 222092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952866819 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.2952866819
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.296949196
Short name T380
Test name
Test status
Simulation time 311596035 ps
CPU time 5.9 seconds
Started Sep 11 05:09:14 AM UTC 24
Finished Sep 11 05:09:21 AM UTC 24
Peak memory 222212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296949196 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.296949196
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3718639408
Short name T96
Test name
Test status
Simulation time 3125632787 ps
CPU time 30.91 seconds
Started Sep 11 05:09:14 AM UTC 24
Finished Sep 11 05:09:47 AM UTC 24
Peak memory 222440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718639408 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.3718639408
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.591257522
Short name T83
Test name
Test status
Simulation time 87436997 ps
CPU time 5.75 seconds
Started Sep 11 05:09:15 AM UTC 24
Finished Sep 11 05:09:22 AM UTC 24
Peak memory 222420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591257522 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.591257522
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1128335111
Short name T386
Test name
Test status
Simulation time 250559738 ps
CPU time 8.25 seconds
Started Sep 11 05:09:14 AM UTC 24
Finished Sep 11 05:09:24 AM UTC 24
Peak memory 229804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128335111 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1128335111
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.334555240
Short name T387
Test name
Test status
Simulation time 127612328 ps
CPU time 5.84 seconds
Started Sep 11 05:09:18 AM UTC 24
Finished Sep 11 05:09:25 AM UTC 24
Peak memory 229772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334555240 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.334555240
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2614040351
Short name T84
Test name
Test status
Simulation time 88853560 ps
CPU time 4.77 seconds
Started Sep 11 05:09:17 AM UTC 24
Finished Sep 11 05:09:22 AM UTC 24
Peak memory 222276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614040351 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.2614040351
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3090228489
Short name T389
Test name
Test status
Simulation time 132581663 ps
CPU time 9.6 seconds
Started Sep 11 05:09:17 AM UTC 24
Finished Sep 11 05:09:27 AM UTC 24
Peak memory 229760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090228489 -assert nopostproc +UVM_T
ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.3090228489
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4153431175
Short name T388
Test name
Test status
Simulation time 597347051 ps
CPU time 5.8 seconds
Started Sep 11 05:09:19 AM UTC 24
Finished Sep 11 05:09:26 AM UTC 24
Peak memory 229764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4153431175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
om_ctrl_csr_mem_rw_with_rand_reset.4153431175
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2109775311
Short name T86
Test name
Test status
Simulation time 347456442 ps
CPU time 5.29 seconds
Started Sep 11 05:09:17 AM UTC 24
Finished Sep 11 05:09:23 AM UTC 24
Peak memory 222344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109775311 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2109775311
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3997146244
Short name T383
Test name
Test status
Simulation time 521670909 ps
CPU time 5.64 seconds
Started Sep 11 05:09:16 AM UTC 24
Finished Sep 11 05:09:22 AM UTC 24
Peak memory 222164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997146244 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.3997146244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.89673098
Short name T382
Test name
Test status
Simulation time 172382373 ps
CPU time 5.04 seconds
Started Sep 11 05:09:16 AM UTC 24
Finished Sep 11 05:09:22 AM UTC 24
Peak memory 222220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89673098 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.89673098
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1261757708
Short name T99
Test name
Test status
Simulation time 747699665 ps
CPU time 19.08 seconds
Started Sep 11 05:09:15 AM UTC 24
Finished Sep 11 05:09:36 AM UTC 24
Peak memory 222440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261757708 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.1261757708
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.601845390
Short name T103
Test name
Test status
Simulation time 172782232 ps
CPU time 4.62 seconds
Started Sep 11 05:09:19 AM UTC 24
Finished Sep 11 05:09:24 AM UTC 24
Peak memory 222420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601845390 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.601845390
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4265834421
Short name T391
Test name
Test status
Simulation time 630787495 ps
CPU time 11.47 seconds
Started Sep 11 05:09:15 AM UTC 24
Finished Sep 11 05:09:28 AM UTC 24
Peak memory 229800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265834421 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.4265834421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2969868468
Short name T66
Test name
Test status
Simulation time 444174706 ps
CPU time 37.06 seconds
Started Sep 11 05:09:16 AM UTC 24
Finished Sep 11 05:09:54 AM UTC 24
Peak memory 224404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969868468 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.2969868468
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.271716629
Short name T392
Test name
Test status
Simulation time 537801605 ps
CPU time 6 seconds
Started Sep 11 05:09:21 AM UTC 24
Finished Sep 11 05:09:28 AM UTC 24
Peak memory 229772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=271716629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ro
m_ctrl_csr_mem_rw_with_rand_reset.271716629
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3727425970
Short name T104
Test name
Test status
Simulation time 1787917001 ps
CPU time 5.39 seconds
Started Sep 11 05:09:21 AM UTC 24
Finished Sep 11 05:09:28 AM UTC 24
Peak memory 229764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727425970 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3727425970
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.878057772
Short name T97
Test name
Test status
Simulation time 6040657053 ps
CPU time 33.46 seconds
Started Sep 11 05:09:19 AM UTC 24
Finished Sep 11 05:09:54 AM UTC 24
Peak memory 222372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878057772 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.878057772
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2981275049
Short name T105
Test name
Test status
Simulation time 87333384 ps
CPU time 5.44 seconds
Started Sep 11 05:09:21 AM UTC 24
Finished Sep 11 05:09:28 AM UTC 24
Peak memory 222340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981275049 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.2981275049
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.50922303
Short name T390
Test name
Test status
Simulation time 88902091 ps
CPU time 7.68 seconds
Started Sep 11 05:09:19 AM UTC 24
Finished Sep 11 05:09:28 AM UTC 24
Peak memory 228516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50922303 -assert nopostproc +UVM_TESTNAME=rom
_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.50922303
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3111441754
Short name T455
Test name
Test status
Simulation time 836022755 ps
CPU time 69.96 seconds
Started Sep 11 05:09:20 AM UTC 24
Finished Sep 11 05:10:32 AM UTC 24
Peak memory 229832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111441754 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.3111441754
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3300370971
Short name T393
Test name
Test status
Simulation time 144994564 ps
CPU time 7.42 seconds
Started Sep 11 05:09:23 AM UTC 24
Finished Sep 11 05:09:31 AM UTC 24
Peak memory 224392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3300370971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r
om_ctrl_csr_mem_rw_with_rand_reset.3300370971
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2156709276
Short name T91
Test name
Test status
Simulation time 334513219 ps
CPU time 5.99 seconds
Started Sep 11 05:09:23 AM UTC 24
Finished Sep 11 05:09:30 AM UTC 24
Peak memory 222148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156709276 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2156709276
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4065495046
Short name T95
Test name
Test status
Simulation time 537786945 ps
CPU time 23.94 seconds
Started Sep 11 05:09:21 AM UTC 24
Finished Sep 11 05:09:46 AM UTC 24
Peak memory 222304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065495046 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.4065495046
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3353520706
Short name T106
Test name
Test status
Simulation time 132541280 ps
CPU time 5.04 seconds
Started Sep 11 05:09:23 AM UTC 24
Finished Sep 11 05:09:29 AM UTC 24
Peak memory 229700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353520706 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.3353520706
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2671120868
Short name T396
Test name
Test status
Simulation time 127204881 ps
CPU time 9.63 seconds
Started Sep 11 05:09:21 AM UTC 24
Finished Sep 11 05:09:32 AM UTC 24
Peak memory 229864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671120868 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2671120868
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4074120482
Short name T119
Test name
Test status
Simulation time 554574740 ps
CPU time 81.01 seconds
Started Sep 11 05:09:21 AM UTC 24
Finished Sep 11 05:10:44 AM UTC 24
Peak memory 224404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074120482 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.4074120482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3499663214
Short name T397
Test name
Test status
Simulation time 1323917832 ps
CPU time 7.2 seconds
Started Sep 11 05:09:24 AM UTC 24
Finished Sep 11 05:09:32 AM UTC 24
Peak memory 229764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3499663214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r
om_ctrl_csr_mem_rw_with_rand_reset.3499663214
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1344899082
Short name T90
Test name
Test status
Simulation time 175339105 ps
CPU time 4.26 seconds
Started Sep 11 05:09:24 AM UTC 24
Finished Sep 11 05:09:29 AM UTC 24
Peak memory 229764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344899082 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1344899082
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1415252438
Short name T101
Test name
Test status
Simulation time 537868322 ps
CPU time 22.22 seconds
Started Sep 11 05:09:23 AM UTC 24
Finished Sep 11 05:09:46 AM UTC 24
Peak memory 222304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415252438 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.1415252438
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4224211641
Short name T395
Test name
Test status
Simulation time 130403152 ps
CPU time 6.69 seconds
Started Sep 11 05:09:24 AM UTC 24
Finished Sep 11 05:09:32 AM UTC 24
Peak memory 222340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224211641 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.4224211641
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.40372031
Short name T399
Test name
Test status
Simulation time 88200584 ps
CPU time 8.62 seconds
Started Sep 11 05:09:24 AM UTC 24
Finished Sep 11 05:09:33 AM UTC 24
Peak memory 228516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40372031 -assert nopostproc +UVM_TESTNAME=rom
_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.40372031
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3253951853
Short name T121
Test name
Test status
Simulation time 1407787137 ps
CPU time 81.82 seconds
Started Sep 11 05:09:24 AM UTC 24
Finished Sep 11 05:10:48 AM UTC 24
Peak memory 224468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253951853 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.3253951853
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3615305706
Short name T394
Test name
Test status
Simulation time 100786798 ps
CPU time 5.04 seconds
Started Sep 11 05:09:25 AM UTC 24
Finished Sep 11 05:09:31 AM UTC 24
Peak memory 229896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3615305706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
om_ctrl_csr_mem_rw_with_rand_reset.3615305706
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.317162289
Short name T92
Test name
Test status
Simulation time 88918940 ps
CPU time 4.29 seconds
Started Sep 11 05:09:25 AM UTC 24
Finished Sep 11 05:09:30 AM UTC 24
Peak memory 222348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317162289 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.317162289
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1689188153
Short name T425
Test name
Test status
Simulation time 4889726279 ps
CPU time 26.48 seconds
Started Sep 11 05:09:24 AM UTC 24
Finished Sep 11 05:09:52 AM UTC 24
Peak memory 222368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689188153 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.1689188153
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1779753636
Short name T398
Test name
Test status
Simulation time 2477215030 ps
CPU time 6.64 seconds
Started Sep 11 05:09:25 AM UTC 24
Finished Sep 11 05:09:33 AM UTC 24
Peak memory 222340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779753636 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.1779753636
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1937551446
Short name T400
Test name
Test status
Simulation time 361286228 ps
CPU time 10.69 seconds
Started Sep 11 05:09:24 AM UTC 24
Finished Sep 11 05:09:36 AM UTC 24
Peak memory 228588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937551446 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1937551446
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1329993519
Short name T113
Test name
Test status
Simulation time 1163653376 ps
CPU time 71.54 seconds
Started Sep 11 05:09:25 AM UTC 24
Finished Sep 11 05:10:38 AM UTC 24
Peak memory 229768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329993519 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.1329993519
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.83359746
Short name T402
Test name
Test status
Simulation time 542411358 ps
CPU time 6.93 seconds
Started Sep 11 05:09:29 AM UTC 24
Finished Sep 11 05:09:37 AM UTC 24
Peak memory 229892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=83359746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom
_ctrl_csr_mem_rw_with_rand_reset.83359746
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2334783413
Short name T93
Test name
Test status
Simulation time 256595963 ps
CPU time 4.94 seconds
Started Sep 11 05:09:29 AM UTC 24
Finished Sep 11 05:09:35 AM UTC 24
Peak memory 222344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334783413 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2334783413
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2994561243
Short name T434
Test name
Test status
Simulation time 1129602661 ps
CPU time 30.11 seconds
Started Sep 11 05:09:26 AM UTC 24
Finished Sep 11 05:09:58 AM UTC 24
Peak memory 222376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994561243 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.2994561243
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3077144256
Short name T404
Test name
Test status
Simulation time 1566983423 ps
CPU time 7.22 seconds
Started Sep 11 05:09:29 AM UTC 24
Finished Sep 11 05:09:37 AM UTC 24
Peak memory 228824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077144256 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.3077144256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.570069550
Short name T401
Test name
Test status
Simulation time 169080171 ps
CPU time 7.9 seconds
Started Sep 11 05:09:27 AM UTC 24
Finished Sep 11 05:09:36 AM UTC 24
Peak memory 228528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570069550 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.570069550
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1287278640
Short name T68
Test name
Test status
Simulation time 631930161 ps
CPU time 44 seconds
Started Sep 11 05:09:29 AM UTC 24
Finished Sep 11 05:10:14 AM UTC 24
Peak memory 229844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287278640 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.1287278640
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3663736037
Short name T23
Test name
Test status
Simulation time 2191487199 ps
CPU time 139.99 seconds
Started Sep 11 04:51:10 AM UTC 24
Finished Sep 11 04:53:32 AM UTC 24
Peak memory 253236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663736037 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.3663736037
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.3685020100
Short name T9
Test name
Test status
Simulation time 195533618 ps
CPU time 14.5 seconds
Started Sep 11 04:51:10 AM UTC 24
Finished Sep 11 04:51:26 AM UTC 24
Peak memory 221348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685020100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3685020100
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.4225257187
Short name T1
Test name
Test status
Simulation time 203262110 ps
CPU time 6.57 seconds
Started Sep 11 04:51:10 AM UTC 24
Finished Sep 11 04:51:18 AM UTC 24
Peak memory 221648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225257187 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4225257187
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.1705575433
Short name T2
Test name
Test status
Simulation time 186644042 ps
CPU time 7.84 seconds
Started Sep 11 04:51:09 AM UTC 24
Finished Sep 11 04:51:18 AM UTC 24
Peak memory 223384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705575433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1705575433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.897498744
Short name T13
Test name
Test status
Simulation time 3542987671 ps
CPU time 108.55 seconds
Started Sep 11 04:51:10 AM UTC 24
Finished Sep 11 04:53:01 AM UTC 24
Peak memory 233104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=897498744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.rom_ctrl_stress_all_with_rand_reset.897498744
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.2759120243
Short name T4
Test name
Test status
Simulation time 130939411 ps
CPU time 6.42 seconds
Started Sep 11 04:51:13 AM UTC 24
Finished Sep 11 04:51:20 AM UTC 24
Peak memory 221316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759120243 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2759120243
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2759844017
Short name T22
Test name
Test status
Simulation time 6355862938 ps
CPU time 134.08 seconds
Started Sep 11 04:51:11 AM UTC 24
Finished Sep 11 04:53:28 AM UTC 24
Peak memory 257420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759844017 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.2759844017
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3826141017
Short name T6
Test name
Test status
Simulation time 141678455 ps
CPU time 8.86 seconds
Started Sep 11 04:51:11 AM UTC 24
Finished Sep 11 04:51:21 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826141017 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3826141017
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1214415094
Short name T24
Test name
Test status
Simulation time 218548827 ps
CPU time 59.81 seconds
Started Sep 11 04:51:11 AM UTC 24
Finished Sep 11 04:52:13 AM UTC 24
Peak memory 257528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214415094 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1214415094
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.3766038573
Short name T5
Test name
Test status
Simulation time 97249773 ps
CPU time 8.11 seconds
Started Sep 11 04:51:11 AM UTC 24
Finished Sep 11 04:51:20 AM UTC 24
Peak memory 221332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766038573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3766038573
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3680020684
Short name T272
Test name
Test status
Simulation time 19279987235 ps
CPU time 325.39 seconds
Started Sep 11 04:51:11 AM UTC 24
Finished Sep 11 04:56:41 AM UTC 24
Peak memory 246592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3680020684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3680020684
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.2443436657
Short name T140
Test name
Test status
Simulation time 347816637 ps
CPU time 6.43 seconds
Started Sep 11 04:52:40 AM UTC 24
Finished Sep 11 04:52:47 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443436657 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2443436657
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1850009388
Short name T179
Test name
Test status
Simulation time 7879177829 ps
CPU time 113.66 seconds
Started Sep 11 04:52:38 AM UTC 24
Finished Sep 11 04:54:33 AM UTC 24
Peak memory 223572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850009388 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.1850009388
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.2521837162
Short name T137
Test name
Test status
Simulation time 350791914 ps
CPU time 10.97 seconds
Started Sep 11 04:52:40 AM UTC 24
Finished Sep 11 04:52:52 AM UTC 24
Peak memory 221336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521837162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2521837162
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.2809554103
Short name T129
Test name
Test status
Simulation time 341745470 ps
CPU time 5.64 seconds
Started Sep 11 04:52:33 AM UTC 24
Finished Sep 11 04:52:39 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809554103 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2809554103
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2784450915
Short name T60
Test name
Test status
Simulation time 2575635915 ps
CPU time 66.29 seconds
Started Sep 11 04:52:40 AM UTC 24
Finished Sep 11 04:53:48 AM UTC 24
Peak memory 230864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2784450915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.rom_ctrl_stress_all_with_rand_reset.2784450915
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.423439056
Short name T138
Test name
Test status
Simulation time 656653245 ps
CPU time 7.18 seconds
Started Sep 11 04:52:52 AM UTC 24
Finished Sep 11 04:53:00 AM UTC 24
Peak memory 221308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423439056 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.423439056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.842617359
Short name T178
Test name
Test status
Simulation time 2182403083 ps
CPU time 100.63 seconds
Started Sep 11 04:52:48 AM UTC 24
Finished Sep 11 04:54:31 AM UTC 24
Peak memory 221532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842617359 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.842617359
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.4143916250
Short name T145
Test name
Test status
Simulation time 480656717 ps
CPU time 14.64 seconds
Started Sep 11 04:52:50 AM UTC 24
Finished Sep 11 04:53:06 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143916250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4143916250
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.2665314286
Short name T143
Test name
Test status
Simulation time 281862284 ps
CPU time 8.15 seconds
Started Sep 11 04:52:46 AM UTC 24
Finished Sep 11 04:52:55 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665314286 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2665314286
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3109796771
Short name T132
Test name
Test status
Simulation time 1140832862 ps
CPU time 16.69 seconds
Started Sep 11 04:52:45 AM UTC 24
Finished Sep 11 04:53:03 AM UTC 24
Peak memory 225504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310979677
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.3109796771
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.1823436607
Short name T134
Test name
Test status
Simulation time 89135085 ps
CPU time 6.28 seconds
Started Sep 11 04:53:02 AM UTC 24
Finished Sep 11 04:53:09 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823436607 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1823436607
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2853118000
Short name T172
Test name
Test status
Simulation time 1446646615 ps
CPU time 78.27 seconds
Started Sep 11 04:53:00 AM UTC 24
Finished Sep 11 04:54:21 AM UTC 24
Peak memory 244056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853118000 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.2853118000
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.1447237207
Short name T147
Test name
Test status
Simulation time 863419853 ps
CPU time 16.38 seconds
Started Sep 11 04:53:02 AM UTC 24
Finished Sep 11 04:53:19 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447237207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1447237207
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.2806988574
Short name T144
Test name
Test status
Simulation time 428806253 ps
CPU time 8.26 seconds
Started Sep 11 04:52:56 AM UTC 24
Finished Sep 11 04:53:06 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806988574 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2806988574
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.3075046853
Short name T142
Test name
Test status
Simulation time 378065007 ps
CPU time 20.62 seconds
Started Sep 11 04:52:55 AM UTC 24
Finished Sep 11 04:53:17 AM UTC 24
Peak memory 223472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307504685
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.3075046853
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3961615304
Short name T208
Test name
Test status
Simulation time 6835701798 ps
CPU time 138.97 seconds
Started Sep 11 04:53:02 AM UTC 24
Finished Sep 11 04:55:23 AM UTC 24
Peak memory 232748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3961615304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.rom_ctrl_stress_all_with_rand_reset.3961615304
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.684411515
Short name T148
Test name
Test status
Simulation time 347034028 ps
CPU time 5.82 seconds
Started Sep 11 04:53:14 AM UTC 24
Finished Sep 11 04:53:21 AM UTC 24
Peak memory 221308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684411515 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.684411515
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1907515946
Short name T52
Test name
Test status
Simulation time 1999378687 ps
CPU time 123.75 seconds
Started Sep 11 04:53:07 AM UTC 24
Finished Sep 11 04:55:13 AM UTC 24
Peak memory 257416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907515946 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.1907515946
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.2474987900
Short name T54
Test name
Test status
Simulation time 693534916 ps
CPU time 12.46 seconds
Started Sep 11 04:53:07 AM UTC 24
Finished Sep 11 04:53:20 AM UTC 24
Peak memory 221472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474987900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2474987900
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.4054970466
Short name T146
Test name
Test status
Simulation time 558614400 ps
CPU time 8.21 seconds
Started Sep 11 04:53:04 AM UTC 24
Finished Sep 11 04:53:13 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054970466 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4054970466
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.2178827699
Short name T133
Test name
Test status
Simulation time 390619700 ps
CPU time 18.44 seconds
Started Sep 11 04:53:03 AM UTC 24
Finished Sep 11 04:53:22 AM UTC 24
Peak memory 225776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217882769
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.2178827699
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3313793087
Short name T267
Test name
Test status
Simulation time 11658113147 ps
CPU time 199.82 seconds
Started Sep 11 04:53:10 AM UTC 24
Finished Sep 11 04:56:33 AM UTC 24
Peak memory 232912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3313793087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3313793087
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.2036334043
Short name T150
Test name
Test status
Simulation time 89461626 ps
CPU time 6.5 seconds
Started Sep 11 04:53:21 AM UTC 24
Finished Sep 11 04:53:29 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036334043 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2036334043
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3503803367
Short name T204
Test name
Test status
Simulation time 1528905268 ps
CPU time 118.68 seconds
Started Sep 11 04:53:18 AM UTC 24
Finished Sep 11 04:55:19 AM UTC 24
Peak memory 242012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503803367 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.3503803367
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.1855950892
Short name T55
Test name
Test status
Simulation time 517532661 ps
CPU time 12.88 seconds
Started Sep 11 04:53:20 AM UTC 24
Finished Sep 11 04:53:35 AM UTC 24
Peak memory 221336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855950892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1855950892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1894271021
Short name T149
Test name
Test status
Simulation time 139581697 ps
CPU time 6.35 seconds
Started Sep 11 04:53:17 AM UTC 24
Finished Sep 11 04:53:25 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894271021 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1894271021
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.4223766932
Short name T131
Test name
Test status
Simulation time 401137810 ps
CPU time 14.07 seconds
Started Sep 11 04:53:14 AM UTC 24
Finished Sep 11 04:53:29 AM UTC 24
Peak memory 225520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422376693
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.4223766932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1628824751
Short name T334
Test name
Test status
Simulation time 18492068104 ps
CPU time 295.24 seconds
Started Sep 11 04:53:21 AM UTC 24
Finished Sep 11 04:58:21 AM UTC 24
Peak memory 245200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1628824751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1628824751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.2684816891
Short name T152
Test name
Test status
Simulation time 126189268 ps
CPU time 7.28 seconds
Started Sep 11 04:53:30 AM UTC 24
Finished Sep 11 04:53:39 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684816891 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2684816891
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1265008074
Short name T226
Test name
Test status
Simulation time 26267349241 ps
CPU time 135.71 seconds
Started Sep 11 04:53:26 AM UTC 24
Finished Sep 11 04:55:44 AM UTC 24
Peak memory 245220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265008074 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.1265008074
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.1579419401
Short name T154
Test name
Test status
Simulation time 1040767460 ps
CPU time 16.55 seconds
Started Sep 11 04:53:28 AM UTC 24
Finished Sep 11 04:53:46 AM UTC 24
Peak memory 221336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579419401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1579419401
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.1507383586
Short name T151
Test name
Test status
Simulation time 635565946 ps
CPU time 7.71 seconds
Started Sep 11 04:53:25 AM UTC 24
Finished Sep 11 04:53:33 AM UTC 24
Peak memory 221520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507383586 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1507383586
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.2600436089
Short name T156
Test name
Test status
Simulation time 283728670 ps
CPU time 25.26 seconds
Started Sep 11 04:53:24 AM UTC 24
Finished Sep 11 04:53:50 AM UTC 24
Peak memory 227632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260043608
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.2600436089
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.4147546185
Short name T63
Test name
Test status
Simulation time 13096025748 ps
CPU time 65.98 seconds
Started Sep 11 04:53:29 AM UTC 24
Finished Sep 11 04:54:37 AM UTC 24
Peak memory 230928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4147546185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.rom_ctrl_stress_all_with_rand_reset.4147546185
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.2334154797
Short name T155
Test name
Test status
Simulation time 262200584 ps
CPU time 7.37 seconds
Started Sep 11 04:53:39 AM UTC 24
Finished Sep 11 04:53:48 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334154797 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2334154797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1606707171
Short name T197
Test name
Test status
Simulation time 3376343056 ps
CPU time 88.09 seconds
Started Sep 11 04:53:34 AM UTC 24
Finished Sep 11 04:55:04 AM UTC 24
Peak memory 223580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606707171 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.1606707171
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.526221532
Short name T157
Test name
Test status
Simulation time 697152791 ps
CPU time 14.55 seconds
Started Sep 11 04:53:34 AM UTC 24
Finished Sep 11 04:53:50 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526221532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.526221532
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.3600960008
Short name T153
Test name
Test status
Simulation time 1235415877 ps
CPU time 9.75 seconds
Started Sep 11 04:53:33 AM UTC 24
Finished Sep 11 04:53:44 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600960008 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3600960008
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.235862213
Short name T158
Test name
Test status
Simulation time 2332267036 ps
CPU time 19.39 seconds
Started Sep 11 04:53:30 AM UTC 24
Finished Sep 11 04:53:51 AM UTC 24
Peak memory 223528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235862213
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.235862213
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.52235916
Short name T213
Test name
Test status
Simulation time 2599607866 ps
CPU time 111.14 seconds
Started Sep 11 04:53:35 AM UTC 24
Finished Sep 11 04:55:29 AM UTC 24
Peak memory 241096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=52235916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 16.rom_ctrl_stress_all_with_rand_reset.52235916
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1547223631
Short name T160
Test name
Test status
Simulation time 178412407 ps
CPU time 6.21 seconds
Started Sep 11 04:53:51 AM UTC 24
Finished Sep 11 04:53:58 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547223631 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1547223631
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.220104310
Short name T231
Test name
Test status
Simulation time 13701884129 ps
CPU time 116.32 seconds
Started Sep 11 04:53:49 AM UTC 24
Finished Sep 11 04:55:47 AM UTC 24
Peak memory 253452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220104310 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.220104310
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.2250987014
Short name T163
Test name
Test status
Simulation time 177685244 ps
CPU time 14.72 seconds
Started Sep 11 04:53:49 AM UTC 24
Finished Sep 11 04:54:04 AM UTC 24
Peak memory 221464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250987014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2250987014
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.1272908083
Short name T159
Test name
Test status
Simulation time 1017019418 ps
CPU time 9.6 seconds
Started Sep 11 04:53:46 AM UTC 24
Finished Sep 11 04:53:57 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272908083 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1272908083
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1339370688
Short name T162
Test name
Test status
Simulation time 568549523 ps
CPU time 17.49 seconds
Started Sep 11 04:53:44 AM UTC 24
Finished Sep 11 04:54:03 AM UTC 24
Peak memory 225440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133937068
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.1339370688
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2371046724
Short name T64
Test name
Test status
Simulation time 1377783385 ps
CPU time 65.12 seconds
Started Sep 11 04:53:49 AM UTC 24
Finished Sep 11 04:54:55 AM UTC 24
Peak memory 228752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2371046724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2371046724
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.2345270986
Short name T164
Test name
Test status
Simulation time 85726491 ps
CPU time 6.13 seconds
Started Sep 11 04:53:59 AM UTC 24
Finished Sep 11 04:54:06 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345270986 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2345270986
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2169126155
Short name T212
Test name
Test status
Simulation time 1400762126 ps
CPU time 94.69 seconds
Started Sep 11 04:53:52 AM UTC 24
Finished Sep 11 04:55:28 AM UTC 24
Peak memory 242020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169126155 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.2169126155
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2639237946
Short name T165
Test name
Test status
Simulation time 669532498 ps
CPU time 10.6 seconds
Started Sep 11 04:53:56 AM UTC 24
Finished Sep 11 04:54:08 AM UTC 24
Peak memory 221400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639237946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2639237946
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.4076693672
Short name T161
Test name
Test status
Simulation time 97444738 ps
CPU time 8.08 seconds
Started Sep 11 04:53:51 AM UTC 24
Finished Sep 11 04:54:00 AM UTC 24
Peak memory 221260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076693672 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.4076693672
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3106371231
Short name T166
Test name
Test status
Simulation time 268412857 ps
CPU time 18.63 seconds
Started Sep 11 04:53:51 AM UTC 24
Finished Sep 11 04:54:11 AM UTC 24
Peak memory 223392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310637123
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.3106371231
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1928289877
Short name T234
Test name
Test status
Simulation time 1602137196 ps
CPU time 110.43 seconds
Started Sep 11 04:53:58 AM UTC 24
Finished Sep 11 04:55:51 AM UTC 24
Peak memory 230800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1928289877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1928289877
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.969353711
Short name T169
Test name
Test status
Simulation time 89524231 ps
CPU time 5.43 seconds
Started Sep 11 04:54:07 AM UTC 24
Finished Sep 11 04:54:14 AM UTC 24
Peak memory 221264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969353711 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.969353711
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3426203174
Short name T227
Test name
Test status
Simulation time 6500464341 ps
CPU time 98.13 seconds
Started Sep 11 04:54:04 AM UTC 24
Finished Sep 11 04:55:44 AM UTC 24
Peak memory 223772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426203174 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.3426203174
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.1069419462
Short name T171
Test name
Test status
Simulation time 1076341042 ps
CPU time 13.82 seconds
Started Sep 11 04:54:05 AM UTC 24
Finished Sep 11 04:54:20 AM UTC 24
Peak memory 221336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069419462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1069419462
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.2626728197
Short name T167
Test name
Test status
Simulation time 381107095 ps
CPU time 7.77 seconds
Started Sep 11 04:54:02 AM UTC 24
Finished Sep 11 04:54:11 AM UTC 24
Peak memory 221340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626728197 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2626728197
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.27325759
Short name T168
Test name
Test status
Simulation time 215325117 ps
CPU time 10.38 seconds
Started Sep 11 04:54:01 AM UTC 24
Finished Sep 11 04:54:13 AM UTC 24
Peak memory 221264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27325759
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.27325759
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3183427564
Short name T285
Test name
Test status
Simulation time 15139370166 ps
CPU time 162.71 seconds
Started Sep 11 04:54:07 AM UTC 24
Finished Sep 11 04:56:53 AM UTC 24
Peak memory 230788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3183427564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3183427564
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3452425831
Short name T56
Test name
Test status
Simulation time 5273181831 ps
CPU time 187.69 seconds
Started Sep 11 04:51:20 AM UTC 24
Finished Sep 11 04:54:30 AM UTC 24
Peak memory 257408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452425831 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.3452425831
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3920523412
Short name T27
Test name
Test status
Simulation time 691509271 ps
CPU time 13.8 seconds
Started Sep 11 04:51:20 AM UTC 24
Finished Sep 11 04:51:35 AM UTC 24
Peak memory 221408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920523412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3920523412
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.604814725
Short name T19
Test name
Test status
Simulation time 364748761 ps
CPU time 8.26 seconds
Started Sep 11 04:51:19 AM UTC 24
Finished Sep 11 04:51:28 AM UTC 24
Peak memory 221352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604814725 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.604814725
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2922108994
Short name T25
Test name
Test status
Simulation time 2673365017 ps
CPU time 54.73 seconds
Started Sep 11 04:51:21 AM UTC 24
Finished Sep 11 04:52:17 AM UTC 24
Peak memory 257580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922108994 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2922108994
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1657703198
Short name T10
Test name
Test status
Simulation time 97047396 ps
CPU time 8.48 seconds
Started Sep 11 04:51:17 AM UTC 24
Finished Sep 11 04:51:26 AM UTC 24
Peak memory 221524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657703198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1657703198
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.973863293
Short name T17
Test name
Test status
Simulation time 578407624 ps
CPU time 10.22 seconds
Started Sep 11 04:51:19 AM UTC 24
Finished Sep 11 04:51:30 AM UTC 24
Peak memory 223388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973863293
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.973863293
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.1150310862
Short name T173
Test name
Test status
Simulation time 831689893 ps
CPU time 7.12 seconds
Started Sep 11 04:54:15 AM UTC 24
Finished Sep 11 04:54:23 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150310862 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1150310862
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.78743042
Short name T299
Test name
Test status
Simulation time 7234844910 ps
CPU time 177.31 seconds
Started Sep 11 04:54:12 AM UTC 24
Finished Sep 11 04:57:12 AM UTC 24
Peak memory 256856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78743042 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.78743042
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.1849041504
Short name T176
Test name
Test status
Simulation time 2073872629 ps
CPU time 14.64 seconds
Started Sep 11 04:54:12 AM UTC 24
Finished Sep 11 04:54:28 AM UTC 24
Peak memory 221064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849041504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1849041504
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.1855205695
Short name T170
Test name
Test status
Simulation time 136529526 ps
CPU time 7.92 seconds
Started Sep 11 04:54:11 AM UTC 24
Finished Sep 11 04:54:20 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855205695 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1855205695
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.1391066326
Short name T174
Test name
Test status
Simulation time 614701735 ps
CPU time 15.78 seconds
Started Sep 11 04:54:09 AM UTC 24
Finished Sep 11 04:54:25 AM UTC 24
Peak memory 223712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139106632
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.1391066326
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1705458351
Short name T206
Test name
Test status
Simulation time 2565125323 ps
CPU time 65.85 seconds
Started Sep 11 04:54:14 AM UTC 24
Finished Sep 11 04:55:21 AM UTC 24
Peak memory 230864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1705458351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1705458351
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.3878903346
Short name T177
Test name
Test status
Simulation time 234686811 ps
CPU time 5.05 seconds
Started Sep 11 04:54:24 AM UTC 24
Finished Sep 11 04:54:30 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878903346 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3878903346
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.924571726
Short name T268
Test name
Test status
Simulation time 5325907853 ps
CPU time 129.57 seconds
Started Sep 11 04:54:21 AM UTC 24
Finished Sep 11 04:56:33 AM UTC 24
Peak memory 244848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924571726 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.924571726
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.3469312287
Short name T180
Test name
Test status
Simulation time 696294444 ps
CPU time 12.39 seconds
Started Sep 11 04:54:21 AM UTC 24
Finished Sep 11 04:54:35 AM UTC 24
Peak memory 221336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469312287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3469312287
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3616081220
Short name T175
Test name
Test status
Simulation time 541469886 ps
CPU time 5.34 seconds
Started Sep 11 04:54:20 AM UTC 24
Finished Sep 11 04:54:26 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616081220 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3616081220
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.2271141614
Short name T186
Test name
Test status
Simulation time 434260025 ps
CPU time 23.12 seconds
Started Sep 11 04:54:17 AM UTC 24
Finished Sep 11 04:54:41 AM UTC 24
Peak memory 223472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227114161
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.2271141614
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2199307952
Short name T125
Test name
Test status
Simulation time 9236275359 ps
CPU time 158.57 seconds
Started Sep 11 04:54:22 AM UTC 24
Finished Sep 11 04:57:03 AM UTC 24
Peak memory 233104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2199307952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2199307952
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.765683500
Short name T183
Test name
Test status
Simulation time 260700162 ps
CPU time 6.3 seconds
Started Sep 11 04:54:32 AM UTC 24
Finished Sep 11 04:54:39 AM UTC 24
Peak memory 221308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765683500 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.765683500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.369919504
Short name T220
Test name
Test status
Simulation time 3373855092 ps
CPU time 69.38 seconds
Started Sep 11 04:54:27 AM UTC 24
Finished Sep 11 04:55:39 AM UTC 24
Peak memory 256636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369919504 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.369919504
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.3416343201
Short name T185
Test name
Test status
Simulation time 508484219 ps
CPU time 10.89 seconds
Started Sep 11 04:54:29 AM UTC 24
Finished Sep 11 04:54:41 AM UTC 24
Peak memory 221336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416343201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3416343201
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2464065000
Short name T181
Test name
Test status
Simulation time 1118702066 ps
CPU time 9.69 seconds
Started Sep 11 04:54:26 AM UTC 24
Finished Sep 11 04:54:37 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464065000 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2464065000
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.3641649796
Short name T182
Test name
Test status
Simulation time 409069641 ps
CPU time 11.52 seconds
Started Sep 11 04:54:26 AM UTC 24
Finished Sep 11 04:54:39 AM UTC 24
Peak memory 223392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364164979
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.3641649796
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.420680379
Short name T127
Test name
Test status
Simulation time 4640765778 ps
CPU time 103.9 seconds
Started Sep 11 04:54:30 AM UTC 24
Finished Sep 11 04:56:16 AM UTC 24
Peak memory 239056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=420680379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.rom_ctrl_stress_all_with_rand_reset.420680379
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.776340028
Short name T123
Test name
Test status
Simulation time 529049907 ps
CPU time 10.06 seconds
Started Sep 11 04:54:38 AM UTC 24
Finished Sep 11 04:54:50 AM UTC 24
Peak memory 221564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776340028 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.776340028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1342896136
Short name T338
Test name
Test status
Simulation time 63683963173 ps
CPU time 226.71 seconds
Started Sep 11 04:54:34 AM UTC 24
Finished Sep 11 04:58:24 AM UTC 24
Peak memory 256388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342896136 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.1342896136
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.113625636
Short name T188
Test name
Test status
Simulation time 497710465 ps
CPU time 11.13 seconds
Started Sep 11 04:54:35 AM UTC 24
Finished Sep 11 04:54:47 AM UTC 24
Peak memory 221536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113625636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.113625636
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2670039919
Short name T184
Test name
Test status
Simulation time 95890430 ps
CPU time 7.63 seconds
Started Sep 11 04:54:32 AM UTC 24
Finished Sep 11 04:54:40 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670039919 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2670039919
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.1772211108
Short name T187
Test name
Test status
Simulation time 686746912 ps
CPU time 11.56 seconds
Started Sep 11 04:54:32 AM UTC 24
Finished Sep 11 04:54:44 AM UTC 24
Peak memory 221536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177221110
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.1772211108
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3656575962
Short name T216
Test name
Test status
Simulation time 7494514059 ps
CPU time 53.77 seconds
Started Sep 11 04:54:37 AM UTC 24
Finished Sep 11 04:55:32 AM UTC 24
Peak memory 230852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3656575962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3656575962
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.655971071
Short name T51
Test name
Test status
Simulation time 691161913 ps
CPU time 6.98 seconds
Started Sep 11 04:54:45 AM UTC 24
Finished Sep 11 04:54:54 AM UTC 24
Peak memory 221308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655971071 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.655971071
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.508793636
Short name T244
Test name
Test status
Simulation time 2086035148 ps
CPU time 78.74 seconds
Started Sep 11 04:54:41 AM UTC 24
Finished Sep 11 04:56:03 AM UTC 24
Peak memory 244816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508793636 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.508793636
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.2755278529
Short name T192
Test name
Test status
Simulation time 875208081 ps
CPU time 13.64 seconds
Started Sep 11 04:54:41 AM UTC 24
Finished Sep 11 04:54:57 AM UTC 24
Peak memory 221264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755278529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2755278529
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.2186071072
Short name T189
Test name
Test status
Simulation time 780983781 ps
CPU time 9.44 seconds
Started Sep 11 04:54:40 AM UTC 24
Finished Sep 11 04:54:51 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186071072 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2186071072
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2250377349
Short name T194
Test name
Test status
Simulation time 1810265543 ps
CPU time 19.52 seconds
Started Sep 11 04:54:40 AM UTC 24
Finished Sep 11 04:55:01 AM UTC 24
Peak memory 223472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225037734
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.2250377349
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2035658268
Short name T266
Test name
Test status
Simulation time 8999854172 ps
CPU time 107.36 seconds
Started Sep 11 04:54:42 AM UTC 24
Finished Sep 11 04:56:33 AM UTC 24
Peak memory 232912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2035658268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2035658268
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.1087556045
Short name T195
Test name
Test status
Simulation time 1654488882 ps
CPU time 4.71 seconds
Started Sep 11 04:54:55 AM UTC 24
Finished Sep 11 04:55:01 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087556045 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1087556045
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3861058712
Short name T318
Test name
Test status
Simulation time 2098003780 ps
CPU time 160.78 seconds
Started Sep 11 04:54:51 AM UTC 24
Finished Sep 11 04:57:34 AM UTC 24
Peak memory 241988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861058712 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.3861058712
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.1912307445
Short name T200
Test name
Test status
Simulation time 337452985 ps
CPU time 16.41 seconds
Started Sep 11 04:54:52 AM UTC 24
Finished Sep 11 04:55:09 AM UTC 24
Peak memory 221336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912307445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1912307445
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.1108860589
Short name T193
Test name
Test status
Simulation time 1516756134 ps
CPU time 9.03 seconds
Started Sep 11 04:54:48 AM UTC 24
Finished Sep 11 04:54:58 AM UTC 24
Peak memory 221260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108860589 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1108860589
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.3462841055
Short name T196
Test name
Test status
Simulation time 292825574 ps
CPU time 15.67 seconds
Started Sep 11 04:54:47 AM UTC 24
Finished Sep 11 04:55:04 AM UTC 24
Peak memory 225520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346284105
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.3462841055
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2747691054
Short name T124
Test name
Test status
Simulation time 3441576083 ps
CPU time 125.27 seconds
Started Sep 11 04:54:54 AM UTC 24
Finished Sep 11 04:57:01 AM UTC 24
Peak memory 239056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2747691054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2747691054
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.37889661
Short name T199
Test name
Test status
Simulation time 825173176 ps
CPU time 6.31 seconds
Started Sep 11 04:55:01 AM UTC 24
Finished Sep 11 04:55:09 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37889661 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.37889661
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2424954631
Short name T250
Test name
Test status
Simulation time 2594013783 ps
CPU time 70.12 seconds
Started Sep 11 04:54:57 AM UTC 24
Finished Sep 11 04:56:09 AM UTC 24
Peak memory 221532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424954631 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.2424954631
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.2533611449
Short name T202
Test name
Test status
Simulation time 448612682 ps
CPU time 16.8 seconds
Started Sep 11 04:54:58 AM UTC 24
Finished Sep 11 04:55:16 AM UTC 24
Peak memory 221336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533611449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2533611449
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1515561692
Short name T198
Test name
Test status
Simulation time 276569751 ps
CPU time 9.58 seconds
Started Sep 11 04:54:56 AM UTC 24
Finished Sep 11 04:55:07 AM UTC 24
Peak memory 221392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515561692 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1515561692
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2785556611
Short name T205
Test name
Test status
Simulation time 1897893040 ps
CPU time 24.55 seconds
Started Sep 11 04:54:55 AM UTC 24
Finished Sep 11 04:55:21 AM UTC 24
Peak memory 227552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278555661
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.2785556611
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1653327795
Short name T241
Test name
Test status
Simulation time 1740153604 ps
CPU time 55.48 seconds
Started Sep 11 04:55:01 AM UTC 24
Finished Sep 11 04:55:59 AM UTC 24
Peak memory 231012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1653327795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1653327795
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.773246500
Short name T203
Test name
Test status
Simulation time 337098917 ps
CPU time 4.12 seconds
Started Sep 11 04:55:14 AM UTC 24
Finished Sep 11 04:55:19 AM UTC 24
Peak memory 221308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773246500 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.773246500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.649746131
Short name T286
Test name
Test status
Simulation time 8579514140 ps
CPU time 107.25 seconds
Started Sep 11 04:55:08 AM UTC 24
Finished Sep 11 04:56:57 AM UTC 24
Peak memory 256320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649746131 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.649746131
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.2442366260
Short name T207
Test name
Test status
Simulation time 504037140 ps
CPU time 12.33 seconds
Started Sep 11 04:55:10 AM UTC 24
Finished Sep 11 04:55:23 AM UTC 24
Peak memory 221528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442366260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2442366260
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.2351240295
Short name T201
Test name
Test status
Simulation time 676918804 ps
CPU time 7.28 seconds
Started Sep 11 04:55:05 AM UTC 24
Finished Sep 11 04:55:14 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351240295 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2351240295
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.2554857878
Short name T211
Test name
Test status
Simulation time 550039219 ps
CPU time 20.49 seconds
Started Sep 11 04:55:04 AM UTC 24
Finished Sep 11 04:55:26 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255485787
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.2554857878
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.135966079
Short name T264
Test name
Test status
Simulation time 1185741364 ps
CPU time 78.23 seconds
Started Sep 11 04:55:11 AM UTC 24
Finished Sep 11 04:56:31 AM UTC 24
Peak memory 230992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=135966079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.rom_ctrl_stress_all_with_rand_reset.135966079
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.2178001483
Short name T214
Test name
Test status
Simulation time 126101536 ps
CPU time 5.69 seconds
Started Sep 11 04:55:22 AM UTC 24
Finished Sep 11 04:55:29 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178001483 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2178001483
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1043026221
Short name T329
Test name
Test status
Simulation time 8496936581 ps
CPU time 157.11 seconds
Started Sep 11 04:55:17 AM UTC 24
Finished Sep 11 04:57:57 AM UTC 24
Peak memory 257392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043026221 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.1043026221
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.772327919
Short name T218
Test name
Test status
Simulation time 997499788 ps
CPU time 13.45 seconds
Started Sep 11 04:55:20 AM UTC 24
Finished Sep 11 04:55:35 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772327919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.772327919
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1721208402
Short name T210
Test name
Test status
Simulation time 135132643 ps
CPU time 8.87 seconds
Started Sep 11 04:55:16 AM UTC 24
Finished Sep 11 04:55:26 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721208402 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1721208402
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.1506720267
Short name T224
Test name
Test status
Simulation time 304887691 ps
CPU time 25.23 seconds
Started Sep 11 04:55:15 AM UTC 24
Finished Sep 11 04:55:41 AM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150672026
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.1506720267
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.4242986984
Short name T290
Test name
Test status
Simulation time 7839614694 ps
CPU time 97.3 seconds
Started Sep 11 04:55:20 AM UTC 24
Finished Sep 11 04:56:59 AM UTC 24
Peak memory 233104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4242986984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.rom_ctrl_stress_all_with_rand_reset.4242986984
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.1261164690
Short name T217
Test name
Test status
Simulation time 105162226 ps
CPU time 6.35 seconds
Started Sep 11 04:55:27 AM UTC 24
Finished Sep 11 04:55:34 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261164690 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1261164690
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1882703844
Short name T262
Test name
Test status
Simulation time 6675473516 ps
CPU time 64.58 seconds
Started Sep 11 04:55:23 AM UTC 24
Finished Sep 11 04:56:30 AM UTC 24
Peak memory 253416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882703844 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.1882703844
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.208217732
Short name T221
Test name
Test status
Simulation time 270033179 ps
CPU time 13.17 seconds
Started Sep 11 04:55:24 AM UTC 24
Finished Sep 11 04:55:39 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208217732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.208217732
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.893240866
Short name T215
Test name
Test status
Simulation time 98513871 ps
CPU time 6.46 seconds
Started Sep 11 04:55:23 AM UTC 24
Finished Sep 11 04:55:31 AM UTC 24
Peak memory 221536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893240866 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.893240866
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.1849225298
Short name T219
Test name
Test status
Simulation time 2774628733 ps
CPU time 15.26 seconds
Started Sep 11 04:55:22 AM UTC 24
Finished Sep 11 04:55:38 AM UTC 24
Peak memory 227696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184922529
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.1849225298
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1586950682
Short name T126
Test name
Test status
Simulation time 14447908930 ps
CPU time 201.14 seconds
Started Sep 11 04:55:25 AM UTC 24
Finished Sep 11 04:58:50 AM UTC 24
Peak memory 233104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1586950682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1586950682
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.2824852607
Short name T29
Test name
Test status
Simulation time 539972405 ps
CPU time 7.41 seconds
Started Sep 11 04:51:30 AM UTC 24
Finished Sep 11 04:51:38 AM UTC 24
Peak memory 221316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824852607 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2824852607
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2661352838
Short name T190
Test name
Test status
Simulation time 10193813980 ps
CPU time 203.63 seconds
Started Sep 11 04:51:26 AM UTC 24
Finished Sep 11 04:54:53 AM UTC 24
Peak memory 252332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661352838 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.2661352838
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.2225324652
Short name T77
Test name
Test status
Simulation time 372925536 ps
CPU time 8.54 seconds
Started Sep 11 04:51:25 AM UTC 24
Finished Sep 11 04:51:35 AM UTC 24
Peak memory 221520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225324652 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2225324652
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.1993151080
Short name T26
Test name
Test status
Simulation time 557951317 ps
CPU time 60.43 seconds
Started Sep 11 04:51:29 AM UTC 24
Finished Sep 11 04:52:31 AM UTC 24
Peak memory 257504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993151080 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1993151080
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1921117268
Short name T20
Test name
Test status
Simulation time 140521907 ps
CPU time 9.17 seconds
Started Sep 11 04:51:23 AM UTC 24
Finished Sep 11 04:51:33 AM UTC 24
Peak memory 221348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921117268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1921117268
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.4243592943
Short name T223
Test name
Test status
Simulation time 126363845 ps
CPU time 6.91 seconds
Started Sep 11 04:55:32 AM UTC 24
Finished Sep 11 04:55:40 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243592943 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.4243592943
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3708840699
Short name T289
Test name
Test status
Simulation time 1814837341 ps
CPU time 87.56 seconds
Started Sep 11 04:55:30 AM UTC 24
Finished Sep 11 04:56:59 AM UTC 24
Peak memory 221468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708840699 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.3708840699
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.3694135914
Short name T225
Test name
Test status
Simulation time 350134799 ps
CPU time 11.89 seconds
Started Sep 11 04:55:30 AM UTC 24
Finished Sep 11 04:55:43 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694135914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3694135914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.807001255
Short name T222
Test name
Test status
Simulation time 292456464 ps
CPU time 9.68 seconds
Started Sep 11 04:55:29 AM UTC 24
Finished Sep 11 04:55:40 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807001255 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.807001255
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.141423804
Short name T228
Test name
Test status
Simulation time 1462898126 ps
CPU time 17.9 seconds
Started Sep 11 04:55:27 AM UTC 24
Finished Sep 11 04:55:46 AM UTC 24
Peak memory 225432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141423804
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.141423804
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2426848069
Short name T308
Test name
Test status
Simulation time 10661479672 ps
CPU time 107.3 seconds
Started Sep 11 04:55:32 AM UTC 24
Finished Sep 11 04:57:21 AM UTC 24
Peak memory 233104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2426848069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2426848069
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.1434360133
Short name T230
Test name
Test status
Simulation time 591497207 ps
CPU time 6.16 seconds
Started Sep 11 04:55:39 AM UTC 24
Finished Sep 11 04:55:46 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434360133 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1434360133
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2656603310
Short name T325
Test name
Test status
Simulation time 9201370676 ps
CPU time 126.58 seconds
Started Sep 11 04:55:35 AM UTC 24
Finished Sep 11 04:57:44 AM UTC 24
Peak memory 223512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656603310 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.2656603310
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.2871706226
Short name T235
Test name
Test status
Simulation time 342867361 ps
CPU time 10.88 seconds
Started Sep 11 04:55:39 AM UTC 24
Finished Sep 11 04:55:51 AM UTC 24
Peak memory 221592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871706226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2871706226
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2975427140
Short name T229
Test name
Test status
Simulation time 144479255 ps
CPU time 9.64 seconds
Started Sep 11 04:55:35 AM UTC 24
Finished Sep 11 04:55:46 AM UTC 24
Peak memory 221392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975427140 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2975427140
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.154547700
Short name T233
Test name
Test status
Simulation time 1362445907 ps
CPU time 15.81 seconds
Started Sep 11 04:55:33 AM UTC 24
Finished Sep 11 04:55:50 AM UTC 24
Peak memory 225432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154547700
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.154547700
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2252872673
Short name T360
Test name
Test status
Simulation time 21187713583 ps
CPU time 377.9 seconds
Started Sep 11 04:55:39 AM UTC 24
Finished Sep 11 05:02:02 AM UTC 24
Peak memory 235020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2252872673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2252872673
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.3162257539
Short name T237
Test name
Test status
Simulation time 127091582 ps
CPU time 7.23 seconds
Started Sep 11 04:55:46 AM UTC 24
Finished Sep 11 04:55:54 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162257539 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3162257539
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3755581179
Short name T339
Test name
Test status
Simulation time 4517584921 ps
CPU time 161.56 seconds
Started Sep 11 04:55:43 AM UTC 24
Finished Sep 11 04:58:27 AM UTC 24
Peak memory 244736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755581179 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.3755581179
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.627677688
Short name T240
Test name
Test status
Simulation time 175334663 ps
CPU time 10.55 seconds
Started Sep 11 04:55:44 AM UTC 24
Finished Sep 11 04:55:55 AM UTC 24
Peak memory 221536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627677688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.627677688
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.1237483726
Short name T232
Test name
Test status
Simulation time 137613210 ps
CPU time 6.73 seconds
Started Sep 11 04:55:40 AM UTC 24
Finished Sep 11 04:55:48 AM UTC 24
Peak memory 221648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237483726 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1237483726
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2783037906
Short name T236
Test name
Test status
Simulation time 176357284 ps
CPU time 11.63 seconds
Started Sep 11 04:55:40 AM UTC 24
Finished Sep 11 04:55:53 AM UTC 24
Peak memory 221680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278303790
6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.2783037906
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3136669613
Short name T261
Test name
Test status
Simulation time 942085454 ps
CPU time 42.65 seconds
Started Sep 11 04:55:45 AM UTC 24
Finished Sep 11 04:56:29 AM UTC 24
Peak memory 228944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3136669613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3136669613
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.4257149632
Short name T239
Test name
Test status
Simulation time 85489894 ps
CPU time 4.6 seconds
Started Sep 11 04:55:49 AM UTC 24
Finished Sep 11 04:55:55 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257149632 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4257149632
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1984077261
Short name T331
Test name
Test status
Simulation time 14986183454 ps
CPU time 139.34 seconds
Started Sep 11 04:55:47 AM UTC 24
Finished Sep 11 04:58:09 AM UTC 24
Peak memory 257396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984077261 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.1984077261
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.3283824166
Short name T247
Test name
Test status
Simulation time 261271078 ps
CPU time 16.75 seconds
Started Sep 11 04:55:48 AM UTC 24
Finished Sep 11 04:56:06 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283824166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3283824166
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.2906735000
Short name T238
Test name
Test status
Simulation time 528030429 ps
CPU time 6.69 seconds
Started Sep 11 04:55:47 AM UTC 24
Finished Sep 11 04:55:55 AM UTC 24
Peak memory 221520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906735000 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2906735000
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.31752212
Short name T255
Test name
Test status
Simulation time 3120110020 ps
CPU time 30.25 seconds
Started Sep 11 04:55:47 AM UTC 24
Finished Sep 11 04:56:18 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31752212
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.31752212
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.891546611
Short name T297
Test name
Test status
Simulation time 2102091717 ps
CPU time 79.69 seconds
Started Sep 11 04:55:48 AM UTC 24
Finished Sep 11 04:57:09 AM UTC 24
Peak memory 239184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=891546611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.rom_ctrl_stress_all_with_rand_reset.891546611
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.2079350173
Short name T243
Test name
Test status
Simulation time 520574731 ps
CPU time 5.37 seconds
Started Sep 11 04:55:55 AM UTC 24
Finished Sep 11 04:56:02 AM UTC 24
Peak memory 220716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079350173 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2079350173
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.380420822
Short name T336
Test name
Test status
Simulation time 1958681636 ps
CPU time 146.84 seconds
Started Sep 11 04:55:52 AM UTC 24
Finished Sep 11 04:58:22 AM UTC 24
Peak memory 253312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380420822 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.380420822
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.725604620
Short name T249
Test name
Test status
Simulation time 261973029 ps
CPU time 13.68 seconds
Started Sep 11 04:55:54 AM UTC 24
Finished Sep 11 04:56:09 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725604620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.725604620
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.1643040848
Short name T242
Test name
Test status
Simulation time 136358478 ps
CPU time 9.22 seconds
Started Sep 11 04:55:51 AM UTC 24
Finished Sep 11 04:56:02 AM UTC 24
Peak memory 221520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643040848 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1643040848
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.3734466299
Short name T246
Test name
Test status
Simulation time 172542088 ps
CPU time 11.98 seconds
Started Sep 11 04:55:51 AM UTC 24
Finished Sep 11 04:56:04 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373446629
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.3734466299
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.544906155
Short name T330
Test name
Test status
Simulation time 2941061689 ps
CPU time 130.88 seconds
Started Sep 11 04:55:54 AM UTC 24
Finished Sep 11 04:58:08 AM UTC 24
Peak memory 231056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=544906155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.rom_ctrl_stress_all_with_rand_reset.544906155
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.501250501
Short name T252
Test name
Test status
Simulation time 517364612 ps
CPU time 7.49 seconds
Started Sep 11 04:56:03 AM UTC 24
Finished Sep 11 04:56:12 AM UTC 24
Peak memory 221308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501250501 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.501250501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3963274119
Short name T307
Test name
Test status
Simulation time 1395588502 ps
CPU time 82.18 seconds
Started Sep 11 04:55:57 AM UTC 24
Finished Sep 11 04:57:21 AM UTC 24
Peak memory 243900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963274119 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.3963274119
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.1746012054
Short name T251
Test name
Test status
Simulation time 255890441 ps
CPU time 10.65 seconds
Started Sep 11 04:56:00 AM UTC 24
Finished Sep 11 04:56:11 AM UTC 24
Peak memory 221464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746012054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1746012054
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.2570641355
Short name T245
Test name
Test status
Simulation time 2595717534 ps
CPU time 7.11 seconds
Started Sep 11 04:55:56 AM UTC 24
Finished Sep 11 04:56:04 AM UTC 24
Peak memory 221392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570641355 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2570641355
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.3891359584
Short name T248
Test name
Test status
Simulation time 752126780 ps
CPU time 11.43 seconds
Started Sep 11 04:55:55 AM UTC 24
Finished Sep 11 04:56:08 AM UTC 24
Peak memory 224956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389135958
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.3891359584
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2598765299
Short name T321
Test name
Test status
Simulation time 2203423522 ps
CPU time 92.8 seconds
Started Sep 11 04:56:03 AM UTC 24
Finished Sep 11 04:57:38 AM UTC 24
Peak memory 230864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2598765299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2598765299
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.2288639044
Short name T254
Test name
Test status
Simulation time 132616578 ps
CPU time 6.81 seconds
Started Sep 11 04:56:10 AM UTC 24
Finished Sep 11 04:56:18 AM UTC 24
Peak memory 221232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288639044 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2288639044
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3347201073
Short name T332
Test name
Test status
Simulation time 7303837507 ps
CPU time 123.46 seconds
Started Sep 11 04:56:05 AM UTC 24
Finished Sep 11 04:58:11 AM UTC 24
Peak memory 242052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347201073 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.3347201073
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.599299205
Short name T258
Test name
Test status
Simulation time 1040334438 ps
CPU time 14.98 seconds
Started Sep 11 04:56:07 AM UTC 24
Finished Sep 11 04:56:24 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599299205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.599299205
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.3527363191
Short name T253
Test name
Test status
Simulation time 139973530 ps
CPU time 9.85 seconds
Started Sep 11 04:56:05 AM UTC 24
Finished Sep 11 04:56:16 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527363191 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3527363191
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2235027603
Short name T274
Test name
Test status
Simulation time 1152204119 ps
CPU time 37.7 seconds
Started Sep 11 04:56:04 AM UTC 24
Finished Sep 11 04:56:43 AM UTC 24
Peak memory 227824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223502760
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.2235027603
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2048031108
Short name T324
Test name
Test status
Simulation time 10288996500 ps
CPU time 90.83 seconds
Started Sep 11 04:56:09 AM UTC 24
Finished Sep 11 04:57:42 AM UTC 24
Peak memory 243152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2048031108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2048031108
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.2150209241
Short name T259
Test name
Test status
Simulation time 130186584 ps
CPU time 6.17 seconds
Started Sep 11 04:56:19 AM UTC 24
Finished Sep 11 04:56:26 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150209241 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2150209241
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3402489390
Short name T346
Test name
Test status
Simulation time 6086469664 ps
CPU time 172.78 seconds
Started Sep 11 04:56:12 AM UTC 24
Finished Sep 11 04:59:08 AM UTC 24
Peak memory 223572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402489390 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.3402489390
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.42490330
Short name T260
Test name
Test status
Simulation time 1454190043 ps
CPU time 10.5 seconds
Started Sep 11 04:56:16 AM UTC 24
Finished Sep 11 04:56:28 AM UTC 24
Peak memory 221348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42490330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_
TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ct
rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.42490330
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.2381220229
Short name T257
Test name
Test status
Simulation time 499014553 ps
CPU time 7.64 seconds
Started Sep 11 04:56:12 AM UTC 24
Finished Sep 11 04:56:21 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381220229 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2381220229
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.3725271591
Short name T256
Test name
Test status
Simulation time 172951198 ps
CPU time 9.4 seconds
Started Sep 11 04:56:10 AM UTC 24
Finished Sep 11 04:56:21 AM UTC 24
Peak memory 221300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372527159
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.3725271591
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.676210454
Short name T342
Test name
Test status
Simulation time 9911617038 ps
CPU time 153.4 seconds
Started Sep 11 04:56:17 AM UTC 24
Finished Sep 11 04:58:53 AM UTC 24
Peak memory 230864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=676210454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.rom_ctrl_stress_all_with_rand_reset.676210454
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1932810668
Short name T265
Test name
Test status
Simulation time 414179629 ps
CPU time 7.35 seconds
Started Sep 11 04:56:24 AM UTC 24
Finished Sep 11 04:56:33 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932810668 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1932810668
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1400568232
Short name T337
Test name
Test status
Simulation time 2966037244 ps
CPU time 117.29 seconds
Started Sep 11 04:56:22 AM UTC 24
Finished Sep 11 04:58:22 AM UTC 24
Peak memory 257360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400568232 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.1400568232
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2605441091
Short name T279
Test name
Test status
Simulation time 2025119891 ps
CPU time 23.98 seconds
Started Sep 11 04:56:22 AM UTC 24
Finished Sep 11 04:56:47 AM UTC 24
Peak memory 221300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605441091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2605441091
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.106454344
Short name T263
Test name
Test status
Simulation time 374913070 ps
CPU time 8.26 seconds
Started Sep 11 04:56:21 AM UTC 24
Finished Sep 11 04:56:30 AM UTC 24
Peak memory 221340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106454344 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.106454344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.3122712847
Short name T269
Test name
Test status
Simulation time 1492701872 ps
CPU time 14.65 seconds
Started Sep 11 04:56:20 AM UTC 24
Finished Sep 11 04:56:36 AM UTC 24
Peak memory 225440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312271284
7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.3122712847
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3747335421
Short name T361
Test name
Test status
Simulation time 20358029119 ps
CPU time 363.62 seconds
Started Sep 11 04:56:24 AM UTC 24
Finished Sep 11 05:02:33 AM UTC 24
Peak memory 234960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3747335421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3747335421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.4239351827
Short name T271
Test name
Test status
Simulation time 481211810 ps
CPU time 6.61 seconds
Started Sep 11 04:56:31 AM UTC 24
Finished Sep 11 04:56:39 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239351827 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4239351827
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2701063494
Short name T345
Test name
Test status
Simulation time 2820009933 ps
CPU time 155.84 seconds
Started Sep 11 04:56:29 AM UTC 24
Finished Sep 11 04:59:08 AM UTC 24
Peak memory 257384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701063494 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.2701063494
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.3184205225
Short name T276
Test name
Test status
Simulation time 497751036 ps
CPU time 15.64 seconds
Started Sep 11 04:56:29 AM UTC 24
Finished Sep 11 04:56:46 AM UTC 24
Peak memory 221264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184205225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3184205225
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.517103500
Short name T270
Test name
Test status
Simulation time 373022662 ps
CPU time 7.8 seconds
Started Sep 11 04:56:28 AM UTC 24
Finished Sep 11 04:56:37 AM UTC 24
Peak memory 221536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517103500 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.517103500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.114658951
Short name T282
Test name
Test status
Simulation time 421652446 ps
CPU time 23.75 seconds
Started Sep 11 04:56:27 AM UTC 24
Finished Sep 11 04:56:52 AM UTC 24
Peak memory 227560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114658951
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.114658951
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.239082031
Short name T74
Test name
Test status
Simulation time 88309199 ps
CPU time 6.37 seconds
Started Sep 11 04:51:39 AM UTC 24
Finished Sep 11 04:51:46 AM UTC 24
Peak memory 221308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239082031 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.239082031
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.229414841
Short name T36
Test name
Test status
Simulation time 670988867 ps
CPU time 9.49 seconds
Started Sep 11 04:51:35 AM UTC 24
Finished Sep 11 04:51:45 AM UTC 24
Peak memory 221540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229414841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.229414841
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.2181491447
Short name T30
Test name
Test status
Simulation time 99643768 ps
CPU time 7.8 seconds
Started Sep 11 04:51:31 AM UTC 24
Finished Sep 11 04:51:40 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181491447 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2181491447
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2829979098
Short name T39
Test name
Test status
Simulation time 145358888 ps
CPU time 76.39 seconds
Started Sep 11 04:51:36 AM UTC 24
Finished Sep 11 04:52:54 AM UTC 24
Peak memory 257536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829979098 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2829979098
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3590478237
Short name T69
Test name
Test status
Simulation time 364001257 ps
CPU time 8.49 seconds
Started Sep 11 04:51:30 AM UTC 24
Finished Sep 11 04:51:39 AM UTC 24
Peak memory 221336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590478237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3590478237
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.1467435344
Short name T34
Test name
Test status
Simulation time 596984831 ps
CPU time 37.57 seconds
Started Sep 11 04:51:31 AM UTC 24
Finished Sep 11 04:52:10 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146743534
4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.1467435344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1056907737
Short name T59
Test name
Test status
Simulation time 7773961766 ps
CPU time 108.99 seconds
Started Sep 11 04:51:36 AM UTC 24
Finished Sep 11 04:53:27 AM UTC 24
Peak memory 230864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1056907737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1056907737
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.681991417
Short name T275
Test name
Test status
Simulation time 956042637 ps
CPU time 7.37 seconds
Started Sep 11 04:56:36 AM UTC 24
Finished Sep 11 04:56:44 AM UTC 24
Peak memory 221308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681991417 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.681991417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.45526618
Short name T348
Test name
Test status
Simulation time 3942449936 ps
CPU time 157.76 seconds
Started Sep 11 04:56:34 AM UTC 24
Finished Sep 11 04:59:14 AM UTC 24
Peak memory 256624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45526618 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.45526618
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.758845242
Short name T280
Test name
Test status
Simulation time 362426979 ps
CPU time 14.31 seconds
Started Sep 11 04:56:34 AM UTC 24
Finished Sep 11 04:56:49 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758845242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.758845242
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3824145803
Short name T273
Test name
Test status
Simulation time 1272534200 ps
CPU time 7.75 seconds
Started Sep 11 04:56:34 AM UTC 24
Finished Sep 11 04:56:42 AM UTC 24
Peak memory 221484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824145803 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3824145803
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.401783042
Short name T281
Test name
Test status
Simulation time 642603407 ps
CPU time 16.85 seconds
Started Sep 11 04:56:31 AM UTC 24
Finished Sep 11 04:56:49 AM UTC 24
Peak memory 223448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401783042
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.401783042
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1212548953
Short name T359
Test name
Test status
Simulation time 4352331886 ps
CPU time 317.54 seconds
Started Sep 11 04:56:34 AM UTC 24
Finished Sep 11 05:01:56 AM UTC 24
Peak memory 243344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1212548953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1212548953
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.1521371656
Short name T283
Test name
Test status
Simulation time 568322740 ps
CPU time 7.23 seconds
Started Sep 11 04:56:44 AM UTC 24
Finished Sep 11 04:56:52 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521371656 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1521371656
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1056977025
Short name T352
Test name
Test status
Simulation time 19858697836 ps
CPU time 167.82 seconds
Started Sep 11 04:56:40 AM UTC 24
Finished Sep 11 04:59:30 AM UTC 24
Peak memory 257468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056977025 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.1056977025
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3783715743
Short name T284
Test name
Test status
Simulation time 169652963 ps
CPU time 9.42 seconds
Started Sep 11 04:56:42 AM UTC 24
Finished Sep 11 04:56:53 AM UTC 24
Peak memory 221336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783715743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3783715743
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1676728618
Short name T278
Test name
Test status
Simulation time 407384626 ps
CPU time 7.64 seconds
Started Sep 11 04:56:38 AM UTC 24
Finished Sep 11 04:56:47 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676728618 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1676728618
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.2827216901
Short name T277
Test name
Test status
Simulation time 352167811 ps
CPU time 8.18 seconds
Started Sep 11 04:56:37 AM UTC 24
Finished Sep 11 04:56:46 AM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282721690
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.2827216901
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2134049413
Short name T347
Test name
Test status
Simulation time 92105712551 ps
CPU time 146.72 seconds
Started Sep 11 04:56:43 AM UTC 24
Finished Sep 11 04:59:12 AM UTC 24
Peak memory 234960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2134049413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2134049413
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3469011433
Short name T288
Test name
Test status
Simulation time 597993830 ps
CPU time 7.3 seconds
Started Sep 11 04:56:50 AM UTC 24
Finished Sep 11 04:56:58 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469011433 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3469011433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2167681924
Short name T335
Test name
Test status
Simulation time 1759065506 ps
CPU time 92.25 seconds
Started Sep 11 04:56:47 AM UTC 24
Finished Sep 11 04:58:22 AM UTC 24
Peak memory 223772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167681924 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.2167681924
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1476973336
Short name T292
Test name
Test status
Simulation time 2264006716 ps
CPU time 13.4 seconds
Started Sep 11 04:56:47 AM UTC 24
Finished Sep 11 04:57:02 AM UTC 24
Peak memory 221400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476973336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1476973336
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.3679333016
Short name T287
Test name
Test status
Simulation time 274139628 ps
CPU time 10 seconds
Started Sep 11 04:56:46 AM UTC 24
Finished Sep 11 04:56:57 AM UTC 24
Peak memory 221392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679333016 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3679333016
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1418024521
Short name T294
Test name
Test status
Simulation time 321026054 ps
CPU time 21.3 seconds
Started Sep 11 04:56:45 AM UTC 24
Finished Sep 11 04:57:08 AM UTC 24
Peak memory 223392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141802452
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.1418024521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.4002647908
Short name T362
Test name
Test status
Simulation time 38827970122 ps
CPU time 354.44 seconds
Started Sep 11 04:56:49 AM UTC 24
Finished Sep 11 05:02:48 AM UTC 24
Peak memory 246592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4002647908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.rom_ctrl_stress_all_with_rand_reset.4002647908
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2566224897
Short name T293
Test name
Test status
Simulation time 86384791 ps
CPU time 6.22 seconds
Started Sep 11 04:56:58 AM UTC 24
Finished Sep 11 04:57:05 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566224897 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2566224897
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2910159413
Short name T354
Test name
Test status
Simulation time 2505547899 ps
CPU time 168.14 seconds
Started Sep 11 04:56:54 AM UTC 24
Finished Sep 11 04:59:45 AM UTC 24
Peak memory 257416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910159413 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.2910159413
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.1861729735
Short name T298
Test name
Test status
Simulation time 510814321 ps
CPU time 15.84 seconds
Started Sep 11 04:56:54 AM UTC 24
Finished Sep 11 04:57:11 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861729735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1861729735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.58533866
Short name T291
Test name
Test status
Simulation time 385544332 ps
CPU time 6.7 seconds
Started Sep 11 04:56:53 AM UTC 24
Finished Sep 11 04:57:01 AM UTC 24
Peak memory 221596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58533866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.58533866
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.2116520068
Short name T302
Test name
Test status
Simulation time 884784010 ps
CPU time 21.73 seconds
Started Sep 11 04:56:51 AM UTC 24
Finished Sep 11 04:57:14 AM UTC 24
Peak memory 227488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211652006
8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.2116520068
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2723225141
Short name T344
Test name
Test status
Simulation time 3117968382 ps
CPU time 124.88 seconds
Started Sep 11 04:56:54 AM UTC 24
Finished Sep 11 04:59:01 AM UTC 24
Peak memory 232912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2723225141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2723225141
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.3554634219
Short name T295
Test name
Test status
Simulation time 547370589 ps
CPU time 5.59 seconds
Started Sep 11 04:57:02 AM UTC 24
Finished Sep 11 04:57:09 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554634219 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3554634219
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3081874368
Short name T353
Test name
Test status
Simulation time 13392605307 ps
CPU time 161.43 seconds
Started Sep 11 04:57:00 AM UTC 24
Finished Sep 11 04:59:44 AM UTC 24
Peak memory 256388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081874368 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.3081874368
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.319399258
Short name T300
Test name
Test status
Simulation time 693532389 ps
CPU time 11.71 seconds
Started Sep 11 04:57:00 AM UTC 24
Finished Sep 11 04:57:13 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319399258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_c
trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.319399258
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3904333181
Short name T296
Test name
Test status
Simulation time 3871258078 ps
CPU time 9.18 seconds
Started Sep 11 04:56:59 AM UTC 24
Finished Sep 11 04:57:09 AM UTC 24
Peak memory 221404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904333181 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3904333181
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3876285540
Short name T314
Test name
Test status
Simulation time 530844281 ps
CPU time 29.03 seconds
Started Sep 11 04:56:58 AM UTC 24
Finished Sep 11 04:57:28 AM UTC 24
Peak memory 227680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387628554
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.3876285540
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3433360844
Short name T340
Test name
Test status
Simulation time 3567716916 ps
CPU time 86.89 seconds
Started Sep 11 04:57:01 AM UTC 24
Finished Sep 11 04:58:30 AM UTC 24
Peak memory 230864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3433360844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3433360844
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.1049924508
Short name T303
Test name
Test status
Simulation time 516471971 ps
CPU time 6.87 seconds
Started Sep 11 04:57:10 AM UTC 24
Finished Sep 11 04:57:18 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049924508 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1049924508
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3574847523
Short name T350
Test name
Test status
Simulation time 2162039978 ps
CPU time 135.68 seconds
Started Sep 11 04:57:06 AM UTC 24
Finished Sep 11 04:59:24 AM UTC 24
Peak memory 253424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574847523 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.3574847523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.2574849171
Short name T310
Test name
Test status
Simulation time 1038150023 ps
CPU time 16 seconds
Started Sep 11 04:57:09 AM UTC 24
Finished Sep 11 04:57:26 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574849171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2574849171
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.544722810
Short name T301
Test name
Test status
Simulation time 531673955 ps
CPU time 7.62 seconds
Started Sep 11 04:57:05 AM UTC 24
Finished Sep 11 04:57:13 AM UTC 24
Peak memory 221536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544722810 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.544722810
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2510118620
Short name T304
Test name
Test status
Simulation time 964767290 ps
CPU time 16.23 seconds
Started Sep 11 04:57:02 AM UTC 24
Finished Sep 11 04:57:20 AM UTC 24
Peak memory 221468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251011862
0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.2510118620
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2697400922
Short name T351
Test name
Test status
Simulation time 3515651560 ps
CPU time 135.96 seconds
Started Sep 11 04:57:10 AM UTC 24
Finished Sep 11 04:59:28 AM UTC 24
Peak memory 232912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2697400922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2697400922
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.112630535
Short name T306
Test name
Test status
Simulation time 358930378 ps
CPU time 5.17 seconds
Started Sep 11 04:57:14 AM UTC 24
Finished Sep 11 04:57:20 AM UTC 24
Peak memory 221308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112630535 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.112630535
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1055848108
Short name T349
Test name
Test status
Simulation time 9069271612 ps
CPU time 124.87 seconds
Started Sep 11 04:57:13 AM UTC 24
Finished Sep 11 04:59:20 AM UTC 24
Peak memory 221532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055848108 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.1055848108
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.1798464298
Short name T311
Test name
Test status
Simulation time 2074329914 ps
CPU time 11.01 seconds
Started Sep 11 04:57:14 AM UTC 24
Finished Sep 11 04:57:26 AM UTC 24
Peak memory 221536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798464298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1798464298
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2109750676
Short name T309
Test name
Test status
Simulation time 285338046 ps
CPU time 8.58 seconds
Started Sep 11 04:57:12 AM UTC 24
Finished Sep 11 04:57:22 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109750676 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2109750676
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3568847331
Short name T305
Test name
Test status
Simulation time 163520343 ps
CPU time 8.17 seconds
Started Sep 11 04:57:11 AM UTC 24
Finished Sep 11 04:57:20 AM UTC 24
Peak memory 221680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356884733
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.3568847331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2658304978
Short name T333
Test name
Test status
Simulation time 968946340 ps
CPU time 55.11 seconds
Started Sep 11 04:57:14 AM UTC 24
Finished Sep 11 04:58:11 AM UTC 24
Peak memory 228816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2658304978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2658304978
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3030398135
Short name T315
Test name
Test status
Simulation time 169320116 ps
CPU time 6.07 seconds
Started Sep 11 04:57:22 AM UTC 24
Finished Sep 11 04:57:29 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030398135 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3030398135
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4174101197
Short name T343
Test name
Test status
Simulation time 6545019203 ps
CPU time 91.66 seconds
Started Sep 11 04:57:20 AM UTC 24
Finished Sep 11 04:58:54 AM UTC 24
Peak memory 253448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174101197 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.4174101197
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3775746882
Short name T317
Test name
Test status
Simulation time 1507502138 ps
CPU time 12.12 seconds
Started Sep 11 04:57:21 AM UTC 24
Finished Sep 11 04:57:34 AM UTC 24
Peak memory 221528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775746882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3775746882
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.479173326
Short name T312
Test name
Test status
Simulation time 98992820 ps
CPU time 7.14 seconds
Started Sep 11 04:57:18 AM UTC 24
Finished Sep 11 04:57:27 AM UTC 24
Peak memory 221340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479173326 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.479173326
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.2037930112
Short name T313
Test name
Test status
Simulation time 1251087013 ps
CPU time 10.6 seconds
Started Sep 11 04:57:16 AM UTC 24
Finished Sep 11 04:57:28 AM UTC 24
Peak memory 223392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203793011
2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.2037930112
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.128399969
Short name T358
Test name
Test status
Simulation time 17873149885 ps
CPU time 255.54 seconds
Started Sep 11 04:57:22 AM UTC 24
Finished Sep 11 05:01:41 AM UTC 24
Peak memory 235088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=128399969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.rom_ctrl_stress_all_with_rand_reset.128399969
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1154635392
Short name T319
Test name
Test status
Simulation time 87460111 ps
CPU time 6.27 seconds
Started Sep 11 04:57:29 AM UTC 24
Finished Sep 11 04:57:37 AM UTC 24
Peak memory 221320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154635392 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1154635392
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2287768200
Short name T355
Test name
Test status
Simulation time 23834598762 ps
CPU time 138.2 seconds
Started Sep 11 04:57:27 AM UTC 24
Finished Sep 11 04:59:48 AM UTC 24
Peak memory 257384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287768200 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.2287768200
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1084104138
Short name T323
Test name
Test status
Simulation time 260838337 ps
CPU time 14.18 seconds
Started Sep 11 04:57:27 AM UTC 24
Finished Sep 11 04:57:42 AM UTC 24
Peak memory 221464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084104138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1084104138
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.2714731577
Short name T316
Test name
Test status
Simulation time 136593240 ps
CPU time 9.62 seconds
Started Sep 11 04:57:23 AM UTC 24
Finished Sep 11 04:57:33 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714731577 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2714731577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1763733181
Short name T320
Test name
Test status
Simulation time 1203348922 ps
CPU time 13.55 seconds
Started Sep 11 04:57:23 AM UTC 24
Finished Sep 11 04:57:37 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176373318
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.1763733181
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.523991212
Short name T356
Test name
Test status
Simulation time 9950932759 ps
CPU time 164.62 seconds
Started Sep 11 04:57:28 AM UTC 24
Finished Sep 11 05:00:16 AM UTC 24
Peak memory 232912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=523991212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.rom_ctrl_stress_all_with_rand_reset.523991212
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.657733995
Short name T326
Test name
Test status
Simulation time 349565647 ps
CPU time 6.75 seconds
Started Sep 11 04:57:37 AM UTC 24
Finished Sep 11 04:57:45 AM UTC 24
Peak memory 221308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657733995 -assert nopostproc +UVM_TESTNA
ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.657733995
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1501661625
Short name T357
Test name
Test status
Simulation time 3171819624 ps
CPU time 173.64 seconds
Started Sep 11 04:57:34 AM UTC 24
Finished Sep 11 05:00:31 AM UTC 24
Peak memory 245188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501661625 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.1501661625
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.3623484688
Short name T327
Test name
Test status
Simulation time 1025706147 ps
CPU time 15.11 seconds
Started Sep 11 04:57:34 AM UTC 24
Finished Sep 11 04:57:51 AM UTC 24
Peak memory 221528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623484688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3623484688
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2945231404
Short name T322
Test name
Test status
Simulation time 103928901 ps
CPU time 8.09 seconds
Started Sep 11 04:57:30 AM UTC 24
Finished Sep 11 04:57:39 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945231404 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2945231404
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.3368676311
Short name T328
Test name
Test status
Simulation time 2077986055 ps
CPU time 19.55 seconds
Started Sep 11 04:57:30 AM UTC 24
Finished Sep 11 04:57:51 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336867631
1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.3368676311
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3873651965
Short name T341
Test name
Test status
Simulation time 1579827266 ps
CPU time 70.8 seconds
Started Sep 11 04:57:35 AM UTC 24
Finished Sep 11 04:58:48 AM UTC 24
Peak memory 230992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3873651965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3873651965
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2108353808
Short name T75
Test name
Test status
Simulation time 272744074 ps
CPU time 7.09 seconds
Started Sep 11 04:51:51 AM UTC 24
Finished Sep 11 04:51:59 AM UTC 24
Peak memory 221316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108353808 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2108353808
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1403602552
Short name T33
Test name
Test status
Simulation time 260012282 ps
CPU time 10.56 seconds
Started Sep 11 04:51:47 AM UTC 24
Finished Sep 11 04:52:00 AM UTC 24
Peak memory 221348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403602552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1403602552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.3346848231
Short name T110
Test name
Test status
Simulation time 566393249 ps
CPU time 9.43 seconds
Started Sep 11 04:51:40 AM UTC 24
Finished Sep 11 04:51:51 AM UTC 24
Peak memory 221648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346848231 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3346848231
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.742145093
Short name T87
Test name
Test status
Simulation time 270254586 ps
CPU time 8.92 seconds
Started Sep 11 04:51:40 AM UTC 24
Finished Sep 11 04:51:50 AM UTC 24
Peak memory 221528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742145093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32k
B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.742145093
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.1093377163
Short name T37
Test name
Test status
Simulation time 292292721 ps
CPU time 19.03 seconds
Started Sep 11 04:51:40 AM UTC 24
Finished Sep 11 04:52:00 AM UTC 24
Peak memory 225432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109337716
3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.1093377163
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.320080138
Short name T209
Test name
Test status
Simulation time 3068423648 ps
CPU time 212.49 seconds
Started Sep 11 04:51:48 AM UTC 24
Finished Sep 11 04:55:24 AM UTC 24
Peak memory 243152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=320080138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.rom_ctrl_stress_all_with_rand_reset.320080138
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.31136261
Short name T76
Test name
Test status
Simulation time 261335308 ps
CPU time 6.95 seconds
Started Sep 11 04:52:00 AM UTC 24
Finished Sep 11 04:52:08 AM UTC 24
Peak memory 221440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31136261 -assert nopostproc +UVM_TESTNAM
E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.31136261
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.113838044
Short name T111
Test name
Test status
Simulation time 187539535 ps
CPU time 8.31 seconds
Started Sep 11 04:51:55 AM UTC 24
Finished Sep 11 04:52:04 AM UTC 24
Peak memory 221416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113838044 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.113838044
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1208421341
Short name T88
Test name
Test status
Simulation time 578225973 ps
CPU time 8.7 seconds
Started Sep 11 04:51:52 AM UTC 24
Finished Sep 11 04:52:02 AM UTC 24
Peak memory 223460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208421341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1208421341
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1800204925
Short name T38
Test name
Test status
Simulation time 412050401 ps
CPU time 25.84 seconds
Started Sep 11 04:51:52 AM UTC 24
Finished Sep 11 04:52:19 AM UTC 24
Peak memory 223384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180020492
5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.1800204925
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3099844053
Short name T128
Test name
Test status
Simulation time 4295003544 ps
CPU time 259 seconds
Started Sep 11 04:52:00 AM UTC 24
Finished Sep 11 04:56:23 AM UTC 24
Peak memory 232912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3099844053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3099844053
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2806211411
Short name T42
Test name
Test status
Simulation time 347920521 ps
CPU time 6.02 seconds
Started Sep 11 04:52:10 AM UTC 24
Finished Sep 11 04:52:18 AM UTC 24
Peak memory 221316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806211411 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2806211411
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3891794170
Short name T191
Test name
Test status
Simulation time 3092812402 ps
CPU time 165.74 seconds
Started Sep 11 04:52:05 AM UTC 24
Finished Sep 11 04:54:54 AM UTC 24
Peak memory 223588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891794170 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.3891794170
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1027908835
Short name T35
Test name
Test status
Simulation time 170553541 ps
CPU time 14.49 seconds
Started Sep 11 04:52:09 AM UTC 24
Finished Sep 11 04:52:25 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027908835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1027908835
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3118698971
Short name T41
Test name
Test status
Simulation time 539129424 ps
CPU time 8.72 seconds
Started Sep 11 04:52:03 AM UTC 24
Finished Sep 11 04:52:13 AM UTC 24
Peak memory 221392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118698971 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3118698971
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3183604192
Short name T65
Test name
Test status
Simulation time 97172811 ps
CPU time 7.46 seconds
Started Sep 11 04:52:01 AM UTC 24
Finished Sep 11 04:52:10 AM UTC 24
Peak memory 223380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183604192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3183604192
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.3783341879
Short name T45
Test name
Test status
Simulation time 1731557676 ps
CPU time 21.78 seconds
Started Sep 11 04:52:02 AM UTC 24
Finished Sep 11 04:52:25 AM UTC 24
Peak memory 225512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378334187
9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.3783341879
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3601592660
Short name T62
Test name
Test status
Simulation time 3556409134 ps
CPU time 133.99 seconds
Started Sep 11 04:52:09 AM UTC 24
Finished Sep 11 04:54:26 AM UTC 24
Peak memory 232912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3601592660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3601592660
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3975585022
Short name T46
Test name
Test status
Simulation time 92753964 ps
CPU time 6.31 seconds
Started Sep 11 04:52:20 AM UTC 24
Finished Sep 11 04:52:27 AM UTC 24
Peak memory 221316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975585022 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3975585022
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2946013777
Short name T47
Test name
Test status
Simulation time 1967933807 ps
CPU time 94.2 seconds
Started Sep 11 04:52:14 AM UTC 24
Finished Sep 11 04:53:50 AM UTC 24
Peak memory 257028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946013777 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.2946013777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.1105757867
Short name T136
Test name
Test status
Simulation time 1045007562 ps
CPU time 13.16 seconds
Started Sep 11 04:52:18 AM UTC 24
Finished Sep 11 04:52:32 AM UTC 24
Peak memory 221344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105757867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1105757867
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1733712839
Short name T44
Test name
Test status
Simulation time 534012683 ps
CPU time 9.05 seconds
Started Sep 11 04:52:14 AM UTC 24
Finished Sep 11 04:52:24 AM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733712839 -assert nopostproc +UVM_TESTNAME=rom_ctr
l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1733712839
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.4097266442
Short name T43
Test name
Test status
Simulation time 2256873321 ps
CPU time 8.95 seconds
Started Sep 11 04:52:11 AM UTC 24
Finished Sep 11 04:52:21 AM UTC 24
Peak memory 221528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097266442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4097266442
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2764040682
Short name T15
Test name
Test status
Simulation time 1523893104 ps
CPU time 62.83 seconds
Started Sep 11 04:52:19 AM UTC 24
Finished Sep 11 04:53:23 AM UTC 24
Peak memory 230720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2764040682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2764040682
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.3384523797
Short name T135
Test name
Test status
Simulation time 445037656 ps
CPU time 6.39 seconds
Started Sep 11 04:52:31 AM UTC 24
Finished Sep 11 04:52:39 AM UTC 24
Peak memory 221324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384523797 -assert nopostproc +UVM_TESTN
AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3384523797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2324008003
Short name T57
Test name
Test status
Simulation time 2368789244 ps
CPU time 166.24 seconds
Started Sep 11 04:52:26 AM UTC 24
Finished Sep 11 04:55:15 AM UTC 24
Peak memory 253396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324008003 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.2324008003
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.3798224738
Short name T139
Test name
Test status
Simulation time 249739933 ps
CPU time 15.87 seconds
Started Sep 11 04:52:28 AM UTC 24
Finished Sep 11 04:52:45 AM UTC 24
Peak memory 221600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798224738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_
ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3798224738
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.926748428
Short name T130
Test name
Test status
Simulation time 281889759 ps
CPU time 9.46 seconds
Started Sep 11 04:52:26 AM UTC 24
Finished Sep 11 04:52:37 AM UTC 24
Peak memory 221352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926748428 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.926748428
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2743129233
Short name T58
Test name
Test status
Simulation time 189259243 ps
CPU time 8.47 seconds
Started Sep 11 04:52:21 AM UTC 24
Finished Sep 11 04:52:31 AM UTC 24
Peak memory 223652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743129233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32
kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2743129233
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.343912800
Short name T141
Test name
Test status
Simulation time 2627730987 ps
CPU time 14.06 seconds
Started Sep 11 04:52:24 AM UTC 24
Finished Sep 11 04:52:39 AM UTC 24
Peak memory 225500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343912800
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.343912800
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.80575931
Short name T61
Test name
Test status
Simulation time 9645123712 ps
CPU time 102.49 seconds
Started Sep 11 04:52:31 AM UTC 24
Finished Sep 11 04:54:16 AM UTC 24
Peak memory 233160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=80575931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 9.rom_ctrl_stress_all_with_rand_reset.80575931
Directory /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest
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