| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.42 | 96.89 | 92.13 | 97.67 | 100.00 | 98.28 | 97.90 | 99.06 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 63.04 | 63.04 | 92.58 | 92.58 | 67.56 | 67.56 | 49.30 | 49.30 | 40.00 | 40.00 | 88.97 | 88.97 | 94.00 | 94.00 | 8.90 | 8.90 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2932225118 |
| 78.38 | 15.33 | 92.94 | 0.36 | 74.58 | 7.02 | 69.92 | 20.62 | 40.00 | 0.00 | 90.69 | 1.72 | 95.50 | 1.50 | 85.01 | 76.11 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1336905808 |
| 83.13 | 4.75 | 93.54 | 0.60 | 75.98 | 1.40 | 77.50 | 7.58 | 60.00 | 20.00 | 93.10 | 2.41 | 95.80 | 0.30 | 85.95 | 0.94 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3625826688 |
| 87.71 | 4.58 | 93.54 | 0.00 | 78.93 | 2.95 | 77.85 | 0.35 | 86.67 | 26.67 | 94.14 | 1.03 | 95.95 | 0.15 | 86.89 | 0.94 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2198817170 |
| 91.20 | 3.49 | 96.53 | 2.99 | 83.85 | 4.92 | 91.15 | 13.30 | 86.67 | 0.00 | 95.17 | 1.03 | 96.25 | 0.30 | 88.76 | 1.87 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1002236890 |
| 92.42 | 1.23 | 96.53 | 0.00 | 87.36 | 3.51 | 94.95 | 3.80 | 86.67 | 0.00 | 95.52 | 0.34 | 96.25 | 0.00 | 89.70 | 0.94 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1856368250 |
| 93.54 | 1.12 | 96.77 | 0.24 | 88.06 | 0.70 | 94.95 | 0.00 | 86.67 | 0.00 | 96.55 | 1.03 | 96.25 | 0.00 | 95.55 | 5.85 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.80974595 |
| 94.65 | 1.11 | 96.89 | 0.12 | 88.20 | 0.14 | 94.95 | 0.00 | 93.33 | 6.67 | 96.90 | 0.34 | 96.25 | 0.00 | 96.02 | 0.47 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.689970851 |
| 95.67 | 1.02 | 96.89 | 0.00 | 88.48 | 0.28 | 95.15 | 0.20 | 100.00 | 6.67 | 96.90 | 0.00 | 96.25 | 0.00 | 96.02 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3468098958 |
| 96.17 | 0.50 | 96.89 | 0.00 | 89.75 | 1.26 | 96.47 | 1.32 | 100.00 | 0.00 | 97.59 | 0.69 | 96.25 | 0.00 | 96.25 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.232431032 |
| 96.42 | 0.24 | 96.89 | 0.00 | 91.01 | 1.26 | 96.58 | 0.10 | 100.00 | 0.00 | 97.93 | 0.34 | 96.25 | 0.00 | 96.25 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.4100241405 |
| 96.65 | 0.23 | 96.89 | 0.00 | 91.01 | 0.00 | 96.58 | 0.00 | 100.00 | 0.00 | 97.93 | 0.00 | 96.25 | 0.00 | 97.89 | 1.64 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.305187099 |
| 96.85 | 0.20 | 96.89 | 0.00 | 91.57 | 0.56 | 96.62 | 0.05 | 100.00 | 0.00 | 97.93 | 0.00 | 96.55 | 0.30 | 98.36 | 0.47 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2288749427 |
| 97.04 | 0.19 | 96.89 | 0.00 | 91.71 | 0.14 | 96.62 | 0.00 | 100.00 | 0.00 | 97.93 | 0.00 | 97.75 | 1.20 | 98.36 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1325887259 |
| 97.14 | 0.10 | 96.89 | 0.00 | 91.85 | 0.14 | 96.85 | 0.23 | 100.00 | 0.00 | 98.28 | 0.34 | 97.75 | 0.00 | 98.36 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1555597802 |
| 97.21 | 0.07 | 96.89 | 0.00 | 91.85 | 0.00 | 97.33 | 0.47 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 98.36 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2640088060 |
| 97.26 | 0.05 | 96.89 | 0.00 | 91.85 | 0.00 | 97.42 | 0.10 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 98.59 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2745186055 |
| 97.29 | 0.03 | 96.89 | 0.00 | 91.99 | 0.14 | 97.53 | 0.10 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 98.59 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.3324367744 |
| 97.32 | 0.03 | 96.89 | 0.00 | 91.99 | 0.00 | 97.53 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 98.83 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2578792501 |
| 97.36 | 0.03 | 96.89 | 0.00 | 91.99 | 0.00 | 97.53 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.75 | 0.00 | 99.06 | 0.23 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.999996697 |
| 97.38 | 0.02 | 96.89 | 0.00 | 91.99 | 0.00 | 97.53 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.90 | 0.15 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2569515036 |
| 97.40 | 0.02 | 96.89 | 0.00 | 92.13 | 0.14 | 97.53 | 0.00 | 100.00 | 0.00 | 98.28 | 0.00 | 97.90 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3181214225 |
| 97.41 | 0.01 | 96.89 | 0.00 | 92.13 | 0.00 | 97.62 | 0.10 | 100.00 | 0.00 | 98.28 | 0.00 | 97.90 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.2634031497 |
| 97.42 | 0.01 | 96.89 | 0.00 | 92.13 | 0.00 | 97.67 | 0.05 | 100.00 | 0.00 | 98.28 | 0.00 | 97.90 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.3037592835 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4110831949 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.701042153 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1439223355 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.797817364 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3275339960 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2872197989 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2439327312 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2980177976 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2584179103 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1985491111 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.467673659 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1519056159 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.177570723 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.970970720 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1862730378 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2209255902 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1853186944 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3077427433 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2488366905 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2757089340 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3666717389 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4132750897 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.661630047 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1985813208 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4154697425 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3482371205 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3749796139 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.948364260 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.710676234 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2045435591 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3011691603 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2673895362 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1058755939 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1714277262 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3159983836 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.7196521 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3938664265 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.225655785 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4194512171 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3373186322 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4262464451 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3999651382 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.230260652 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1284457085 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3868790659 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3434731403 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1994294437 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3776075927 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.329570780 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.583396793 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1323447898 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.907665085 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1883349710 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.293207791 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.527907121 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.665614520 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2486419064 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1843030533 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1429751281 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1402077823 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3411943880 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.842970299 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4199622571 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1000667685 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2348492783 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2332453121 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2649786107 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.210468733 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1216143138 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.832910099 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3678833061 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.933129303 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3955604868 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4094158746 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3056155663 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3685008359 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4014594540 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.522213387 |
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| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.1467435344 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1056907737 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.681991417 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.45526618 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.758845242 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3824145803 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.401783042 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1212548953 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.1521371656 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1056977025 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3783715743 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1676728618 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.2827216901 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2134049413 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3469011433 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2167681924 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1476973336 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.3679333016 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1418024521 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.4002647908 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2566224897 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2910159413 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.1861729735 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.58533866 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.2116520068 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2723225141 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.3554634219 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3081874368 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.319399258 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3904333181 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3876285540 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3433360844 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.1049924508 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3574847523 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.2574849171 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.544722810 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2510118620 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2697400922 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.112630535 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1055848108 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.1798464298 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2109750676 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3568847331 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2658304978 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.3030398135 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4174101197 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3775746882 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.479173326 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.2037930112 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.128399969 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1154635392 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2287768200 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1084104138 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.2714731577 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1763733181 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.523991212 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.657733995 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1501661625 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.3623484688 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2945231404 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.3368676311 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3873651965 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2108353808 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1403602552 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.3346848231 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.742145093 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.1093377163 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.320080138 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.31136261 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.113838044 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1208421341 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1800204925 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3099844053 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2806211411 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3891794170 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1027908835 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3118698971 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3183604192 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.3783341879 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3601592660 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3975585022 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2946013777 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.1105757867 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1733712839 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.4097266442 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2764040682 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.3384523797 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2324008003 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.3798224738 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.926748428 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2743129233 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.343912800 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.80575931 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.4225257187 | Sep 11 04:51:10 AM UTC 24 | Sep 11 04:51:18 AM UTC 24 | 203262110 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.1705575433 | Sep 11 04:51:09 AM UTC 24 | Sep 11 04:51:18 AM UTC 24 | 186644042 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.3324367744 | Sep 11 04:51:11 AM UTC 24 | Sep 11 04:51:18 AM UTC 24 | 350941179 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.2759120243 | Sep 11 04:51:13 AM UTC 24 | Sep 11 04:51:20 AM UTC 24 | 130939411 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.3766038573 | Sep 11 04:51:11 AM UTC 24 | Sep 11 04:51:20 AM UTC 24 | 97249773 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3826141017 | Sep 11 04:51:11 AM UTC 24 | Sep 11 04:51:21 AM UTC 24 | 141678455 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3625826688 | Sep 11 04:51:11 AM UTC 24 | Sep 11 04:51:22 AM UTC 24 | 169639125 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2932225118 | Sep 11 04:51:11 AM UTC 24 | Sep 11 04:51:25 AM UTC 24 | 224061092 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.3685020100 | Sep 11 04:51:10 AM UTC 24 | Sep 11 04:51:26 AM UTC 24 | 195533618 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1657703198 | Sep 11 04:51:17 AM UTC 24 | Sep 11 04:51:26 AM UTC 24 | 97047396 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.604814725 | Sep 11 04:51:19 AM UTC 24 | Sep 11 04:51:28 AM UTC 24 | 364748761 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.4100241405 | Sep 11 04:51:22 AM UTC 24 | Sep 11 04:51:29 AM UTC 24 | 346285140 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.973863293 | Sep 11 04:51:19 AM UTC 24 | Sep 11 04:51:30 AM UTC 24 | 578407624 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1856368250 | Sep 11 04:51:09 AM UTC 24 | Sep 11 04:51:30 AM UTC 24 | 4149529198 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1921117268 | Sep 11 04:51:23 AM UTC 24 | Sep 11 04:51:33 AM UTC 24 | 140521907 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3920523412 | Sep 11 04:51:20 AM UTC 24 | Sep 11 04:51:35 AM UTC 24 | 691509271 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.2225324652 | Sep 11 04:51:25 AM UTC 24 | Sep 11 04:51:35 AM UTC 24 | 372925536 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.2824852607 | Sep 11 04:51:30 AM UTC 24 | Sep 11 04:51:38 AM UTC 24 | 539972405 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3590478237 | Sep 11 04:51:30 AM UTC 24 | Sep 11 04:51:39 AM UTC 24 | 364001257 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.2181491447 | Sep 11 04:51:31 AM UTC 24 | Sep 11 04:51:40 AM UTC 24 | 99643768 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.229414841 | Sep 11 04:51:35 AM UTC 24 | Sep 11 04:51:45 AM UTC 24 | 670988867 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.239082031 | Sep 11 04:51:39 AM UTC 24 | Sep 11 04:51:46 AM UTC 24 | 88309199 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.742145093 | Sep 11 04:51:40 AM UTC 24 | Sep 11 04:51:50 AM UTC 24 | 270254586 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.3346848231 | Sep 11 04:51:40 AM UTC 24 | Sep 11 04:51:51 AM UTC 24 | 566393249 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2745186055 | Sep 11 04:51:26 AM UTC 24 | Sep 11 04:51:51 AM UTC 24 | 1039916037 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.3037592835 | Sep 11 04:51:25 AM UTC 24 | Sep 11 04:51:55 AM UTC 24 | 1380864879 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2108353808 | Sep 11 04:51:51 AM UTC 24 | Sep 11 04:51:59 AM UTC 24 | 272744074 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1403602552 | Sep 11 04:51:47 AM UTC 24 | Sep 11 04:52:00 AM UTC 24 | 260012282 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.1093377163 | Sep 11 04:51:40 AM UTC 24 | Sep 11 04:52:00 AM UTC 24 | 292292721 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1208421341 | Sep 11 04:51:52 AM UTC 24 | Sep 11 04:52:02 AM UTC 24 | 578225973 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.113838044 | Sep 11 04:51:55 AM UTC 24 | Sep 11 04:52:04 AM UTC 24 | 187539535 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.31136261 | Sep 11 04:52:00 AM UTC 24 | Sep 11 04:52:08 AM UTC 24 | 261335308 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1002236890 | Sep 11 04:51:27 AM UTC 24 | Sep 11 04:52:08 AM UTC 24 | 2766852863 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.3183604192 | Sep 11 04:52:01 AM UTC 24 | Sep 11 04:52:10 AM UTC 24 | 97172811 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.1467435344 | Sep 11 04:51:31 AM UTC 24 | Sep 11 04:52:10 AM UTC 24 | 596984831 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1555597802 | Sep 11 04:51:56 AM UTC 24 | Sep 11 04:52:11 AM UTC 24 | 665408856 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1214415094 | Sep 11 04:51:11 AM UTC 24 | Sep 11 04:52:13 AM UTC 24 | 218548827 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3118698971 | Sep 11 04:52:03 AM UTC 24 | Sep 11 04:52:13 AM UTC 24 | 539129424 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2922108994 | Sep 11 04:51:21 AM UTC 24 | Sep 11 04:52:17 AM UTC 24 | 2673365017 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2806211411 | Sep 11 04:52:10 AM UTC 24 | Sep 11 04:52:18 AM UTC 24 | 347920521 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1800204925 | Sep 11 04:51:52 AM UTC 24 | Sep 11 04:52:19 AM UTC 24 | 412050401 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.4097266442 | Sep 11 04:52:11 AM UTC 24 | Sep 11 04:52:21 AM UTC 24 | 2256873321 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1733712839 | Sep 11 04:52:14 AM UTC 24 | Sep 11 04:52:24 AM UTC 24 | 534012683 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1027908835 | Sep 11 04:52:09 AM UTC 24 | Sep 11 04:52:25 AM UTC 24 | 170553541 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.3783341879 | Sep 11 04:52:02 AM UTC 24 | Sep 11 04:52:25 AM UTC 24 | 1731557676 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3975585022 | Sep 11 04:52:20 AM UTC 24 | Sep 11 04:52:27 AM UTC 24 | 92753964 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.232431032 | Sep 11 04:52:12 AM UTC 24 | Sep 11 04:52:31 AM UTC 24 | 317699882 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2743129233 | Sep 11 04:52:21 AM UTC 24 | Sep 11 04:52:31 AM UTC 24 | 189259243 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.1993151080 | Sep 11 04:51:29 AM UTC 24 | Sep 11 04:52:31 AM UTC 24 | 557951317 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.1105757867 | Sep 11 04:52:18 AM UTC 24 | Sep 11 04:52:32 AM UTC 24 | 1045007562 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.926748428 | Sep 11 04:52:26 AM UTC 24 | Sep 11 04:52:37 AM UTC 24 | 281889759 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.3384523797 | Sep 11 04:52:31 AM UTC 24 | Sep 11 04:52:39 AM UTC 24 | 445037656 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.2809554103 | Sep 11 04:52:33 AM UTC 24 | Sep 11 04:52:39 AM UTC 24 | 341745470 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.343912800 | Sep 11 04:52:24 AM UTC 24 | Sep 11 04:52:39 AM UTC 24 | 2627730987 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.3798224738 | Sep 11 04:52:28 AM UTC 24 | Sep 11 04:52:45 AM UTC 24 | 249739933 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.2443436657 | Sep 11 04:52:40 AM UTC 24 | Sep 11 04:52:47 AM UTC 24 | 347816637 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.2634031497 | Sep 11 04:52:32 AM UTC 24 | Sep 11 04:52:51 AM UTC 24 | 227411858 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.3075046853 | Sep 11 04:52:55 AM UTC 24 | Sep 11 04:53:17 AM UTC 24 | 378065007 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.2521837162 | Sep 11 04:52:40 AM UTC 24 | Sep 11 04:52:52 AM UTC 24 | 350791914 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2829979098 | Sep 11 04:51:36 AM UTC 24 | Sep 11 04:52:54 AM UTC 24 | 145358888 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.2665314286 | Sep 11 04:52:46 AM UTC 24 | Sep 11 04:52:55 AM UTC 24 | 281862284 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.423439056 | Sep 11 04:52:52 AM UTC 24 | Sep 11 04:53:00 AM UTC 24 | 656653245 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1336905808 | Sep 11 04:51:21 AM UTC 24 | Sep 11 04:53:01 AM UTC 24 | 1683176211 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.897498744 | Sep 11 04:51:10 AM UTC 24 | Sep 11 04:53:01 AM UTC 24 | 3542987671 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3109796771 | Sep 11 04:52:45 AM UTC 24 | Sep 11 04:53:03 AM UTC 24 | 1140832862 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.2806988574 | Sep 11 04:52:56 AM UTC 24 | Sep 11 04:53:06 AM UTC 24 | 428806253 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.4143916250 | Sep 11 04:52:50 AM UTC 24 | Sep 11 04:53:06 AM UTC 24 | 480656717 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.1823436607 | Sep 11 04:53:02 AM UTC 24 | Sep 11 04:53:09 AM UTC 24 | 89135085 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.4054970466 | Sep 11 04:53:04 AM UTC 24 | Sep 11 04:53:13 AM UTC 24 | 558614400 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2640088060 | Sep 11 04:51:56 AM UTC 24 | Sep 11 04:53:16 AM UTC 24 | 1283902544 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.4223766932 | Sep 11 04:53:14 AM UTC 24 | Sep 11 04:53:29 AM UTC 24 | 401137810 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.1447237207 | Sep 11 04:53:02 AM UTC 24 | Sep 11 04:53:19 AM UTC 24 | 863419853 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.2474987900 | Sep 11 04:53:07 AM UTC 24 | Sep 11 04:53:20 AM UTC 24 | 693534916 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.684411515 | Sep 11 04:53:14 AM UTC 24 | Sep 11 04:53:21 AM UTC 24 | 347034028 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.2178827699 | Sep 11 04:53:03 AM UTC 24 | Sep 11 04:53:22 AM UTC 24 | 390619700 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2764040682 | Sep 11 04:52:19 AM UTC 24 | Sep 11 04:53:23 AM UTC 24 | 1523893104 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1894271021 | Sep 11 04:53:17 AM UTC 24 | Sep 11 04:53:25 AM UTC 24 | 139581697 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1056907737 | Sep 11 04:51:36 AM UTC 24 | Sep 11 04:53:27 AM UTC 24 | 7773961766 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2759844017 | Sep 11 04:51:11 AM UTC 24 | Sep 11 04:53:28 AM UTC 24 | 6355862938 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.2036334043 | Sep 11 04:53:21 AM UTC 24 | Sep 11 04:53:29 AM UTC 24 | 89461626 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2288749427 | Sep 11 04:51:10 AM UTC 24 | Sep 11 04:53:33 AM UTC 24 | 909990829 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3663736037 | Sep 11 04:51:10 AM UTC 24 | Sep 11 04:53:32 AM UTC 24 | 2191487199 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.1507383586 | Sep 11 04:53:25 AM UTC 24 | Sep 11 04:53:33 AM UTC 24 | 635565946 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.1855950892 | Sep 11 04:53:20 AM UTC 24 | Sep 11 04:53:35 AM UTC 24 | 517532661 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.2684816891 | Sep 11 04:53:30 AM UTC 24 | Sep 11 04:53:39 AM UTC 24 | 126189268 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.3600960008 | Sep 11 04:53:33 AM UTC 24 | Sep 11 04:53:44 AM UTC 24 | 1235415877 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.1579419401 | Sep 11 04:53:28 AM UTC 24 | Sep 11 04:53:46 AM UTC 24 | 1040767460 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2784450915 | Sep 11 04:52:40 AM UTC 24 | Sep 11 04:53:48 AM UTC 24 | 2575635915 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.2334154797 | Sep 11 04:53:39 AM UTC 24 | Sep 11 04:53:48 AM UTC 24 | 262200584 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2946013777 | Sep 11 04:52:14 AM UTC 24 | Sep 11 04:53:50 AM UTC 24 | 1967933807 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.2600436089 | Sep 11 04:53:24 AM UTC 24 | Sep 11 04:53:50 AM UTC 24 | 283728670 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.526221532 | Sep 11 04:53:34 AM UTC 24 | Sep 11 04:53:50 AM UTC 24 | 697152791 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.235862213 | Sep 11 04:53:30 AM UTC 24 | Sep 11 04:53:51 AM UTC 24 | 2332267036 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2198817170 | Sep 11 04:51:34 AM UTC 24 | Sep 11 04:53:55 AM UTC 24 | 5855094548 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.1272908083 | Sep 11 04:53:46 AM UTC 24 | Sep 11 04:53:57 AM UTC 24 | 1017019418 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1547223631 | Sep 11 04:53:51 AM UTC 24 | Sep 11 04:53:58 AM UTC 24 | 178412407 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.4076693672 | Sep 11 04:53:51 AM UTC 24 | Sep 11 04:54:00 AM UTC 24 | 97444738 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1339370688 | Sep 11 04:53:44 AM UTC 24 | Sep 11 04:54:03 AM UTC 24 | 568549523 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.2250987014 | Sep 11 04:53:49 AM UTC 24 | Sep 11 04:54:04 AM UTC 24 | 177685244 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.2345270986 | Sep 11 04:53:59 AM UTC 24 | Sep 11 04:54:06 AM UTC 24 | 85726491 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2639237946 | Sep 11 04:53:56 AM UTC 24 | Sep 11 04:54:08 AM UTC 24 | 669532498 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3468098958 | Sep 11 04:51:46 AM UTC 24 | Sep 11 04:54:10 AM UTC 24 | 9271954940 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3106371231 | Sep 11 04:53:51 AM UTC 24 | Sep 11 04:54:11 AM UTC 24 | 268412857 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.2626728197 | Sep 11 04:54:02 AM UTC 24 | Sep 11 04:54:11 AM UTC 24 | 381107095 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.27325759 | Sep 11 04:54:01 AM UTC 24 | Sep 11 04:54:13 AM UTC 24 | 215325117 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.969353711 | Sep 11 04:54:07 AM UTC 24 | Sep 11 04:54:14 AM UTC 24 | 89524231 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.80575931 | Sep 11 04:52:31 AM UTC 24 | Sep 11 04:54:16 AM UTC 24 | 9645123712 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.1855205695 | Sep 11 04:54:11 AM UTC 24 | Sep 11 04:54:20 AM UTC 24 | 136529526 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.1069419462 | Sep 11 04:54:05 AM UTC 24 | Sep 11 04:54:20 AM UTC 24 | 1076341042 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2853118000 | Sep 11 04:53:00 AM UTC 24 | Sep 11 04:54:21 AM UTC 24 | 1446646615 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.1150310862 | Sep 11 04:54:15 AM UTC 24 | Sep 11 04:54:23 AM UTC 24 | 831689893 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.1391066326 | Sep 11 04:54:09 AM UTC 24 | Sep 11 04:54:25 AM UTC 24 | 614701735 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3601592660 | Sep 11 04:52:09 AM UTC 24 | Sep 11 04:54:26 AM UTC 24 | 3556409134 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3616081220 | Sep 11 04:54:20 AM UTC 24 | Sep 11 04:54:26 AM UTC 24 | 541469886 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.1849041504 | Sep 11 04:54:12 AM UTC 24 | Sep 11 04:54:28 AM UTC 24 | 2073872629 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.3878903346 | Sep 11 04:54:24 AM UTC 24 | Sep 11 04:54:30 AM UTC 24 | 234686811 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3452425831 | Sep 11 04:51:20 AM UTC 24 | Sep 11 04:54:30 AM UTC 24 | 5273181831 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.842617359 | Sep 11 04:52:48 AM UTC 24 | Sep 11 04:54:31 AM UTC 24 | 2182403083 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1850009388 | Sep 11 04:52:38 AM UTC 24 | Sep 11 04:54:33 AM UTC 24 | 7879177829 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.3469312287 | Sep 11 04:54:21 AM UTC 24 | Sep 11 04:54:35 AM UTC 24 | 696294444 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.4147546185 | Sep 11 04:53:29 AM UTC 24 | Sep 11 04:54:37 AM UTC 24 | 13096025748 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2464065000 | Sep 11 04:54:26 AM UTC 24 | Sep 11 04:54:37 AM UTC 24 | 1118702066 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.3641649796 | Sep 11 04:54:26 AM UTC 24 | Sep 11 04:54:39 AM UTC 24 | 409069641 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.765683500 | Sep 11 04:54:32 AM UTC 24 | Sep 11 04:54:39 AM UTC 24 | 260700162 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2670039919 | Sep 11 04:54:32 AM UTC 24 | Sep 11 04:54:40 AM UTC 24 | 95890430 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.3416343201 | Sep 11 04:54:29 AM UTC 24 | Sep 11 04:54:41 AM UTC 24 | 508484219 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.2271141614 | Sep 11 04:54:17 AM UTC 24 | Sep 11 04:54:41 AM UTC 24 | 434260025 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.1772211108 | Sep 11 04:54:32 AM UTC 24 | Sep 11 04:54:44 AM UTC 24 | 686746912 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.113625636 | Sep 11 04:54:35 AM UTC 24 | Sep 11 04:54:47 AM UTC 24 | 497710465 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.776340028 | Sep 11 04:54:38 AM UTC 24 | Sep 11 04:54:50 AM UTC 24 | 529049907 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.2186071072 | Sep 11 04:54:40 AM UTC 24 | Sep 11 04:54:51 AM UTC 24 | 780983781 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2661352838 | Sep 11 04:51:26 AM UTC 24 | Sep 11 04:54:53 AM UTC 24 | 10193813980 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.655971071 | Sep 11 04:54:45 AM UTC 24 | Sep 11 04:54:54 AM UTC 24 | 691161913 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3891794170 | Sep 11 04:52:05 AM UTC 24 | Sep 11 04:54:54 AM UTC 24 | 3092812402 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2371046724 | Sep 11 04:53:49 AM UTC 24 | Sep 11 04:54:55 AM UTC 24 | 1377783385 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.2755278529 | Sep 11 04:54:41 AM UTC 24 | Sep 11 04:54:57 AM UTC 24 | 875208081 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.1108860589 | Sep 11 04:54:48 AM UTC 24 | Sep 11 04:54:58 AM UTC 24 | 1516756134 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2250377349 | Sep 11 04:54:40 AM UTC 24 | Sep 11 04:55:01 AM UTC 24 | 1810265543 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.1087556045 | Sep 11 04:54:55 AM UTC 24 | Sep 11 04:55:01 AM UTC 24 | 1654488882 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.3462841055 | Sep 11 04:54:47 AM UTC 24 | Sep 11 04:55:04 AM UTC 24 | 292825574 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1606707171 | Sep 11 04:53:34 AM UTC 24 | Sep 11 04:55:04 AM UTC 24 | 3376343056 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1515561692 | Sep 11 04:54:56 AM UTC 24 | Sep 11 04:55:07 AM UTC 24 | 276569751 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.37889661 | Sep 11 04:55:01 AM UTC 24 | Sep 11 04:55:09 AM UTC 24 | 825173176 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.1912307445 | Sep 11 04:54:52 AM UTC 24 | Sep 11 04:55:09 AM UTC 24 | 337452985 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1907515946 | Sep 11 04:53:07 AM UTC 24 | Sep 11 04:55:13 AM UTC 24 | 1999378687 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.2351240295 | Sep 11 04:55:05 AM UTC 24 | Sep 11 04:55:14 AM UTC 24 | 676918804 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2324008003 | Sep 11 04:52:26 AM UTC 24 | Sep 11 04:55:15 AM UTC 24 | 2368789244 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.2533611449 | Sep 11 04:54:58 AM UTC 24 | Sep 11 04:55:16 AM UTC 24 | 448612682 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.773246500 | Sep 11 04:55:14 AM UTC 24 | Sep 11 04:55:19 AM UTC 24 | 337098917 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3503803367 | Sep 11 04:53:18 AM UTC 24 | Sep 11 04:55:19 AM UTC 24 | 1528905268 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2785556611 | Sep 11 04:54:55 AM UTC 24 | Sep 11 04:55:21 AM UTC 24 | 1897893040 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1705458351 | Sep 11 04:54:14 AM UTC 24 | Sep 11 04:55:21 AM UTC 24 | 2565125323 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.2442366260 | Sep 11 04:55:10 AM UTC 24 | Sep 11 04:55:23 AM UTC 24 | 504037140 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3961615304 | Sep 11 04:53:02 AM UTC 24 | Sep 11 04:55:23 AM UTC 24 | 6835701798 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.320080138 | Sep 11 04:51:48 AM UTC 24 | Sep 11 04:55:24 AM UTC 24 | 3068423648 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1721208402 | Sep 11 04:55:16 AM UTC 24 | Sep 11 04:55:26 AM UTC 24 | 135132643 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.2554857878 | Sep 11 04:55:04 AM UTC 24 | Sep 11 04:55:26 AM UTC 24 | 550039219 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2169126155 | Sep 11 04:53:52 AM UTC 24 | Sep 11 04:55:28 AM UTC 24 | 1400762126 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.52235916 | Sep 11 04:53:35 AM UTC 24 | Sep 11 04:55:29 AM UTC 24 | 2599607866 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.2178001483 | Sep 11 04:55:22 AM UTC 24 | Sep 11 04:55:29 AM UTC 24 | 126101536 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.893240866 | Sep 11 04:55:23 AM UTC 24 | Sep 11 04:55:31 AM UTC 24 | 98513871 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3656575962 | Sep 11 04:54:37 AM UTC 24 | Sep 11 04:55:32 AM UTC 24 | 7494514059 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.1261164690 | Sep 11 04:55:27 AM UTC 24 | Sep 11 04:55:34 AM UTC 24 | 105162226 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.772327919 | Sep 11 04:55:20 AM UTC 24 | Sep 11 04:55:35 AM UTC 24 | 997499788 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.1849225298 | Sep 11 04:55:22 AM UTC 24 | Sep 11 04:55:38 AM UTC 24 | 2774628733 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.369919504 | Sep 11 04:54:27 AM UTC 24 | Sep 11 04:55:39 AM UTC 24 | 3373855092 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.208217732 | Sep 11 04:55:24 AM UTC 24 | Sep 11 04:55:39 AM UTC 24 | 270033179 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.807001255 | Sep 11 04:55:29 AM UTC 24 | Sep 11 04:55:40 AM UTC 24 | 292456464 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.4243592943 | Sep 11 04:55:32 AM UTC 24 | Sep 11 04:55:40 AM UTC 24 | 126363845 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.1506720267 | Sep 11 04:55:15 AM UTC 24 | Sep 11 04:55:41 AM UTC 24 | 304887691 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.3694135914 | Sep 11 04:55:30 AM UTC 24 | Sep 11 04:55:43 AM UTC 24 | 350134799 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1265008074 | Sep 11 04:53:26 AM UTC 24 | Sep 11 04:55:44 AM UTC 24 | 26267349241 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3426203174 | Sep 11 04:54:04 AM UTC 24 | Sep 11 04:55:44 AM UTC 24 | 6500464341 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.689970851 | Sep 11 04:52:52 AM UTC 24 | Sep 11 04:55:45 AM UTC 24 | 5904319134 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.141423804 | Sep 11 04:55:27 AM UTC 24 | Sep 11 04:55:46 AM UTC 24 | 1462898126 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2975427140 | Sep 11 04:55:35 AM UTC 24 | Sep 11 04:55:46 AM UTC 24 | 144479255 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.1434360133 | Sep 11 04:55:39 AM UTC 24 | Sep 11 04:55:46 AM UTC 24 | 591497207 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.220104310 | Sep 11 04:53:49 AM UTC 24 | Sep 11 04:55:47 AM UTC 24 | 13701884129 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.1237483726 | Sep 11 04:55:40 AM UTC 24 | Sep 11 04:55:48 AM UTC 24 | 137613210 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.154547700 | Sep 11 04:55:33 AM UTC 24 | Sep 11 04:55:50 AM UTC 24 | 1362445907 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1928289877 | Sep 11 04:53:58 AM UTC 24 | Sep 11 04:55:51 AM UTC 24 | 1602137196 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.2871706226 | Sep 11 04:55:39 AM UTC 24 | Sep 11 04:55:51 AM UTC 24 | 342867361 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2783037906 | Sep 11 04:55:40 AM UTC 24 | Sep 11 04:55:53 AM UTC 24 | 176357284 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.3162257539 | Sep 11 04:55:46 AM UTC 24 | Sep 11 04:55:54 AM UTC 24 | 127091582 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.2906735000 | Sep 11 04:55:47 AM UTC 24 | Sep 11 04:55:55 AM UTC 24 | 528030429 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.4257149632 | Sep 11 04:55:49 AM UTC 24 | Sep 11 04:55:55 AM UTC 24 | 85489894 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.627677688 | Sep 11 04:55:44 AM UTC 24 | Sep 11 04:55:55 AM UTC 24 | 175334663 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1653327795 | Sep 11 04:55:01 AM UTC 24 | Sep 11 04:55:59 AM UTC 24 | 1740153604 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.1643040848 | Sep 11 04:55:51 AM UTC 24 | Sep 11 04:56:02 AM UTC 24 | 136358478 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.2079350173 | Sep 11 04:55:55 AM UTC 24 | Sep 11 04:56:02 AM UTC 24 | 520574731 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.508793636 | Sep 11 04:54:41 AM UTC 24 | Sep 11 04:56:03 AM UTC 24 | 2086035148 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.2570641355 | Sep 11 04:55:56 AM UTC 24 | Sep 11 04:56:04 AM UTC 24 | 2595717534 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.3734466299 | Sep 11 04:55:51 AM UTC 24 | Sep 11 04:56:04 AM UTC 24 | 172542088 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.3283824166 | Sep 11 04:55:48 AM UTC 24 | Sep 11 04:56:06 AM UTC 24 | 261271078 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.3891359584 | Sep 11 04:55:55 AM UTC 24 | Sep 11 04:56:08 AM UTC 24 | 752126780 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.725604620 | Sep 11 04:55:54 AM UTC 24 | Sep 11 04:56:09 AM UTC 24 | 261973029 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2424954631 | Sep 11 04:54:57 AM UTC 24 | Sep 11 04:56:09 AM UTC 24 | 2594013783 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.1746012054 | Sep 11 04:56:00 AM UTC 24 | Sep 11 04:56:11 AM UTC 24 | 255890441 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.501250501 | Sep 11 04:56:03 AM UTC 24 | Sep 11 04:56:12 AM UTC 24 | 517364612 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.420680379 | Sep 11 04:54:30 AM UTC 24 | Sep 11 04:56:16 AM UTC 24 | 4640765778 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.3527363191 | Sep 11 04:56:05 AM UTC 24 | Sep 11 04:56:16 AM UTC 24 | 139973530 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.2288639044 | Sep 11 04:56:10 AM UTC 24 | Sep 11 04:56:18 AM UTC 24 | 132616578 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.31752212 | Sep 11 04:55:47 AM UTC 24 | Sep 11 04:56:18 AM UTC 24 | 3120110020 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.3725271591 | Sep 11 04:56:10 AM UTC 24 | Sep 11 04:56:21 AM UTC 24 | 172951198 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.2381220229 | Sep 11 04:56:12 AM UTC 24 | Sep 11 04:56:21 AM UTC 24 | 499014553 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3099844053 | Sep 11 04:52:00 AM UTC 24 | Sep 11 04:56:23 AM UTC 24 | 4295003544 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.599299205 | Sep 11 04:56:07 AM UTC 24 | Sep 11 04:56:24 AM UTC 24 | 1040334438 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.2150209241 | Sep 11 04:56:19 AM UTC 24 | Sep 11 04:56:26 AM UTC 24 | 130186584 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.42490330 | Sep 11 04:56:16 AM UTC 24 | Sep 11 04:56:28 AM UTC 24 | 1454190043 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3136669613 | Sep 11 04:55:45 AM UTC 24 | Sep 11 04:56:29 AM UTC 24 | 942085454 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1882703844 | Sep 11 04:55:23 AM UTC 24 | Sep 11 04:56:30 AM UTC 24 | 6675473516 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.106454344 | Sep 11 04:56:21 AM UTC 24 | Sep 11 04:56:30 AM UTC 24 | 374913070 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.135966079 | Sep 11 04:55:11 AM UTC 24 | Sep 11 04:56:31 AM UTC 24 | 1185741364 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1932810668 | Sep 11 04:56:24 AM UTC 24 | Sep 11 04:56:33 AM UTC 24 | 414179629 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2035658268 | Sep 11 04:54:42 AM UTC 24 | Sep 11 04:56:33 AM UTC 24 | 8999854172 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3313793087 | Sep 11 04:53:10 AM UTC 24 | Sep 11 04:56:33 AM UTC 24 | 11658113147 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.924571726 | Sep 11 04:54:21 AM UTC 24 | Sep 11 04:56:33 AM UTC 24 | 5325907853 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.3122712847 | Sep 11 04:56:20 AM UTC 24 | Sep 11 04:56:36 AM UTC 24 | 1492701872 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.517103500 | Sep 11 04:56:28 AM UTC 24 | Sep 11 04:56:37 AM UTC 24 | 373022662 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.4239351827 | Sep 11 04:56:31 AM UTC 24 | Sep 11 04:56:39 AM UTC 24 | 481211810 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3680020684 | Sep 11 04:51:11 AM UTC 24 | Sep 11 04:56:41 AM UTC 24 | 19279987235 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3824145803 | Sep 11 04:56:34 AM UTC 24 | Sep 11 04:56:42 AM UTC 24 | 1272534200 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2235027603 | Sep 11 04:56:04 AM UTC 24 | Sep 11 04:56:43 AM UTC 24 | 1152204119 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.681991417 | Sep 11 04:56:36 AM UTC 24 | Sep 11 04:56:44 AM UTC 24 | 956042637 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.3184205225 | Sep 11 04:56:29 AM UTC 24 | Sep 11 04:56:46 AM UTC 24 | 497751036 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.2827216901 | Sep 11 04:56:37 AM UTC 24 | Sep 11 04:56:46 AM UTC 24 | 352167811 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1676728618 | Sep 11 04:56:38 AM UTC 24 | Sep 11 04:56:47 AM UTC 24 | 407384626 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2605441091 | Sep 11 04:56:22 AM UTC 24 | Sep 11 04:56:47 AM UTC 24 | 2025119891 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.758845242 | Sep 11 04:56:34 AM UTC 24 | Sep 11 04:56:49 AM UTC 24 | 362426979 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.401783042 | Sep 11 04:56:31 AM UTC 24 | Sep 11 04:56:49 AM UTC 24 | 642603407 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.114658951 | Sep 11 04:56:27 AM UTC 24 | Sep 11 04:56:52 AM UTC 24 | 421652446 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.1521371656 | Sep 11 04:56:44 AM UTC 24 | Sep 11 04:56:52 AM UTC 24 | 568322740 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.3783715743 | Sep 11 04:56:42 AM UTC 24 | Sep 11 04:56:53 AM UTC 24 | 169652963 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3183427564 | Sep 11 04:54:07 AM UTC 24 | Sep 11 04:56:53 AM UTC 24 | 15139370166 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.649746131 | Sep 11 04:55:08 AM UTC 24 | Sep 11 04:56:57 AM UTC 24 | 8579514140 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.3679333016 | Sep 11 04:56:46 AM UTC 24 | Sep 11 04:56:57 AM UTC 24 | 274139628 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3469011433 | Sep 11 04:56:50 AM UTC 24 | Sep 11 04:56:58 AM UTC 24 | 597993830 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3708840699 | Sep 11 04:55:30 AM UTC 24 | Sep 11 04:56:59 AM UTC 24 | 1814837341 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.4242986984 | Sep 11 04:55:20 AM UTC 24 | Sep 11 04:56:59 AM UTC 24 | 7839614694 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.58533866 | Sep 11 04:56:53 AM UTC 24 | Sep 11 04:57:01 AM UTC 24 | 385544332 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2747691054 | Sep 11 04:54:54 AM UTC 24 | Sep 11 04:57:01 AM UTC 24 | 3441576083 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1476973336 | Sep 11 04:56:47 AM UTC 24 | Sep 11 04:57:02 AM UTC 24 | 2264006716 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2199307952 | Sep 11 04:54:22 AM UTC 24 | Sep 11 04:57:03 AM UTC 24 | 9236275359 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2566224897 | Sep 11 04:56:58 AM UTC 24 | Sep 11 04:57:05 AM UTC 24 | 86384791 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1418024521 | Sep 11 04:56:45 AM UTC 24 | Sep 11 04:57:08 AM UTC 24 | 321026054 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.3554634219 | Sep 11 04:57:02 AM UTC 24 | Sep 11 04:57:09 AM UTC 24 | 547370589 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3904333181 | Sep 11 04:56:59 AM UTC 24 | Sep 11 04:57:09 AM UTC 24 | 3871258078 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.891546611 | Sep 11 04:55:48 AM UTC 24 | Sep 11 04:57:09 AM UTC 24 | 2102091717 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.1861729735 | Sep 11 04:56:54 AM UTC 24 | Sep 11 04:57:11 AM UTC 24 | 510814321 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_09_10/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.78743042 | Sep 11 04:54:12 AM UTC 24 | Sep 11 04:57:12 AM UTC 24 | 7234844910 ps |
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