Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.36 96.77 92.13 97.67 100.00 98.19 97.91 98.83


Total tests in report: 457
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
63.89 63.89 91.81 91.81 72.61 72.61 47.17 47.17 40.00 40.00 88.77 88.77 93.73 93.73 13.11 13.11 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1552204253
73.48 9.59 92.18 0.37 79.21 6.60 57.10 9.93 40.00 0.00 90.22 1.45 95.22 1.49 60.42 47.31 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1237796562
80.13 6.65 92.18 0.00 81.18 1.97 87.70 30.60 40.00 0.00 91.30 1.09 95.22 0.00 73.30 12.88 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.156729540
84.76 4.63 92.93 0.74 82.44 1.26 93.12 5.42 60.00 20.00 94.20 2.90 95.67 0.45 74.94 1.64 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.2851446490
89.07 4.31 92.93 0.00 84.69 2.25 93.65 0.53 86.67 26.67 94.57 0.36 95.82 0.15 75.18 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.364984778
90.43 1.36 96.40 3.47 86.94 2.25 94.38 0.72 86.67 0.00 96.38 1.81 96.12 0.30 76.11 0.94 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.2480364271
91.74 1.32 96.40 0.00 87.50 0.56 96.00 1.62 93.33 6.67 96.74 0.36 96.12 0.00 76.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1990776262
92.91 1.16 96.53 0.12 87.78 0.28 96.00 0.00 100.00 6.67 97.10 0.36 96.12 0.00 76.81 0.70 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.495818013
94.00 1.09 96.77 0.25 88.48 0.70 96.00 0.00 100.00 0.00 98.19 1.09 96.12 0.00 82.44 5.62 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2148127234
94.94 0.94 96.77 0.00 88.48 0.00 96.00 0.00 100.00 0.00 98.19 0.00 96.12 0.00 88.99 6.56 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3548323811
95.61 0.67 96.77 0.00 88.48 0.00 96.00 0.00 100.00 0.00 98.19 0.00 96.12 0.00 93.68 4.68 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3237305830
96.01 0.40 96.77 0.00 90.17 1.69 96.75 0.75 100.00 0.00 98.19 0.00 96.27 0.15 93.91 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.675837528
96.29 0.28 96.77 0.00 90.87 0.70 96.80 0.05 100.00 0.00 98.19 0.00 96.57 0.30 94.85 0.94 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.653949454
96.49 0.20 96.77 0.00 90.87 0.00 96.80 0.00 100.00 0.00 98.19 0.00 96.57 0.00 96.25 1.41 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.563358759
96.68 0.19 96.77 0.00 91.01 0.14 96.80 0.00 100.00 0.00 98.19 0.00 97.76 1.19 96.25 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1896054594
96.85 0.17 96.77 0.00 91.01 0.00 96.80 0.00 100.00 0.00 98.19 0.00 97.76 0.00 97.42 1.17 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.910893390
97.02 0.17 96.77 0.00 91.71 0.70 97.03 0.23 100.00 0.00 98.19 0.00 97.76 0.00 97.66 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.2283064199
97.09 0.08 96.77 0.00 91.99 0.28 97.28 0.25 100.00 0.00 98.19 0.00 97.76 0.00 97.66 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4032649413
97.16 0.06 96.77 0.00 91.99 0.00 97.47 0.20 100.00 0.00 98.19 0.00 97.76 0.00 97.89 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.116235278
97.19 0.03 96.77 0.00 91.99 0.00 97.47 0.00 100.00 0.00 98.19 0.00 97.76 0.00 98.13 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3639007483
97.22 0.03 96.77 0.00 91.99 0.00 97.47 0.00 100.00 0.00 98.19 0.00 97.76 0.00 98.36 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3599936884
97.26 0.03 96.77 0.00 91.99 0.00 97.47 0.00 100.00 0.00 98.19 0.00 97.76 0.00 98.59 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2742099648
97.29 0.03 96.77 0.00 91.99 0.00 97.47 0.00 100.00 0.00 98.19 0.00 97.76 0.00 98.83 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3149295412
97.31 0.02 96.77 0.00 91.99 0.00 97.47 0.00 100.00 0.00 98.19 0.00 97.91 0.15 98.83 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3211217725
97.33 0.02 96.77 0.00 92.13 0.14 97.47 0.00 100.00 0.00 98.19 0.00 97.91 0.00 98.83 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1010476937
97.35 0.02 96.77 0.00 92.13 0.00 97.60 0.12 100.00 0.00 98.19 0.00 97.91 0.00 98.83 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2535963861
97.36 0.01 96.77 0.00 92.13 0.00 97.67 0.07 100.00 0.00 98.19 0.00 97.91 0.00 98.83 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1167132626

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1947483725
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3891804572
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2117485868
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1479931207
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3017465147
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1540860223
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3022851675
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3591984963
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2756679740
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1243630720
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2923852511
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.707130397
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1138493304
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1092503079
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1766339621
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1338306580
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2335118175
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1741877744
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2673387529
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3338425869
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1760931626
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.732711524
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3534990531
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3705890141
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2726983118
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2867284281
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3779055761
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2005193641
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4243337384
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.344910467
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.815307623
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2489223938
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3140655913
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.881990128
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2716830375
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.930554524
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1247437524
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3989462337
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3436115503
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2361527046
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2827583595
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.708177889
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1090189201
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3764625213
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2955706768
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2031817389
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3820463122
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.678421063
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2649416502
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3521475098
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4147471024
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2559398766
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3668371474
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1069563180
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3631333391
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.186572341
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4007644013
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2530514273
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3496426467
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.531078089
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1657476494
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3583454292
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1598678965
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3826062229
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2827578175
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1749203601
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1389998385
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2675470405
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1605388980
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1338915053
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.707739616
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2779100047
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3793533700
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1767950315
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.834447952
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1531166041
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3867095293
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1232981042
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.765320998
/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2116972278
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/workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2363301239
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Total test records in report: 457
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.3478108836 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:27 AM UTC 24 172793070 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.1448262341 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:27 AM UTC 24 89416160 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.2455482773 Sep 24 06:44:21 AM UTC 24 Sep 24 06:44:28 AM UTC 24 587164117 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.3224791249 Sep 24 06:44:21 AM UTC 24 Sep 24 06:44:28 AM UTC 24 100984624 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.236012292 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:29 AM UTC 24 370906152 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.1131585880 Sep 24 06:44:21 AM UTC 24 Sep 24 06:44:29 AM UTC 24 130744117 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.116952471 Sep 24 06:44:21 AM UTC 24 Sep 24 06:44:29 AM UTC 24 564711191 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.1179288829 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:29 AM UTC 24 544958248 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.2283064199 Sep 24 06:44:21 AM UTC 24 Sep 24 06:44:29 AM UTC 24 552518818 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1552204253 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:30 AM UTC 24 145004770 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.2480364271 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:31 AM UTC 24 89733419 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.3745052208 Sep 24 06:44:25 AM UTC 24 Sep 24 06:44:32 AM UTC 24 396432401 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.1984230771 Sep 24 06:44:26 AM UTC 24 Sep 24 06:44:32 AM UTC 24 377736757 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.2851446490 Sep 24 06:44:21 AM UTC 24 Sep 24 06:44:32 AM UTC 24 754881009 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.2549928043 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:33 AM UTC 24 96443064 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.926060733 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:33 AM UTC 24 191648589 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.2535963861 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:34 AM UTC 24 832182676 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.2123043800 Sep 24 06:44:25 AM UTC 24 Sep 24 06:44:34 AM UTC 24 495488282 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1430063407 Sep 24 06:44:23 AM UTC 24 Sep 24 06:44:34 AM UTC 24 374596633 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.738451615 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:34 AM UTC 24 273571619 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.1811831773 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:36 AM UTC 24 93135716 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1990776262 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:36 AM UTC 24 533488702 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.94334725 Sep 24 06:44:23 AM UTC 24 Sep 24 06:44:37 AM UTC 24 368397188 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1167132626 Sep 24 06:44:21 AM UTC 24 Sep 24 06:44:37 AM UTC 24 207780640 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3680042599 Sep 24 06:44:25 AM UTC 24 Sep 24 06:44:37 AM UTC 24 348087815 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2001811019 Sep 24 06:44:31 AM UTC 24 Sep 24 06:44:37 AM UTC 24 416789955 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.2172292838 Sep 24 06:44:29 AM UTC 24 Sep 24 06:44:38 AM UTC 24 96316744 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.2858167930 Sep 24 06:44:28 AM UTC 24 Sep 24 06:44:39 AM UTC 24 87342104 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1497319034 Sep 24 06:44:31 AM UTC 24 Sep 24 06:44:39 AM UTC 24 517330426 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.257003636 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:39 AM UTC 24 2448450584 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.1269590529 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:39 AM UTC 24 541932285 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.174121082 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:39 AM UTC 24 180420403 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.3772628442 Sep 24 06:44:26 AM UTC 24 Sep 24 06:44:40 AM UTC 24 794218696 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3115526901 Sep 24 06:44:33 AM UTC 24 Sep 24 06:44:40 AM UTC 24 197154945 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3466161712 Sep 24 06:44:34 AM UTC 24 Sep 24 06:44:41 AM UTC 24 1125991059 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.549385026 Sep 24 06:44:29 AM UTC 24 Sep 24 06:44:42 AM UTC 24 524666036 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3058744386 Sep 24 06:44:27 AM UTC 24 Sep 24 06:44:43 AM UTC 24 1246862954 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.2835810113 Sep 24 06:44:30 AM UTC 24 Sep 24 06:44:44 AM UTC 24 701880808 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.1148517346 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:44 AM UTC 24 631582972 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.3240571297 Sep 24 06:44:22 AM UTC 24 Sep 24 06:44:44 AM UTC 24 252461265 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.940343448 Sep 24 06:44:35 AM UTC 24 Sep 24 06:44:45 AM UTC 24 98511433 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2808855024 Sep 24 06:44:35 AM UTC 24 Sep 24 06:44:45 AM UTC 24 407942692 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.675837528 Sep 24 06:44:23 AM UTC 24 Sep 24 06:44:45 AM UTC 24 920029579 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.1416222550 Sep 24 06:44:40 AM UTC 24 Sep 24 06:44:46 AM UTC 24 443057158 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.1007284388 Sep 24 06:44:42 AM UTC 24 Sep 24 06:44:49 AM UTC 24 131893481 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.734856034 Sep 24 06:44:40 AM UTC 24 Sep 24 06:44:49 AM UTC 24 764496751 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3548323811 Sep 24 06:44:39 AM UTC 24 Sep 24 06:44:49 AM UTC 24 3591793996 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3631037320 Sep 24 06:44:33 AM UTC 24 Sep 24 06:44:49 AM UTC 24 2271163798 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2920629058 Sep 24 06:44:38 AM UTC 24 Sep 24 06:44:50 AM UTC 24 525420937 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.1885526859 Sep 24 06:44:35 AM UTC 24 Sep 24 06:44:50 AM UTC 24 185034348 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.116235278 Sep 24 06:44:29 AM UTC 24 Sep 24 06:44:51 AM UTC 24 209352062 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.953233500 Sep 24 06:44:32 AM UTC 24 Sep 24 06:44:53 AM UTC 24 4593404258 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3274444280 Sep 24 06:44:46 AM UTC 24 Sep 24 06:44:54 AM UTC 24 86286372 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.737590837 Sep 24 06:44:44 AM UTC 24 Sep 24 06:44:54 AM UTC 24 145206680 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.247317458 Sep 24 06:44:50 AM UTC 24 Sep 24 06:44:56 AM UTC 24 568014909 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.4063043100 Sep 24 06:44:39 AM UTC 24 Sep 24 06:44:57 AM UTC 24 301085872 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1542792438 Sep 24 06:44:37 AM UTC 24 Sep 24 06:44:57 AM UTC 24 511039672 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.2962190638 Sep 24 06:44:40 AM UTC 24 Sep 24 06:44:58 AM UTC 24 214955334 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.455906802 Sep 24 06:44:47 AM UTC 24 Sep 24 06:44:58 AM UTC 24 547233471 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.3259557073 Sep 24 06:44:41 AM UTC 24 Sep 24 06:44:59 AM UTC 24 281713970 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1836190877 Sep 24 06:44:54 AM UTC 24 Sep 24 06:45:00 AM UTC 24 312587213 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.156729540 Sep 24 06:44:22 AM UTC 24 Sep 24 06:45:03 AM UTC 24 806728262 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.2376028840 Sep 24 06:44:49 AM UTC 24 Sep 24 06:45:03 AM UTC 24 837501160 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.4060791491 Sep 24 06:44:51 AM UTC 24 Sep 24 06:45:04 AM UTC 24 145449504 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3452590162 Sep 24 06:44:46 AM UTC 24 Sep 24 06:45:06 AM UTC 24 3799049498 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.3382726107 Sep 24 06:44:51 AM UTC 24 Sep 24 06:45:06 AM UTC 24 1135280595 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.904480634 Sep 24 06:44:43 AM UTC 24 Sep 24 06:45:06 AM UTC 24 800900829 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.2162388481 Sep 24 06:44:58 AM UTC 24 Sep 24 06:45:09 AM UTC 24 95173747 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.2431760723 Sep 24 06:45:00 AM UTC 24 Sep 24 06:45:09 AM UTC 24 126841069 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3652893837 Sep 24 06:44:55 AM UTC 24 Sep 24 06:45:09 AM UTC 24 169215920 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.563358759 Sep 24 06:45:01 AM UTC 24 Sep 24 06:45:13 AM UTC 24 269250649 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.57626689 Sep 24 06:44:50 AM UTC 24 Sep 24 06:45:14 AM UTC 24 1027388088 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.4248738379 Sep 24 06:44:46 AM UTC 24 Sep 24 06:45:14 AM UTC 24 2181338955 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.3619453221 Sep 24 06:45:06 AM UTC 24 Sep 24 06:45:15 AM UTC 24 930786248 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.1473391181 Sep 24 06:45:06 AM UTC 24 Sep 24 06:45:16 AM UTC 24 380300846 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.3005551469 Sep 24 06:45:04 AM UTC 24 Sep 24 06:45:16 AM UTC 24 175203541 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.547845371 Sep 24 06:45:10 AM UTC 24 Sep 24 06:45:18 AM UTC 24 92055825 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3273409389 Sep 24 06:44:59 AM UTC 24 Sep 24 06:45:19 AM UTC 24 997940872 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.2336188690 Sep 24 06:44:39 AM UTC 24 Sep 24 06:45:19 AM UTC 24 4042564149 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1339064453 Sep 24 06:45:00 AM UTC 24 Sep 24 06:45:22 AM UTC 24 3491947660 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.1007276134 Sep 24 06:45:15 AM UTC 24 Sep 24 06:45:24 AM UTC 24 1201553451 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.350820814 Sep 24 06:44:22 AM UTC 24 Sep 24 06:45:25 AM UTC 24 740817557 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3929856059 Sep 24 06:44:46 AM UTC 24 Sep 24 06:45:25 AM UTC 24 2701873980 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.3606993281 Sep 24 06:45:17 AM UTC 24 Sep 24 06:45:26 AM UTC 24 730789155 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.439244269 Sep 24 06:45:10 AM UTC 24 Sep 24 06:45:26 AM UTC 24 1033951270 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.2783075317 Sep 24 06:45:20 AM UTC 24 Sep 24 06:45:29 AM UTC 24 143159415 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3134360668 Sep 24 06:45:06 AM UTC 24 Sep 24 06:45:30 AM UTC 24 1310156382 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1237796562 Sep 24 06:44:28 AM UTC 24 Sep 24 06:45:30 AM UTC 24 1068307908 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.1094595638 Sep 24 06:45:23 AM UTC 24 Sep 24 06:45:31 AM UTC 24 347178334 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.495784435 Sep 24 06:45:15 AM UTC 24 Sep 24 06:45:31 AM UTC 24 289334957 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.2217287828 Sep 24 06:44:22 AM UTC 24 Sep 24 06:45:31 AM UTC 24 567039300 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4032649413 Sep 24 06:44:22 AM UTC 24 Sep 24 06:45:34 AM UTC 24 897535181 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.3379846955 Sep 24 06:45:25 AM UTC 24 Sep 24 06:45:36 AM UTC 24 100292244 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.2794384308 Sep 24 06:45:21 AM UTC 24 Sep 24 06:45:37 AM UTC 24 498915815 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.3645260751 Sep 24 06:45:19 AM UTC 24 Sep 24 06:45:38 AM UTC 24 290224302 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.2251644374 Sep 24 06:45:31 AM UTC 24 Sep 24 06:45:38 AM UTC 24 517688879 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2091067677 Sep 24 06:44:22 AM UTC 24 Sep 24 06:45:39 AM UTC 24 145005815 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3204238381 Sep 24 06:45:32 AM UTC 24 Sep 24 06:45:39 AM UTC 24 96481187 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.1371387892 Sep 24 06:45:26 AM UTC 24 Sep 24 06:45:39 AM UTC 24 672268155 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.1988969976 Sep 24 06:45:32 AM UTC 24 Sep 24 06:45:41 AM UTC 24 519236201 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.2680374793 Sep 24 06:44:22 AM UTC 24 Sep 24 06:45:42 AM UTC 24 412079712 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.364984778 Sep 24 06:44:22 AM UTC 24 Sep 24 06:45:43 AM UTC 24 6658275899 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.2316416892 Sep 24 06:45:13 AM UTC 24 Sep 24 06:45:43 AM UTC 24 1818636430 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.1078909666 Sep 24 06:45:24 AM UTC 24 Sep 24 06:45:44 AM UTC 24 225435690 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.768021096 Sep 24 06:45:37 AM UTC 24 Sep 24 06:45:45 AM UTC 24 271662638 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.1842409588 Sep 24 06:45:40 AM UTC 24 Sep 24 06:45:46 AM UTC 24 490306482 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.4058632932 Sep 24 06:45:35 AM UTC 24 Sep 24 06:45:46 AM UTC 24 600631926 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.2098924481 Sep 24 06:45:31 AM UTC 24 Sep 24 06:45:47 AM UTC 24 261075358 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.1084788733 Sep 24 06:45:40 AM UTC 24 Sep 24 06:45:49 AM UTC 24 98327903 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.531506689 Sep 24 06:45:32 AM UTC 24 Sep 24 06:45:49 AM UTC 24 261736971 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.4049051837 Sep 24 06:44:37 AM UTC 24 Sep 24 06:45:51 AM UTC 24 10666782195 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.2735863015 Sep 24 06:45:39 AM UTC 24 Sep 24 06:45:52 AM UTC 24 263907802 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.2638290583 Sep 24 06:45:44 AM UTC 24 Sep 24 06:45:53 AM UTC 24 516497149 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1825673507 Sep 24 06:44:21 AM UTC 24 Sep 24 06:45:54 AM UTC 24 8085238957 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.3267691888 Sep 24 06:45:46 AM UTC 24 Sep 24 06:45:55 AM UTC 24 277779863 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2094983745 Sep 24 06:44:40 AM UTC 24 Sep 24 06:45:57 AM UTC 24 1833848053 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1431719625 Sep 24 06:44:22 AM UTC 24 Sep 24 06:45:58 AM UTC 24 8203217203 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1801563759 Sep 24 06:45:42 AM UTC 24 Sep 24 06:45:59 AM UTC 24 2255447200 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.2043077942 Sep 24 06:45:50 AM UTC 24 Sep 24 06:45:59 AM UTC 24 519822411 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.1199044451 Sep 24 06:45:47 AM UTC 24 Sep 24 06:46:00 AM UTC 24 175614518 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.2432503379 Sep 24 06:45:40 AM UTC 24 Sep 24 06:46:00 AM UTC 24 432975884 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.3018131143 Sep 24 06:45:44 AM UTC 24 Sep 24 06:46:02 AM UTC 24 132975253 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.792570656 Sep 24 06:45:50 AM UTC 24 Sep 24 06:46:02 AM UTC 24 509261276 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.694640833 Sep 24 06:45:56 AM UTC 24 Sep 24 06:46:04 AM UTC 24 516186000 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3538825571 Sep 24 06:45:10 AM UTC 24 Sep 24 06:46:05 AM UTC 24 2481321225 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.2096307466 Sep 24 06:45:53 AM UTC 24 Sep 24 06:46:07 AM UTC 24 997385240 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.1693746313 Sep 24 06:46:01 AM UTC 24 Sep 24 06:46:09 AM UTC 24 128238790 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.929365403 Sep 24 06:45:58 AM UTC 24 Sep 24 06:46:09 AM UTC 24 1032195365 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3237305830 Sep 24 06:44:25 AM UTC 24 Sep 24 06:46:10 AM UTC 24 8849276395 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.336333770 Sep 24 06:45:50 AM UTC 24 Sep 24 06:46:11 AM UTC 24 223834216 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.2030085670 Sep 24 06:46:00 AM UTC 24 Sep 24 06:46:11 AM UTC 24 254938882 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.641604706 Sep 24 06:44:22 AM UTC 24 Sep 24 06:46:13 AM UTC 24 4274744636 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.4262688464 Sep 24 06:46:03 AM UTC 24 Sep 24 06:46:14 AM UTC 24 283382947 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.515468381 Sep 24 06:46:06 AM UTC 24 Sep 24 06:46:15 AM UTC 24 445784924 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.3201351273 Sep 24 06:45:57 AM UTC 24 Sep 24 06:46:18 AM UTC 24 416905800 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.4192651963 Sep 24 06:46:09 AM UTC 24 Sep 24 06:46:18 AM UTC 24 382398498 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.1565948335 Sep 24 06:46:03 AM UTC 24 Sep 24 06:46:19 AM UTC 24 930384647 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.532325369 Sep 24 06:46:12 AM UTC 24 Sep 24 06:46:20 AM UTC 24 921679035 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1510308010 Sep 24 06:45:04 AM UTC 24 Sep 24 06:46:22 AM UTC 24 3139665105 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.4275167479 Sep 24 06:46:08 AM UTC 24 Sep 24 06:46:23 AM UTC 24 855886821 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.288050536 Sep 24 06:46:14 AM UTC 24 Sep 24 06:46:24 AM UTC 24 349154022 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.3752812944 Sep 24 06:46:20 AM UTC 24 Sep 24 06:46:25 AM UTC 24 85780939 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.3866813920 Sep 24 06:46:01 AM UTC 24 Sep 24 06:46:27 AM UTC 24 977916526 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.692573678 Sep 24 06:46:11 AM UTC 24 Sep 24 06:46:27 AM UTC 24 255197898 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1240294155 Sep 24 06:44:51 AM UTC 24 Sep 24 06:46:31 AM UTC 24 4069799813 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.541797293 Sep 24 06:46:26 AM UTC 24 Sep 24 06:46:44 AM UTC 24 439595061 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.311111612 Sep 24 06:44:49 AM UTC 24 Sep 24 06:46:33 AM UTC 24 7990478475 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.269274324 Sep 24 06:46:19 AM UTC 24 Sep 24 06:46:33 AM UTC 24 498503020 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2683571549 Sep 24 06:46:13 AM UTC 24 Sep 24 06:46:33 AM UTC 24 289993849 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.1251769149 Sep 24 06:46:23 AM UTC 24 Sep 24 06:46:34 AM UTC 24 1497166826 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3404351594 Sep 24 06:44:30 AM UTC 24 Sep 24 06:46:35 AM UTC 24 8908128541 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3392448697 Sep 24 06:46:21 AM UTC 24 Sep 24 06:46:36 AM UTC 24 633745463 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.323158444 Sep 24 06:46:29 AM UTC 24 Sep 24 06:46:37 AM UTC 24 190928709 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.653949454 Sep 24 06:44:21 AM UTC 24 Sep 24 06:46:39 AM UTC 24 329934028 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.753388237 Sep 24 06:46:29 AM UTC 24 Sep 24 06:46:39 AM UTC 24 109071137 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2524821730 Sep 24 06:45:08 AM UTC 24 Sep 24 06:46:40 AM UTC 24 1262422052 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.13203906 Sep 24 06:46:31 AM UTC 24 Sep 24 06:46:40 AM UTC 24 177188511 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3630663288 Sep 24 06:46:35 AM UTC 24 Sep 24 06:46:42 AM UTC 24 695254897 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1737750316 Sep 24 06:44:39 AM UTC 24 Sep 24 06:46:43 AM UTC 24 1942015995 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.3068597989 Sep 24 06:46:37 AM UTC 24 Sep 24 06:46:48 AM UTC 24 191302102 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.656925776 Sep 24 06:46:42 AM UTC 24 Sep 24 06:46:50 AM UTC 24 261825211 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.2840936094 Sep 24 06:46:42 AM UTC 24 Sep 24 06:46:50 AM UTC 24 103634710 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.92875428 Sep 24 06:46:35 AM UTC 24 Sep 24 06:46:51 AM UTC 24 907025717 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.2550317764 Sep 24 06:46:33 AM UTC 24 Sep 24 06:46:51 AM UTC 24 250098288 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.230429504 Sep 24 06:46:39 AM UTC 24 Sep 24 06:46:52 AM UTC 24 752869600 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4048924262 Sep 24 06:44:26 AM UTC 24 Sep 24 06:46:56 AM UTC 24 2187270769 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4210601256 Sep 24 06:45:32 AM UTC 24 Sep 24 06:46:56 AM UTC 24 2648488673 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2637741191 Sep 24 06:46:49 AM UTC 24 Sep 24 06:46:57 AM UTC 24 299847020 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.1912036288 Sep 24 06:46:44 AM UTC 24 Sep 24 06:46:57 AM UTC 24 991893223 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.2401678817 Sep 24 06:46:52 AM UTC 24 Sep 24 06:47:00 AM UTC 24 162943488 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.3430171665 Sep 24 06:46:51 AM UTC 24 Sep 24 06:47:01 AM UTC 24 142251970 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3246247741 Sep 24 06:44:22 AM UTC 24 Sep 24 06:47:02 AM UTC 24 3404945338 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4173086536 Sep 24 06:45:26 AM UTC 24 Sep 24 06:47:03 AM UTC 24 6977019891 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.3781645156 Sep 24 06:46:42 AM UTC 24 Sep 24 06:47:03 AM UTC 24 311809365 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2419816455 Sep 24 06:44:33 AM UTC 24 Sep 24 06:47:06 AM UTC 24 15466566535 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.1875268028 Sep 24 06:46:57 AM UTC 24 Sep 24 06:47:06 AM UTC 24 137969653 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2363301239 Sep 24 06:44:25 AM UTC 24 Sep 24 06:47:07 AM UTC 24 2307855143 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.2044855512 Sep 24 06:46:51 AM UTC 24 Sep 24 06:47:08 AM UTC 24 207667241 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.4282878978 Sep 24 06:46:57 AM UTC 24 Sep 24 06:47:09 AM UTC 24 1329442894 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.3881429300 Sep 24 06:46:52 AM UTC 24 Sep 24 06:47:09 AM UTC 24 997792750 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.37986632 Sep 24 06:47:04 AM UTC 24 Sep 24 06:47:12 AM UTC 24 400403034 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1201363742 Sep 24 06:45:04 AM UTC 24 Sep 24 06:47:13 AM UTC 24 8281165476 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.1161855684 Sep 24 06:47:02 AM UTC 24 Sep 24 06:47:15 AM UTC 24 504287457 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1625863965 Sep 24 06:47:07 AM UTC 24 Sep 24 06:47:15 AM UTC 24 481353466 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.1044855030 Sep 24 06:47:09 AM UTC 24 Sep 24 06:47:16 AM UTC 24 98371708 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.3870638157 Sep 24 06:46:58 AM UTC 24 Sep 24 06:47:17 AM UTC 24 1660876949 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.495818013 Sep 24 06:44:47 AM UTC 24 Sep 24 06:47:22 AM UTC 24 2836859502 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2238584280 Sep 24 06:47:13 AM UTC 24 Sep 24 06:47:23 AM UTC 24 2083301928 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1624397238 Sep 24 06:47:07 AM UTC 24 Sep 24 06:47:24 AM UTC 24 696509876 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.540579529 Sep 24 06:47:16 AM UTC 24 Sep 24 06:47:25 AM UTC 24 260184903 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.1844193424 Sep 24 06:47:09 AM UTC 24 Sep 24 06:47:26 AM UTC 24 137808457 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.462260538 Sep 24 06:45:27 AM UTC 24 Sep 24 06:47:27 AM UTC 24 6095658256 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.4145050085 Sep 24 06:46:12 AM UTC 24 Sep 24 06:47:28 AM UTC 24 5119091407 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2553546987 Sep 24 06:47:17 AM UTC 24 Sep 24 06:47:29 AM UTC 24 566823552 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3503869011 Sep 24 06:44:35 AM UTC 24 Sep 24 06:47:30 AM UTC 24 9666515663 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2036426341 Sep 24 06:45:15 AM UTC 24 Sep 24 06:47:31 AM UTC 24 1318107893 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.2196097675 Sep 24 06:47:03 AM UTC 24 Sep 24 06:47:31 AM UTC 24 1114082322 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.4008636644 Sep 24 06:47:16 AM UTC 24 Sep 24 06:47:33 AM UTC 24 1881645142 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3175793511 Sep 24 06:45:17 AM UTC 24 Sep 24 06:47:33 AM UTC 24 3091150724 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.2953417773 Sep 24 06:47:25 AM UTC 24 Sep 24 06:47:34 AM UTC 24 127878427 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1125472797 Sep 24 06:46:46 AM UTC 24 Sep 24 06:47:35 AM UTC 24 13347874616 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3614880177 Sep 24 06:45:47 AM UTC 24 Sep 24 06:47:35 AM UTC 24 9964210609 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.1646126206 Sep 24 06:47:26 AM UTC 24 Sep 24 06:47:36 AM UTC 24 100270948 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2451340501 Sep 24 06:47:23 AM UTC 24 Sep 24 06:47:37 AM UTC 24 887727610 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.78647640 Sep 24 06:47:31 AM UTC 24 Sep 24 06:47:39 AM UTC 24 256933391 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.376492212 Sep 24 06:47:14 AM UTC 24 Sep 24 06:47:40 AM UTC 24 26440857622 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3012618797 Sep 24 06:47:32 AM UTC 24 Sep 24 06:47:41 AM UTC 24 372341079 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.817554908 Sep 24 06:47:36 AM UTC 24 Sep 24 06:47:45 AM UTC 24 128102844 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3080300722 Sep 24 06:46:00 AM UTC 24 Sep 24 06:47:46 AM UTC 24 2017511752 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3774513261 Sep 24 06:45:38 AM UTC 24 Sep 24 06:47:47 AM UTC 24 2519177839 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2884470208 Sep 24 06:47:29 AM UTC 24 Sep 24 06:47:47 AM UTC 24 264509083 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2273377714 Sep 24 06:47:37 AM UTC 24 Sep 24 06:47:48 AM UTC 24 593599916 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1801776495 Sep 24 06:46:26 AM UTC 24 Sep 24 06:47:48 AM UTC 24 3006284637 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3657587651 Sep 24 06:47:41 AM UTC 24 Sep 24 06:47:49 AM UTC 24 461252328 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.1265402334 Sep 24 06:47:34 AM UTC 24 Sep 24 06:47:49 AM UTC 24 193670277 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.1043896685 Sep 24 06:47:50 AM UTC 24 Sep 24 06:48:08 AM UTC 24 1004592624 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2096250308 Sep 24 06:47:32 AM UTC 24 Sep 24 06:47:50 AM UTC 24 659817495 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.531423571 Sep 24 06:47:36 AM UTC 24 Sep 24 06:47:51 AM UTC 24 1041630575 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.530800897 Sep 24 06:47:25 AM UTC 24 Sep 24 06:47:51 AM UTC 24 803776008 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3832637477 Sep 24 06:47:49 AM UTC 24 Sep 24 06:47:56 AM UTC 24 176675155 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1874977344 Sep 24 06:44:53 AM UTC 24 Sep 24 06:47:56 AM UTC 24 5393239061 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.4169053416 Sep 24 06:47:40 AM UTC 24 Sep 24 06:47:57 AM UTC 24 348565837 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.993551983 Sep 24 06:47:42 AM UTC 24 Sep 24 06:47:57 AM UTC 24 429348979 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2126453825 Sep 24 06:46:52 AM UTC 24 Sep 24 06:47:58 AM UTC 24 5104384335 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2594163546 Sep 24 06:45:23 AM UTC 24 Sep 24 06:47:59 AM UTC 24 8213765737 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1733376497 Sep 24 06:47:52 AM UTC 24 Sep 24 06:47:59 AM UTC 24 95877526 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.3153101363 Sep 24 06:47:49 AM UTC 24 Sep 24 06:47:59 AM UTC 24 124999230 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3018895902 Sep 24 06:45:20 AM UTC 24 Sep 24 06:48:00 AM UTC 24 9869935594 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.2162852246 Sep 24 06:47:46 AM UTC 24 Sep 24 06:48:00 AM UTC 24 1050475020 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1228315773 Sep 24 06:44:59 AM UTC 24 Sep 24 06:48:03 AM UTC 24 10105273059 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.567831595 Sep 24 06:44:40 AM UTC 24 Sep 24 06:48:03 AM UTC 24 9043344295 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.2150773583 Sep 24 06:47:57 AM UTC 24 Sep 24 06:48:06 AM UTC 24 147839122 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3686067134 Sep 24 06:47:48 AM UTC 24 Sep 24 06:48:07 AM UTC 24 1042081986 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1767663318 Sep 24 06:47:59 AM UTC 24 Sep 24 06:48:08 AM UTC 24 127417704 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.4000440154 Sep 24 06:47:59 AM UTC 24 Sep 24 06:48:09 AM UTC 24 499631462 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2990845857 Sep 24 06:44:34 AM UTC 24 Sep 24 06:48:09 AM UTC 24 9937151928 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2356212007 Sep 24 06:46:05 AM UTC 24 Sep 24 06:48:09 AM UTC 24 2918188305 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.899586346 Sep 24 06:47:49 AM UTC 24 Sep 24 06:48:09 AM UTC 24 3833584202 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3071228151 Sep 24 06:47:52 AM UTC 24 Sep 24 06:48:11 AM UTC 24 1062761124 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3699461157 Sep 24 06:44:22 AM UTC 24 Sep 24 06:48:12 AM UTC 24 16798625549 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1510889661 Sep 24 06:44:59 AM UTC 24 Sep 24 06:48:12 AM UTC 24 2435254726 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.4026632342 Sep 24 06:48:04 AM UTC 24 Sep 24 06:48:13 AM UTC 24 251989200 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2690835622 Sep 24 06:45:55 AM UTC 24 Sep 24 06:48:14 AM UTC 24 6577498973 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.2508941087 Sep 24 06:48:01 AM UTC 24 Sep 24 06:48:14 AM UTC 24 347838378 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1362554684 Sep 24 06:45:32 AM UTC 24 Sep 24 06:48:14 AM UTC 24 3470654400 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1120954539 Sep 24 06:44:21 AM UTC 24 Sep 24 06:48:14 AM UTC 24 4463791840 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3453920379 Sep 24 06:44:22 AM UTC 24 Sep 24 06:48:15 AM UTC 24 5813128098 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.2234013146 Sep 24 06:48:10 AM UTC 24 Sep 24 06:48:17 AM UTC 24 959819074 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.830911485 Sep 24 06:47:58 AM UTC 24 Sep 24 06:48:17 AM UTC 24 511958339 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_23/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.2145361492 Sep 24 06:48:10 AM UTC 24 Sep 24 06:48:18 AM UTC 24 100039432 ps
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