Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.41 96.77 92.13 97.67 100.00 98.19 98.06 99.06


Total tests in report: 458
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
63.21 63.21 91.81 91.81 72.61 72.61 46.58 46.58 40.00 40.00 88.77 88.77 93.58 93.58 9.13 9.13 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1442368713
74.24 11.03 92.31 0.50 81.18 8.57 61.05 14.47 46.67 6.67 91.67 2.90 95.07 1.49 51.76 42.62 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.4031496853
80.22 5.98 93.42 1.12 82.58 1.40 74.42 13.38 66.67 20.00 95.29 3.62 95.52 0.45 53.63 1.87 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3846181609
84.95 4.73 93.42 0.00 85.39 2.81 74.47 0.05 93.33 26.67 95.65 0.36 95.67 0.15 56.67 3.04 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1422352820
88.82 3.87 93.42 0.00 85.67 0.28 83.97 9.50 93.33 0.00 95.65 0.00 95.67 0.00 74.00 17.33 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.909172598
90.53 1.71 93.42 0.00 86.10 0.42 88.50 4.53 100.00 6.67 96.01 0.36 95.67 0.00 74.00 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.877281489
92.07 1.54 93.42 0.00 86.10 0.00 89.20 0.70 100.00 0.00 96.01 0.00 95.67 0.00 84.07 10.07 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.269482699
93.22 1.15 96.53 3.10 88.90 2.81 89.50 0.30 100.00 0.00 97.10 1.09 95.97 0.30 84.54 0.47 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.805671653
94.31 1.09 96.77 0.25 89.61 0.70 89.50 0.00 100.00 0.00 98.19 1.09 95.97 0.00 90.16 5.62 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.262330207
95.31 0.99 96.77 0.00 90.87 1.26 94.47 4.97 100.00 0.00 98.19 0.00 95.97 0.00 90.87 0.70 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.903162137
95.94 0.63 96.77 0.00 91.01 0.14 94.62 0.15 100.00 0.00 98.19 0.00 96.12 0.15 94.85 3.98 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.2049083461
96.30 0.36 96.77 0.00 91.29 0.28 96.47 1.85 100.00 0.00 98.19 0.00 96.27 0.15 95.08 0.23 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.2885699861
96.56 0.26 96.77 0.00 91.85 0.56 96.53 0.05 100.00 0.00 98.19 0.00 96.57 0.30 96.02 0.94 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2372615939
96.80 0.23 96.77 0.00 91.85 0.00 96.53 0.00 100.00 0.00 98.19 0.00 96.57 0.00 97.66 1.64 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2094192770
97.01 0.21 96.77 0.00 91.99 0.14 96.53 0.00 100.00 0.00 98.19 0.00 97.91 1.34 97.66 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.132237593
97.13 0.13 96.77 0.00 91.99 0.00 97.17 0.65 100.00 0.00 98.19 0.00 97.91 0.00 97.89 0.23 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3570631643
97.21 0.07 96.77 0.00 91.99 0.00 97.22 0.05 100.00 0.00 98.19 0.00 97.91 0.00 98.36 0.47 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1422913296
97.24 0.04 96.77 0.00 91.99 0.00 97.47 0.25 100.00 0.00 98.19 0.00 97.91 0.00 98.36 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.962195923
97.28 0.03 96.77 0.00 91.99 0.00 97.47 0.00 100.00 0.00 98.19 0.00 97.91 0.00 98.59 0.23 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4281865609
97.31 0.03 96.77 0.00 91.99 0.00 97.47 0.00 100.00 0.00 98.19 0.00 97.91 0.00 98.83 0.23 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3914464824
97.34 0.03 96.77 0.00 91.99 0.00 97.47 0.00 100.00 0.00 98.19 0.00 97.91 0.00 99.06 0.23 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.593672775
97.36 0.02 96.77 0.00 91.99 0.00 97.47 0.00 100.00 0.00 98.19 0.00 98.06 0.15 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.3008693647
97.39 0.02 96.77 0.00 92.13 0.14 97.47 0.00 100.00 0.00 98.19 0.00 98.06 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.24686535
97.40 0.02 96.77 0.00 92.13 0.00 97.60 0.12 100.00 0.00 98.19 0.00 98.06 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.884391368
97.41 0.01 96.77 0.00 92.13 0.00 97.67 0.07 100.00 0.00 98.19 0.00 98.06 0.00 99.06 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3963726059

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2765590838
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1479668343
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2084191425
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.866322698
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1616126499
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2288801997
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1487373076
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4124353014
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4059697543
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2485929975
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.457265656
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4140574124
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2586767481
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1167770641
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2676255876
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3903436237
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.29331454
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.308000525
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.583264207
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3547123745
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1677892846
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1424440347
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1530030627
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2194780111
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.131514207
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3316535514
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1928932288
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3657411737
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2410782799
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1835075085
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2645189451
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3972330782
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3501923478
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.905137657
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.130851965
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4207018229
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3156350540
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1033845188
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.574285812
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1939000240
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3691158880
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.51704211
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3532357395
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3440205735
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2222424079
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1554489792
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.773964756
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1322713204
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.533506463
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2319477335
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2338385618
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1121478785
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1481889444
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2185307473
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2856044382
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2571486004
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1621033329
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.142900896
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2132673386
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2816478768
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1168049942
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1032570613
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2960501256
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.850617042
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2728476208
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1952851612
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2142415372
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3235494245
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1556455694
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.451190759
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2378323560
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1840021562
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3532474668
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1946892985
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2280101962
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2087839126
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1613150239
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1935703281
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2936069736
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3354969920
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1839479821
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3332248133
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1000485969
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2905369342
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/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.2237236198
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1196341574
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/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.314795590
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/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.115349618
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1162976824
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3943489586
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/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.882210480
/workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.4039945607



Total test records in report: 458
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.1140251553 Oct 02 09:06:40 PM UTC 24 Oct 02 09:06:45 PM UTC 24 88976247 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.3513422254 Oct 02 09:06:40 PM UTC 24 Oct 02 09:06:46 PM UTC 24 366557882 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.2049083461 Oct 02 09:06:40 PM UTC 24 Oct 02 09:06:47 PM UTC 24 375621302 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.132383104 Oct 02 09:06:40 PM UTC 24 Oct 02 09:06:47 PM UTC 24 404392654 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.622018037 Oct 02 09:06:40 PM UTC 24 Oct 02 09:06:47 PM UTC 24 453830631 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.805671653 Oct 02 09:06:41 PM UTC 24 Oct 02 09:06:49 PM UTC 24 365380343 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3846181609 Oct 02 09:06:40 PM UTC 24 Oct 02 09:06:50 PM UTC 24 168661351 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2567770916 Oct 02 09:06:41 PM UTC 24 Oct 02 09:06:51 PM UTC 24 536801616 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1442368713 Oct 02 09:06:41 PM UTC 24 Oct 02 09:06:51 PM UTC 24 137952230 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.877281489 Oct 02 09:06:40 PM UTC 24 Oct 02 09:06:52 PM UTC 24 543976129 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.962195923 Oct 02 09:06:40 PM UTC 24 Oct 02 09:06:52 PM UTC 24 742659307 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3790627996 Oct 02 09:06:41 PM UTC 24 Oct 02 09:06:53 PM UTC 24 152147903 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.4073164581 Oct 02 09:06:48 PM UTC 24 Oct 02 09:06:54 PM UTC 24 90141604 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.2865916696 Oct 02 09:06:48 PM UTC 24 Oct 02 09:06:54 PM UTC 24 519152342 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1224272152 Oct 02 09:06:48 PM UTC 24 Oct 02 09:06:54 PM UTC 24 948885276 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.810545172 Oct 02 09:06:48 PM UTC 24 Oct 02 09:06:55 PM UTC 24 370292893 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1881462784 Oct 02 09:06:48 PM UTC 24 Oct 02 09:06:55 PM UTC 24 277970246 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3943489586 Oct 02 09:06:48 PM UTC 24 Oct 02 09:06:56 PM UTC 24 539640733 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.1338105573 Oct 02 09:06:48 PM UTC 24 Oct 02 09:06:56 PM UTC 24 410414259 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1227211456 Oct 02 09:06:48 PM UTC 24 Oct 02 09:06:56 PM UTC 24 269751410 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.60097163 Oct 02 09:06:50 PM UTC 24 Oct 02 09:06:57 PM UTC 24 171724744 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1422913296 Oct 02 09:06:48 PM UTC 24 Oct 02 09:06:57 PM UTC 24 398277851 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2859904260 Oct 02 09:06:51 PM UTC 24 Oct 02 09:06:57 PM UTC 24 102566492 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.4056566968 Oct 02 09:06:51 PM UTC 24 Oct 02 09:06:58 PM UTC 24 269647422 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.720113688 Oct 02 09:06:48 PM UTC 24 Oct 02 09:06:59 PM UTC 24 168696303 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.3945698824 Oct 02 09:06:53 PM UTC 24 Oct 02 09:07:00 PM UTC 24 127906417 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.884391368 Oct 02 09:06:48 PM UTC 24 Oct 02 09:07:00 PM UTC 24 501667065 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.4267879223 Oct 02 09:06:48 PM UTC 24 Oct 02 09:07:01 PM UTC 24 341818812 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.903162137 Oct 02 09:06:40 PM UTC 24 Oct 02 09:07:01 PM UTC 24 5012893284 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.2915857175 Oct 02 09:06:53 PM UTC 24 Oct 02 09:07:02 PM UTC 24 143376737 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1567918086 Oct 02 09:06:54 PM UTC 24 Oct 02 09:07:02 PM UTC 24 551533983 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2347840467 Oct 02 09:06:56 PM UTC 24 Oct 02 09:07:03 PM UTC 24 89187055 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.3304746394 Oct 02 09:06:48 PM UTC 24 Oct 02 09:07:03 PM UTC 24 212811773 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1740241878 Oct 02 09:06:56 PM UTC 24 Oct 02 09:07:03 PM UTC 24 95731154 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3185039700 Oct 02 09:06:59 PM UTC 24 Oct 02 09:07:06 PM UTC 24 258526065 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.4279207771 Oct 02 09:06:51 PM UTC 24 Oct 02 09:07:06 PM UTC 24 853014120 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1162976824 Oct 02 09:06:49 PM UTC 24 Oct 02 09:07:06 PM UTC 24 986224834 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2115397449 Oct 02 09:06:48 PM UTC 24 Oct 02 09:07:07 PM UTC 24 3686454603 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.3079982459 Oct 02 09:06:54 PM UTC 24 Oct 02 09:07:07 PM UTC 24 571545619 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3356411349 Oct 02 09:06:55 PM UTC 24 Oct 02 09:07:08 PM UTC 24 530123491 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.980941475 Oct 02 09:06:58 PM UTC 24 Oct 02 09:07:08 PM UTC 24 1311821774 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.2885699861 Oct 02 09:06:48 PM UTC 24 Oct 02 09:07:08 PM UTC 24 552583745 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3638803268 Oct 02 09:06:52 PM UTC 24 Oct 02 09:07:09 PM UTC 24 998643723 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.1868261765 Oct 02 09:07:00 PM UTC 24 Oct 02 09:07:09 PM UTC 24 276440979 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.216051383 Oct 02 09:07:01 PM UTC 24 Oct 02 09:07:09 PM UTC 24 911614017 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3453573955 Oct 02 09:06:56 PM UTC 24 Oct 02 09:07:11 PM UTC 24 360573527 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.3654254534 Oct 02 09:07:03 PM UTC 24 Oct 02 09:07:11 PM UTC 24 501267831 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.974498684 Oct 02 09:07:03 PM UTC 24 Oct 02 09:07:12 PM UTC 24 188499291 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2019134550 Oct 02 09:07:02 PM UTC 24 Oct 02 09:07:13 PM UTC 24 321375132 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.1008625562 Oct 02 09:07:08 PM UTC 24 Oct 02 09:07:15 PM UTC 24 300417216 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3332461597 Oct 02 09:06:58 PM UTC 24 Oct 02 09:07:15 PM UTC 24 991310100 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.31966367 Oct 02 09:07:08 PM UTC 24 Oct 02 09:07:16 PM UTC 24 358472266 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.3418632024 Oct 02 09:07:10 PM UTC 24 Oct 02 09:07:17 PM UTC 24 348312083 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.2422614096 Oct 02 09:07:03 PM UTC 24 Oct 02 09:07:19 PM UTC 24 1156808503 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.4290669958 Oct 02 09:07:11 PM UTC 24 Oct 02 09:07:20 PM UTC 24 144916748 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.882210480 Oct 02 09:07:01 PM UTC 24 Oct 02 09:07:21 PM UTC 24 436493716 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.2297529335 Oct 02 09:07:13 PM UTC 24 Oct 02 09:07:21 PM UTC 24 89185880 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.3929097848 Oct 02 09:07:07 PM UTC 24 Oct 02 09:07:21 PM UTC 24 177179607 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.4287113341 Oct 02 09:07:10 PM UTC 24 Oct 02 09:07:22 PM UTC 24 172768949 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.1887114883 Oct 02 09:07:10 PM UTC 24 Oct 02 09:07:22 PM UTC 24 145125356 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.909172598 Oct 02 09:06:40 PM UTC 24 Oct 02 09:07:24 PM UTC 24 2213434062 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3744874785 Oct 02 09:07:12 PM UTC 24 Oct 02 09:07:24 PM UTC 24 499415492 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.4204878762 Oct 02 09:07:15 PM UTC 24 Oct 02 09:07:25 PM UTC 24 2237879882 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1229744602 Oct 02 09:07:18 PM UTC 24 Oct 02 09:07:25 PM UTC 24 259079768 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.1420460729 Oct 02 09:07:15 PM UTC 24 Oct 02 09:07:25 PM UTC 24 309277319 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.2902712045 Oct 02 09:07:16 PM UTC 24 Oct 02 09:07:27 PM UTC 24 174267333 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3570631643 Oct 02 09:07:08 PM UTC 24 Oct 02 09:07:29 PM UTC 24 1030786687 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.2391026444 Oct 02 09:07:23 PM UTC 24 Oct 02 09:07:30 PM UTC 24 336078540 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.3265943155 Oct 02 09:07:22 PM UTC 24 Oct 02 09:07:31 PM UTC 24 614113426 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.920750259 Oct 02 09:07:28 PM UTC 24 Oct 02 09:07:35 PM UTC 24 640528925 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2093199995 Oct 02 09:07:22 PM UTC 24 Oct 02 09:07:36 PM UTC 24 1128380651 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.2021512240 Oct 02 09:07:25 PM UTC 24 Oct 02 09:07:36 PM UTC 24 744330277 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.3539050826 Oct 02 09:07:23 PM UTC 24 Oct 02 09:07:37 PM UTC 24 463709184 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3803230280 Oct 02 09:07:25 PM UTC 24 Oct 02 09:07:39 PM UTC 24 206350661 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1261824795 Oct 02 09:07:28 PM UTC 24 Oct 02 09:07:39 PM UTC 24 806701716 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.2540237865 Oct 02 09:07:30 PM UTC 24 Oct 02 09:07:40 PM UTC 24 276425766 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3452691106 Oct 02 09:07:23 PM UTC 24 Oct 02 09:07:42 PM UTC 24 1231715605 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.3078429293 Oct 02 09:07:38 PM UTC 24 Oct 02 09:07:46 PM UTC 24 170265458 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.174836616 Oct 02 09:07:32 PM UTC 24 Oct 02 09:07:47 PM UTC 24 347353288 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.4107075499 Oct 02 09:07:38 PM UTC 24 Oct 02 09:07:48 PM UTC 24 471613611 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.2389646358 Oct 02 09:07:45 PM UTC 24 Oct 02 09:07:52 PM UTC 24 168438587 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.1158667634 Oct 02 09:07:48 PM UTC 24 Oct 02 09:07:57 PM UTC 24 101281771 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.119438662 Oct 02 09:07:38 PM UTC 24 Oct 02 09:07:58 PM UTC 24 916281891 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.4065030200 Oct 02 09:07:40 PM UTC 24 Oct 02 09:07:58 PM UTC 24 252558912 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3120798862 Oct 02 09:07:48 PM UTC 24 Oct 02 09:07:59 PM UTC 24 738786245 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.4031496853 Oct 02 09:06:52 PM UTC 24 Oct 02 09:08:03 PM UTC 24 2750394757 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.185921886 Oct 02 09:07:58 PM UTC 24 Oct 02 09:08:04 PM UTC 24 175548379 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.687576928 Oct 02 09:07:51 PM UTC 24 Oct 02 09:08:05 PM UTC 24 261841245 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3963726059 Oct 02 09:07:05 PM UTC 24 Oct 02 09:08:07 PM UTC 24 986756051 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.199036231 Oct 02 09:07:59 PM UTC 24 Oct 02 09:08:09 PM UTC 24 439410189 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.2738731638 Oct 02 09:08:05 PM UTC 24 Oct 02 09:08:14 PM UTC 24 504124304 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3061383529 Oct 02 09:06:54 PM UTC 24 Oct 02 09:08:15 PM UTC 24 1699763259 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.1875142283 Oct 02 09:08:03 PM UTC 24 Oct 02 09:08:19 PM UTC 24 169864630 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.206499721 Oct 02 09:08:10 PM UTC 24 Oct 02 09:08:20 PM UTC 24 272014283 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.141502477 Oct 02 09:07:59 PM UTC 24 Oct 02 09:08:20 PM UTC 24 1760215090 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2372615939 Oct 02 09:06:40 PM UTC 24 Oct 02 09:08:27 PM UTC 24 240977218 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.2776154647 Oct 02 09:06:41 PM UTC 24 Oct 02 09:08:28 PM UTC 24 1130228459 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.4099540351 Oct 02 09:08:21 PM UTC 24 Oct 02 09:08:29 PM UTC 24 251146811 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.2721763410 Oct 02 09:06:48 PM UTC 24 Oct 02 09:08:30 PM UTC 24 212316776 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.2043136519 Oct 02 09:08:16 PM UTC 24 Oct 02 09:08:30 PM UTC 24 575384862 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4095915982 Oct 02 09:06:58 PM UTC 24 Oct 02 09:08:30 PM UTC 24 8557369098 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.4188629320 Oct 02 09:06:48 PM UTC 24 Oct 02 09:08:30 PM UTC 24 192546735 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1121470196 Oct 02 09:08:04 PM UTC 24 Oct 02 09:08:32 PM UTC 24 791892867 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.3198318990 Oct 02 09:08:09 PM UTC 24 Oct 02 09:08:32 PM UTC 24 1692979040 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.4107097592 Oct 02 09:06:58 PM UTC 24 Oct 02 09:08:33 PM UTC 24 7911787780 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.560198574 Oct 02 09:07:40 PM UTC 24 Oct 02 09:08:34 PM UTC 24 14507703225 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1422352820 Oct 02 09:06:40 PM UTC 24 Oct 02 09:08:36 PM UTC 24 7839773272 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.3077352033 Oct 02 09:08:31 PM UTC 24 Oct 02 09:08:36 PM UTC 24 126529970 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.3698055036 Oct 02 09:08:31 PM UTC 24 Oct 02 09:08:38 PM UTC 24 553696777 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.3188624430 Oct 02 09:08:28 PM UTC 24 Oct 02 09:08:39 PM UTC 24 139706583 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.269482699 Oct 02 09:06:49 PM UTC 24 Oct 02 09:08:40 PM UTC 24 1880936286 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.206812814 Oct 02 09:07:28 PM UTC 24 Oct 02 09:08:40 PM UTC 24 4374440315 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.987332900 Oct 02 09:08:31 PM UTC 24 Oct 02 09:08:41 PM UTC 24 141079700 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3601999041 Oct 02 09:08:34 PM UTC 24 Oct 02 09:08:43 PM UTC 24 210511532 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.1831565514 Oct 02 09:08:36 PM UTC 24 Oct 02 09:08:45 PM UTC 24 137826970 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.3998894911 Oct 02 09:08:29 PM UTC 24 Oct 02 09:08:45 PM UTC 24 1386643298 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3579092077 Oct 02 09:08:40 PM UTC 24 Oct 02 09:08:47 PM UTC 24 222221443 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.4176099919 Oct 02 09:08:33 PM UTC 24 Oct 02 09:08:49 PM UTC 24 349925982 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.1292088106 Oct 02 09:08:43 PM UTC 24 Oct 02 09:08:49 PM UTC 24 575993511 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.3517273866 Oct 02 09:08:38 PM UTC 24 Oct 02 09:08:51 PM UTC 24 729516648 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1269555617 Oct 02 09:07:12 PM UTC 24 Oct 02 09:08:51 PM UTC 24 8562513187 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.926105312 Oct 02 09:06:48 PM UTC 24 Oct 02 09:08:52 PM UTC 24 1199309789 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1026777170 Oct 02 09:07:11 PM UTC 24 Oct 02 09:08:52 PM UTC 24 2605444518 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.1948358191 Oct 02 09:08:21 PM UTC 24 Oct 02 09:08:52 PM UTC 24 4251923352 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4057298146 Oct 02 09:06:48 PM UTC 24 Oct 02 09:08:53 PM UTC 24 13139250992 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2192274472 Oct 02 09:07:23 PM UTC 24 Oct 02 09:08:54 PM UTC 24 7694886456 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.658210203 Oct 02 09:08:34 PM UTC 24 Oct 02 09:08:54 PM UTC 24 1992387423 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.481204254 Oct 02 09:08:46 PM UTC 24 Oct 02 09:08:54 PM UTC 24 130627369 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3313461574 Oct 02 09:07:01 PM UTC 24 Oct 02 09:08:56 PM UTC 24 2960858805 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.3054036288 Oct 02 09:08:41 PM UTC 24 Oct 02 09:08:57 PM UTC 24 411139681 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.3591761930 Oct 02 09:08:49 PM UTC 24 Oct 02 09:08:58 PM UTC 24 272041328 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.765339899 Oct 02 09:08:47 PM UTC 24 Oct 02 09:08:58 PM UTC 24 563154710 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.1192902875 Oct 02 09:08:46 PM UTC 24 Oct 02 09:08:59 PM UTC 24 1128279585 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.2069968893 Oct 02 09:08:53 PM UTC 24 Oct 02 09:09:01 PM UTC 24 599503198 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.4287382310 Oct 02 09:08:54 PM UTC 24 Oct 02 09:09:02 PM UTC 24 136129155 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.833611141 Oct 02 09:08:55 PM UTC 24 Oct 02 09:09:02 PM UTC 24 732438120 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.891123292 Oct 02 09:08:52 PM UTC 24 Oct 02 09:09:05 PM UTC 24 692139272 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.745946150 Oct 02 09:06:48 PM UTC 24 Oct 02 09:09:05 PM UTC 24 2724485553 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.99108058 Oct 02 09:08:59 PM UTC 24 Oct 02 09:09:06 PM UTC 24 1037980708 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.3181469140 Oct 02 09:08:55 PM UTC 24 Oct 02 09:09:07 PM UTC 24 173806703 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.4039945607 Oct 02 09:07:02 PM UTC 24 Oct 02 09:09:07 PM UTC 24 13520923800 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.957729533 Oct 02 09:08:58 PM UTC 24 Oct 02 09:09:07 PM UTC 24 203771611 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3091406114 Oct 02 09:06:41 PM UTC 24 Oct 02 09:09:08 PM UTC 24 9692424850 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.115349618 Oct 02 09:06:48 PM UTC 24 Oct 02 09:09:08 PM UTC 24 1703225903 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3651714138 Oct 02 09:06:48 PM UTC 24 Oct 02 09:09:08 PM UTC 24 2937890292 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.3008693647 Oct 02 09:09:03 PM UTC 24 Oct 02 09:09:10 PM UTC 24 663307397 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.211373387 Oct 02 09:08:54 PM UTC 24 Oct 02 09:09:10 PM UTC 24 1113584730 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.2603398947 Oct 02 09:08:59 PM UTC 24 Oct 02 09:09:13 PM UTC 24 699091386 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.1621822831 Oct 02 09:09:07 PM UTC 24 Oct 02 09:09:14 PM UTC 24 1383300350 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.2811692540 Oct 02 09:09:08 PM UTC 24 Oct 02 09:09:16 PM UTC 24 385980781 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.350536540 Oct 02 09:07:10 PM UTC 24 Oct 02 09:09:16 PM UTC 24 4448607561 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3360516951 Oct 02 09:07:40 PM UTC 24 Oct 02 09:09:16 PM UTC 24 1873973273 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.3162978788 Oct 02 09:09:09 PM UTC 24 Oct 02 09:09:18 PM UTC 24 128038299 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3543808696 Oct 02 09:09:01 PM UTC 24 Oct 02 09:09:18 PM UTC 24 293217599 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.2876842510 Oct 02 09:09:11 PM UTC 24 Oct 02 09:09:19 PM UTC 24 141110527 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3610682704 Oct 02 09:09:09 PM UTC 24 Oct 02 09:09:19 PM UTC 24 697023467 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.2766454155 Oct 02 09:09:06 PM UTC 24 Oct 02 09:09:20 PM UTC 24 1909665279 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.2539164367 Oct 02 09:08:57 PM UTC 24 Oct 02 09:09:20 PM UTC 24 324431298 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.926281911 Oct 02 09:06:48 PM UTC 24 Oct 02 09:09:20 PM UTC 24 2170351964 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.1377073426 Oct 02 09:09:08 PM UTC 24 Oct 02 09:09:21 PM UTC 24 2111431794 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1393891126 Oct 02 09:07:10 PM UTC 24 Oct 02 09:09:22 PM UTC 24 6463593857 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.773491326 Oct 02 09:06:52 PM UTC 24 Oct 02 09:09:22 PM UTC 24 4525242552 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.752018930 Oct 02 09:09:17 PM UTC 24 Oct 02 09:09:23 PM UTC 24 834756428 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2669712262 Oct 02 09:08:00 PM UTC 24 Oct 02 09:09:25 PM UTC 24 6859985200 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.2259800162 Oct 02 09:09:21 PM UTC 24 Oct 02 09:09:28 PM UTC 24 88734958 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.3713802675 Oct 02 09:09:19 PM UTC 24 Oct 02 09:09:28 PM UTC 24 204788864 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.2607901079 Oct 02 09:09:10 PM UTC 24 Oct 02 09:09:29 PM UTC 24 1127562850 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.574474927 Oct 02 09:06:40 PM UTC 24 Oct 02 09:09:30 PM UTC 24 3384538761 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.674117331 Oct 02 09:09:15 PM UTC 24 Oct 02 09:09:30 PM UTC 24 262087141 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.648187691 Oct 02 09:07:36 PM UTC 24 Oct 02 09:09:30 PM UTC 24 1598944674 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1189226774 Oct 02 09:06:55 PM UTC 24 Oct 02 09:09:31 PM UTC 24 7936670354 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.1455311122 Oct 02 09:09:25 PM UTC 24 Oct 02 09:09:32 PM UTC 24 130169818 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.928076222 Oct 02 09:07:25 PM UTC 24 Oct 02 09:09:33 PM UTC 24 2039979041 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.53959168 Oct 02 09:09:20 PM UTC 24 Oct 02 09:09:34 PM UTC 24 168440656 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3107228836 Oct 02 09:07:50 PM UTC 24 Oct 02 09:09:34 PM UTC 24 6635393064 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2503104576 Oct 02 09:09:21 PM UTC 24 Oct 02 09:09:34 PM UTC 24 1673426788 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3517707074 Oct 02 09:08:28 PM UTC 24 Oct 02 09:09:35 PM UTC 24 1944834826 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.3196748743 Oct 02 09:09:17 PM UTC 24 Oct 02 09:09:35 PM UTC 24 736273857 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.864054608 Oct 02 09:09:23 PM UTC 24 Oct 02 09:09:37 PM UTC 24 341571679 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.377766775 Oct 02 09:09:31 PM UTC 24 Oct 02 09:09:38 PM UTC 24 501022694 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3408817433 Oct 02 09:07:16 PM UTC 24 Oct 02 09:09:39 PM UTC 24 16623126470 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.3140482101 Oct 02 09:09:29 PM UTC 24 Oct 02 09:09:39 PM UTC 24 569619356 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.2444441962 Oct 02 09:09:35 PM UTC 24 Oct 02 09:09:40 PM UTC 24 251587821 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.3539494694 Oct 02 09:09:21 PM UTC 24 Oct 02 09:09:41 PM UTC 24 313963954 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2263008052 Oct 02 09:07:17 PM UTC 24 Oct 02 09:09:41 PM UTC 24 7333409084 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.2595408766 Oct 02 09:09:32 PM UTC 24 Oct 02 09:09:42 PM UTC 24 543622938 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.1042903048 Oct 02 09:09:30 PM UTC 24 Oct 02 09:09:42 PM UTC 24 174873944 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.740314876 Oct 02 09:07:07 PM UTC 24 Oct 02 09:09:43 PM UTC 24 3155744812 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.514933391 Oct 02 09:09:40 PM UTC 24 Oct 02 09:09:46 PM UTC 24 88332875 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.1192507831 Oct 02 09:09:36 PM UTC 24 Oct 02 09:09:46 PM UTC 24 2207366783 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2434596785 Oct 02 09:08:52 PM UTC 24 Oct 02 09:09:46 PM UTC 24 1262579589 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2993460620 Oct 02 09:09:34 PM UTC 24 Oct 02 09:09:48 PM UTC 24 696804449 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.3826864201 Oct 02 09:09:26 PM UTC 24 Oct 02 09:09:48 PM UTC 24 1126092518 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.2825493684 Oct 02 09:09:38 PM UTC 24 Oct 02 09:09:50 PM UTC 24 168712112 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.3096347049 Oct 02 09:09:41 PM UTC 24 Oct 02 09:09:50 PM UTC 24 101228925 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.3558560882 Oct 02 09:09:43 PM UTC 24 Oct 02 09:09:51 PM UTC 24 335816323 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2377659563 Oct 02 09:09:09 PM UTC 24 Oct 02 09:09:51 PM UTC 24 8073810680 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.2061811009 Oct 02 09:09:31 PM UTC 24 Oct 02 09:09:53 PM UTC 24 191016187 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.3251559908 Oct 02 09:09:43 PM UTC 24 Oct 02 09:09:53 PM UTC 24 280941804 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.764659857 Oct 02 09:09:42 PM UTC 24 Oct 02 09:09:54 PM UTC 24 1288939365 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.1293283573 Oct 02 09:09:49 PM UTC 24 Oct 02 09:09:55 PM UTC 24 625751290 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.3802597695 Oct 02 09:09:47 PM UTC 24 Oct 02 09:09:56 PM UTC 24 146353500 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1904555667 Oct 02 09:09:36 PM UTC 24 Oct 02 09:09:58 PM UTC 24 2114166466 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.3115400720 Oct 02 09:09:51 PM UTC 24 Oct 02 09:09:59 PM UTC 24 202915719 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.3395454540 Oct 02 09:09:54 PM UTC 24 Oct 02 09:10:01 PM UTC 24 498527289 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.1858366986 Oct 02 09:09:47 PM UTC 24 Oct 02 09:10:01 PM UTC 24 831439236 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1691710395 Oct 02 09:09:40 PM UTC 24 Oct 02 09:10:03 PM UTC 24 1591879468 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.1254966972 Oct 02 09:09:55 PM UTC 24 Oct 02 09:10:05 PM UTC 24 192693036 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3913101481 Oct 02 09:08:50 PM UTC 24 Oct 02 09:10:05 PM UTC 24 1284804619 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.2799446449 Oct 02 09:10:00 PM UTC 24 Oct 02 09:10:07 PM UTC 24 168377691 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.1332765261 Oct 02 09:09:51 PM UTC 24 Oct 02 09:10:08 PM UTC 24 250780203 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2330677891 Oct 02 09:09:31 PM UTC 24 Oct 02 09:10:09 PM UTC 24 1155219769 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.1293546338 Oct 02 09:09:57 PM UTC 24 Oct 02 09:10:11 PM UTC 24 521397120 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3746141916 Oct 02 09:10:02 PM UTC 24 Oct 02 09:10:12 PM UTC 24 607949089 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.476794212 Oct 02 09:09:55 PM UTC 24 Oct 02 09:10:15 PM UTC 24 830807628 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.4158747276 Oct 02 09:10:08 PM UTC 24 Oct 02 09:10:17 PM UTC 24 959826919 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.743706957 Oct 02 09:09:51 PM UTC 24 Oct 02 09:10:18 PM UTC 24 314853700 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.4216754747 Oct 02 09:10:02 PM UTC 24 Oct 02 09:10:18 PM UTC 24 1462153066 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.3887916411 Oct 02 09:10:09 PM UTC 24 Oct 02 09:10:20 PM UTC 24 373370947 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2307833336 Oct 02 09:08:15 PM UTC 24 Oct 02 09:10:20 PM UTC 24 13524579554 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.330766718 Oct 02 09:07:32 PM UTC 24 Oct 02 09:10:21 PM UTC 24 11437906379 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.4057755270 Oct 02 09:10:06 PM UTC 24 Oct 02 09:10:22 PM UTC 24 177792406 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.380146782 Oct 02 09:07:23 PM UTC 24 Oct 02 09:10:23 PM UTC 24 7792166775 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.656055024 Oct 02 09:08:32 PM UTC 24 Oct 02 09:10:24 PM UTC 24 1888406971 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.517456754 Oct 02 09:08:59 PM UTC 24 Oct 02 09:10:25 PM UTC 24 1675493666 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.276981624 Oct 02 09:10:18 PM UTC 24 Oct 02 09:10:25 PM UTC 24 85444464 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.132379895 Oct 02 09:09:34 PM UTC 24 Oct 02 09:10:28 PM UTC 24 1034768917 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2887184650 Oct 02 09:10:13 PM UTC 24 Oct 02 09:10:29 PM UTC 24 262856303 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.2123875188 Oct 02 09:10:19 PM UTC 24 Oct 02 09:10:29 PM UTC 24 136292669 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.1793295427 Oct 02 09:10:23 PM UTC 24 Oct 02 09:10:30 PM UTC 24 776937374 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.900456663 Oct 02 09:10:19 PM UTC 24 Oct 02 09:10:31 PM UTC 24 1738442394 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3023388125 Oct 02 09:10:24 PM UTC 24 Oct 02 09:10:32 PM UTC 24 464525850 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.1307061501 Oct 02 09:10:09 PM UTC 24 Oct 02 09:10:34 PM UTC 24 430970964 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.4027518952 Oct 02 09:09:53 PM UTC 24 Oct 02 09:10:35 PM UTC 24 2461997693 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.588358568 Oct 02 09:10:30 PM UTC 24 Oct 02 09:10:35 PM UTC 24 350326556 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1695861913 Oct 02 09:10:25 PM UTC 24 Oct 02 09:10:35 PM UTC 24 532098772 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.961186979 Oct 02 09:10:21 PM UTC 24 Oct 02 09:10:36 PM UTC 24 998490766 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.2240239757 Oct 02 09:10:31 PM UTC 24 Oct 02 09:10:39 PM UTC 24 542970032 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2958489381 Oct 02 09:09:32 PM UTC 24 Oct 02 09:10:39 PM UTC 24 1164767455 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.2031328026 Oct 02 09:10:26 PM UTC 24 Oct 02 09:10:39 PM UTC 24 447103508 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.877547573 Oct 02 09:09:39 PM UTC 24 Oct 02 09:10:40 PM UTC 24 2862313622 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2121935795 Oct 02 09:08:46 PM UTC 24 Oct 02 09:10:40 PM UTC 24 5731149663 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3139137989 Oct 02 09:08:33 PM UTC 24 Oct 02 09:10:41 PM UTC 24 3452136712 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.4138466632 Oct 02 09:07:53 PM UTC 24 Oct 02 09:10:41 PM UTC 24 8354923328 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.2318467491 Oct 02 09:10:36 PM UTC 24 Oct 02 09:10:43 PM UTC 24 561455427 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.3043046397 Oct 02 09:10:36 PM UTC 24 Oct 02 09:10:44 PM UTC 24 496416552 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.173618449 Oct 02 09:10:40 PM UTC 24 Oct 02 09:10:46 PM UTC 24 439012264 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.3315812859 Oct 02 09:10:33 PM UTC 24 Oct 02 09:10:46 PM UTC 24 667442278 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1743571825 Oct 02 09:10:31 PM UTC 24 Oct 02 09:10:47 PM UTC 24 646843905 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_02/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2513202687 Oct 02 09:10:41 PM UTC 24 Oct 02 09:10:47 PM UTC 24 187783193 ps
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