| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.87 | 99.36 | 92.56 | 97.67 | 100.00 | 98.55 | 97.91 | 99.06 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 62.80 | 62.80 | 94.78 | 94.78 | 68.96 | 68.96 | 41.33 | 41.33 | 40.00 | 40.00 | 88.77 | 88.77 | 93.58 | 93.58 | 12.18 | 12.18 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.4099701205 |
| 77.65 | 14.85 | 95.16 | 0.38 | 77.39 | 8.43 | 60.10 | 18.77 | 40.00 | 0.00 | 91.30 | 2.54 | 95.07 | 1.49 | 84.54 | 72.37 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4227060045 |
| 84.64 | 6.99 | 95.16 | 0.00 | 79.49 | 2.11 | 72.58 | 12.47 | 73.33 | 33.33 | 91.67 | 0.36 | 95.22 | 0.15 | 85.01 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1459029928 |
| 89.51 | 4.88 | 98.73 | 3.57 | 84.97 | 5.48 | 79.50 | 6.92 | 86.67 | 13.33 | 94.57 | 2.90 | 95.52 | 0.30 | 86.65 | 1.64 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.1491773562 |
| 92.22 | 2.71 | 98.98 | 0.25 | 86.24 | 1.26 | 87.53 | 8.03 | 93.33 | 6.67 | 96.38 | 1.81 | 95.97 | 0.45 | 87.12 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3369190667 |
| 94.07 | 1.85 | 99.11 | 0.13 | 86.38 | 0.14 | 92.67 | 5.15 | 100.00 | 6.67 | 96.74 | 0.36 | 95.97 | 0.00 | 87.59 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.1769031875 |
| 95.26 | 1.20 | 99.36 | 0.25 | 87.08 | 0.70 | 92.67 | 0.00 | 100.00 | 0.00 | 97.83 | 1.09 | 95.97 | 0.00 | 93.91 | 6.32 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3239682439 |
| 96.09 | 0.83 | 99.36 | 0.00 | 89.47 | 2.39 | 95.03 | 2.35 | 100.00 | 0.00 | 97.83 | 0.00 | 96.12 | 0.15 | 94.85 | 0.94 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.3202061946 |
| 96.38 | 0.29 | 99.36 | 0.00 | 90.45 | 0.98 | 96.08 | 1.05 | 100.00 | 0.00 | 97.83 | 0.00 | 96.12 | 0.00 | 94.85 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2430889479 |
| 96.65 | 0.26 | 99.36 | 0.00 | 91.01 | 0.56 | 96.12 | 0.05 | 100.00 | 0.00 | 97.83 | 0.00 | 96.42 | 0.30 | 95.78 | 0.94 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.1392740432 |
| 96.85 | 0.21 | 99.36 | 0.00 | 91.01 | 0.00 | 96.72 | 0.60 | 100.00 | 0.00 | 97.83 | 0.00 | 96.57 | 0.15 | 96.49 | 0.70 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.1242970959 |
| 97.02 | 0.16 | 99.36 | 0.00 | 91.01 | 0.00 | 96.72 | 0.00 | 100.00 | 0.00 | 97.83 | 0.00 | 97.46 | 0.90 | 96.72 | 0.23 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3460684936 |
| 97.17 | 0.16 | 99.36 | 0.00 | 91.15 | 0.14 | 97.33 | 0.60 | 100.00 | 0.00 | 98.19 | 0.36 | 97.46 | 0.00 | 96.72 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3004655175 |
| 97.29 | 0.11 | 99.36 | 0.00 | 91.85 | 0.70 | 97.42 | 0.10 | 100.00 | 0.00 | 98.19 | 0.00 | 97.46 | 0.00 | 96.72 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1266658541 |
| 97.40 | 0.11 | 99.36 | 0.00 | 92.28 | 0.42 | 97.42 | 0.00 | 100.00 | 0.00 | 98.55 | 0.36 | 97.46 | 0.00 | 96.72 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.834979746 |
| 97.50 | 0.10 | 99.36 | 0.00 | 92.28 | 0.00 | 97.42 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.46 | 0.00 | 97.42 | 0.70 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2405895101 |
| 97.57 | 0.07 | 99.36 | 0.00 | 92.28 | 0.00 | 97.47 | 0.05 | 100.00 | 0.00 | 98.55 | 0.00 | 97.46 | 0.00 | 97.89 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1006890355 |
| 97.64 | 0.06 | 99.36 | 0.00 | 92.42 | 0.14 | 97.47 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.76 | 0.30 | 97.89 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2928257076 |
| 97.69 | 0.05 | 99.36 | 0.00 | 92.42 | 0.00 | 97.47 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.15 | 98.13 | 0.23 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3500637084 |
| 97.73 | 0.04 | 99.36 | 0.00 | 92.42 | 0.00 | 97.53 | 0.05 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 98.36 | 0.23 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2218239916 |
| 97.77 | 0.03 | 99.36 | 0.00 | 92.56 | 0.14 | 97.62 | 0.10 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 98.36 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3830407698 |
| 97.80 | 0.03 | 99.36 | 0.00 | 92.56 | 0.00 | 97.62 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 98.59 | 0.23 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2787953209 |
| 97.83 | 0.03 | 99.36 | 0.00 | 92.56 | 0.00 | 97.62 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 98.83 | 0.23 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4240551840 |
| 97.87 | 0.03 | 99.36 | 0.00 | 92.56 | 0.00 | 97.62 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.23 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1540606547 |
| 97.87 | 0.01 | 99.36 | 0.00 | 92.56 | 0.00 | 97.67 | 0.05 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.2619994818 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2720608944 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1755058309 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2939794208 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1324409495 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.997281297 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1536613574 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3499006538 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3014097257 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3908502176 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3458553843 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.497670180 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1022027634 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1613008644 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4288109667 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2702421135 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1339756026 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1653297191 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.47298206 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.17208932 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2869757119 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2734948753 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3700906161 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4001606083 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3151710237 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1877977614 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3490339980 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2225036555 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2759112638 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2543981899 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2196892630 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4076842540 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2287973076 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.194103450 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3275124975 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1972958460 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3264612726 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1176821743 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.936807692 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3100422338 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1620197050 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3918726939 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.26513960 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2409986177 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2146254349 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1975023628 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1610127413 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.341642413 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3875085890 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2523509320 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3236655019 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2239356288 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.925283241 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3205880958 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3957893429 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2323074481 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3066341819 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3309128640 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.158061916 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3792356858 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3609249859 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.103673877 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1453251395 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1818252663 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3326952348 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2781173341 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1011148479 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1438052249 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2624843350 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.103844755 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3376126463 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1088441016 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.839944904 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.289204534 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3127778481 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3067733743 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.968212553 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1939893764 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.158351431 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2158344925 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1649025341 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1741120809 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2884288091 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3697607705 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.984062295 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1570405981 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.474998548 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2854206023 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2028833173 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3884446170 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.310590854 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.345654280 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3191142507 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.769711825 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1638132076 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.17454396 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.788264377 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1575288330 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3889617346 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.482984255 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2827477817 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2281480514 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1478023273 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2434045282 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2224636498 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3079000980 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3399221163 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1791264639 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2812144914 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.657524743 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1076225385 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1237107291 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1678347069 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2571499976 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.557974776 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3557440597 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1269747169 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2951235363 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2863711288 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.133210737 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2983300414 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3096879554 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1836304978 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3957697519 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1619961440 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2447304959 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3781715785 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3206007638 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.515447909 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.163082719 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2874484447 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1966128556 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.801254856 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4193462081 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1738011236 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3128756832 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2464558779 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.970561293 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.4068433525 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2468787830 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.4070662083 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.4185665996 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.3459100100 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.3308623191 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2307770539 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.300088272 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1023700458 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.1303467361 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.4123943879 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.4258807866 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.4089943276 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.598790497 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2460287608 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.137393115 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1297870875 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.1427097557 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3540439245 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.357643371 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2925330047 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1262816892 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.2975905674 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3619605964 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2403388606 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3800091348 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.1583350569 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.1080678087 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1138712527 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1683351101 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1163465418 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.1834866420 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.3150125821 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.461339533 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.874535808 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.3144688001 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.544796065 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.1915441956 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.455495569 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2166981689 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1626872774 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.387329238 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3308788546 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3258770415 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.2947115740 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.355294987 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.325376379 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.3997102159 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2771994484 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1085136811 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.977154752 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1226137354 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2739543427 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1760416728 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2240505968 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1204312759 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.1103723919 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.2960911486 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.568034743 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.2000678598 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3145744391 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2024205416 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.700678159 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3837741970 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3465494679 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.3653910909 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3237773400 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.3557704537 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.1905485220 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.4190389128 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3803442340 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.2122871084 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2036864684 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.730572723 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2753444430 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.3193597642 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.426150138 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.4084492960 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1130565211 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.911638590 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1563902319 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.3926991611 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.1103568290 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.2212363884 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2289642008 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3069462963 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.872065684 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.1347597680 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.1585137629 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2502946802 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2443892313 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.2127079400 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.556821669 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.140546690 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.541609602 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.1262945030 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2810413991 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.3385747731 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.916198887 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.1634395729 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.2337215255 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.3085497059 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1569669406 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3131830040 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3947254930 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3994146799 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.2016636334 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.2395350699 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1519939335 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.2629740011 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3727573657 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.4121052207 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1236131113 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.3336456291 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3144936823 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.2626084223 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3102816906 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.4151998670 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.490222208 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.554762408 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.106278633 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.145030869 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2527749412 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.3166146952 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1786155489 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.1270278161 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1684300632 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.4261169665 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3909743978 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.2676032884 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.1540538812 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2645843843 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1981077195 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1394416489 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2230367312 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.4049447394 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.3542262636 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.3706313725 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.3348084056 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.2113062520 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.958577957 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.2090444001 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.429320209 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.3316686447 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.3847662122 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.1442561425 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3872129519 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.1759962205 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3594423286 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.695965844 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.1335621072 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.420390187 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.4209380394 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.199305281 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2456850416 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.2363785895 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2769419126 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2372341833 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2549608389 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.1909295054 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2237507637 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.4243223905 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.1824356015 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.972797515 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3843047193 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.4069808940 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.69210998 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.1374068726 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.849792568 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.4175370344 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.2050407622 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.553399829 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.1645628852 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.1149273838 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.3272352847 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.326687526 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.616560908 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.640270916 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.2350291597 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.3357469588 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1431405987 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2740680649 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.90850137 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2174861170 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.1350595656 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.3118710698 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.458966282 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2349850331 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1375520197 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4224662249 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.1471633918 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.4081162451 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.3369433628 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.471965551 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.3638273182 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1389442534 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2182821996 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.505613610 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.4117656937 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3857889413 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.1452879475 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.2749141689 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.907989110 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1904535331 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.1656737565 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2603346564 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.3505259475 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4174603621 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2258005919 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.1772241024 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2323351791 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3015092793 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.821857918 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3841960543 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2766701004 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1179759110 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.4008077778 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3779770075 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3629552076 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.126229507 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.698138689 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.1816507148 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.3660774275 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.702484162 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1371061537 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3305799888 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.813829250 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1966560687 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.195131534 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1295549635 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1450526873 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2756746266 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.1079500583 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3274622140 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3903659906 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.1949837862 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.848930504 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.480581067 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.1642669880 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.3493235743 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3266756347 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.2092175300 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2549909799 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.1646235080 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.3909058456 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.667249593 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3165396339 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1236582487 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2024797485 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.1914383546 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.727976667 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.4007984188 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.442337649 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.1576418875 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1356964168 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.520823339 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.983376405 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.693359220 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.249329067 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.192601138 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2351839744 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.1189520608 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.1124768594 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.1060331169 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.512135443 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.878413046 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3206248582 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1693949564 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1079648850 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3739029733 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.624613955 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3342360253 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.3166210374 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1969117760 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3576365111 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.3449221139 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3570254287 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3428011435 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3998065376 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.2879793534 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.257662453 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2534729416 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.1607974724 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1248089502 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.1844156771 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.4029083531 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2842661523 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1312468506 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1099070183 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2876471391 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.3240815054 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2600878106 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.1768810783 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.1656823856 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.689528533 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.4068433525 | Oct 09 10:50:34 PM UTC 24 | Oct 09 10:50:40 PM UTC 24 | 299284898 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.3459100100 | Oct 09 10:50:34 PM UTC 24 | Oct 09 10:50:42 PM UTC 24 | 336727073 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.4185665996 | Oct 09 10:50:34 PM UTC 24 | Oct 09 10:50:43 PM UTC 24 | 179449921 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.4258807866 | Oct 09 10:50:36 PM UTC 24 | Oct 09 10:50:44 PM UTC 24 | 429872540 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1006890355 | Oct 09 10:50:37 PM UTC 24 | Oct 09 10:50:45 PM UTC 24 | 1051695247 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.3308623191 | Oct 09 10:50:34 PM UTC 24 | Oct 09 10:50:45 PM UTC 24 | 520381349 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.300088272 | Oct 09 10:50:37 PM UTC 24 | Oct 09 10:50:45 PM UTC 24 | 128225763 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.2122871084 | Oct 09 10:50:39 PM UTC 24 | Oct 09 10:50:46 PM UTC 24 | 299949909 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.4099701205 | Oct 09 10:50:37 PM UTC 24 | Oct 09 10:50:46 PM UTC 24 | 177551157 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.4070662083 | Oct 09 10:50:34 PM UTC 24 | Oct 09 10:50:47 PM UTC 24 | 213961637 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2430889479 | Oct 09 10:50:36 PM UTC 24 | Oct 09 10:50:48 PM UTC 24 | 819010311 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.3348084056 | Oct 09 10:50:41 PM UTC 24 | Oct 09 10:50:49 PM UTC 24 | 137125794 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.3004655175 | Oct 09 10:50:36 PM UTC 24 | Oct 09 10:50:50 PM UTC 24 | 372736536 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.1303467361 | Oct 09 10:50:36 PM UTC 24 | Oct 09 10:50:50 PM UTC 24 | 589073138 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1394416489 | Oct 09 10:50:44 PM UTC 24 | Oct 09 10:50:51 PM UTC 24 | 206916561 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.3542262636 | Oct 09 10:50:41 PM UTC 24 | Oct 09 10:50:52 PM UTC 24 | 582410742 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3369190667 | Oct 09 10:50:39 PM UTC 24 | Oct 09 10:50:54 PM UTC 24 | 296834061 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.1491773562 | Oct 09 10:50:48 PM UTC 24 | Oct 09 10:50:54 PM UTC 24 | 152376589 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1904535331 | Oct 09 10:50:46 PM UTC 24 | Oct 09 10:50:55 PM UTC 24 | 184732658 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.2960911486 | Oct 09 10:51:45 PM UTC 24 | Oct 09 10:51:54 PM UTC 24 | 146640516 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.2113062520 | Oct 09 10:50:41 PM UTC 24 | Oct 09 10:50:55 PM UTC 24 | 207142829 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.2619994818 | Oct 09 10:50:37 PM UTC 24 | Oct 09 10:50:55 PM UTC 24 | 315244353 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.2749141689 | Oct 09 10:50:46 PM UTC 24 | Oct 09 10:50:55 PM UTC 24 | 1509628205 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1079648850 | Oct 09 10:50:48 PM UTC 24 | Oct 09 10:50:56 PM UTC 24 | 346495267 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.1452879475 | Oct 09 10:50:46 PM UTC 24 | Oct 09 10:50:57 PM UTC 24 | 358906036 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.4049447394 | Oct 09 10:50:41 PM UTC 24 | Oct 09 10:50:57 PM UTC 24 | 299417241 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.3144688001 | Oct 09 10:51:31 PM UTC 24 | Oct 09 10:51:41 PM UTC 24 | 164395487 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3739029733 | Oct 09 10:50:48 PM UTC 24 | Oct 09 10:50:57 PM UTC 24 | 173823884 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.3166210374 | Oct 09 10:50:51 PM UTC 24 | Oct 09 10:50:59 PM UTC 24 | 1540550155 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.878413046 | Oct 09 10:50:51 PM UTC 24 | Oct 09 10:50:59 PM UTC 24 | 315867180 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.2879793534 | Oct 09 10:50:53 PM UTC 24 | Oct 09 10:51:01 PM UTC 24 | 295324117 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.624613955 | Oct 09 10:50:53 PM UTC 24 | Oct 09 10:51:01 PM UTC 24 | 315652642 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1969117760 | Oct 09 10:50:51 PM UTC 24 | Oct 09 10:51:02 PM UTC 24 | 196319859 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3998065376 | Oct 09 10:50:55 PM UTC 24 | Oct 09 10:51:04 PM UTC 24 | 312977925 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.3449221139 | Oct 09 10:50:56 PM UTC 24 | Oct 09 10:51:04 PM UTC 24 | 169996110 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.257662453 | Oct 09 10:50:55 PM UTC 24 | Oct 09 10:51:05 PM UTC 24 | 144014645 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2842661523 | Oct 09 10:50:58 PM UTC 24 | Oct 09 10:51:06 PM UTC 24 | 403973632 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.4029083531 | Oct 09 10:50:58 PM UTC 24 | Oct 09 10:51:06 PM UTC 24 | 137158775 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1693949564 | Oct 09 10:50:51 PM UTC 24 | Oct 09 10:51:06 PM UTC 24 | 1028768681 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.3202061946 | Oct 09 10:50:51 PM UTC 24 | Oct 09 10:51:08 PM UTC 24 | 343783273 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.1656737565 | Oct 09 10:50:46 PM UTC 24 | Oct 09 10:51:08 PM UTC 24 | 347444466 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3428011435 | Oct 09 10:50:56 PM UTC 24 | Oct 09 10:51:09 PM UTC 24 | 1898049912 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3342360253 | Oct 09 10:50:53 PM UTC 24 | Oct 09 10:51:09 PM UTC 24 | 1314876645 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.2600878106 | Oct 09 10:51:03 PM UTC 24 | Oct 09 10:51:10 PM UTC 24 | 982689548 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.1607974724 | Oct 09 10:51:02 PM UTC 24 | Oct 09 10:51:10 PM UTC 24 | 213087755 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2218239916 | Oct 09 10:50:48 PM UTC 24 | Oct 09 10:51:14 PM UTC 24 | 1100550463 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.1242970959 | Oct 09 10:50:58 PM UTC 24 | Oct 09 10:51:15 PM UTC 24 | 659155853 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.1844156771 | Oct 09 10:51:00 PM UTC 24 | Oct 09 10:51:17 PM UTC 24 | 926752574 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1099070183 | Oct 09 10:51:07 PM UTC 24 | Oct 09 10:51:17 PM UTC 24 | 172001438 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.1768810783 | Oct 09 10:51:02 PM UTC 24 | Oct 09 10:51:17 PM UTC 24 | 2107233927 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.1297870875 | Oct 09 10:51:08 PM UTC 24 | Oct 09 10:51:18 PM UTC 24 | 572298470 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.3240815054 | Oct 09 10:51:04 PM UTC 24 | Oct 09 10:51:18 PM UTC 24 | 537653901 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.598790497 | Oct 09 10:51:10 PM UTC 24 | Oct 09 10:51:18 PM UTC 24 | 293064349 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.2975905674 | Oct 09 10:51:11 PM UTC 24 | Oct 09 10:51:19 PM UTC 24 | 431450172 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.137393115 | Oct 09 10:51:09 PM UTC 24 | Oct 09 10:51:20 PM UTC 24 | 372601139 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.357643371 | Oct 09 10:51:16 PM UTC 24 | Oct 09 10:51:24 PM UTC 24 | 322335051 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.1427097557 | Oct 09 10:51:07 PM UTC 24 | Oct 09 10:51:25 PM UTC 24 | 361533264 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.1656823856 | Oct 09 10:51:03 PM UTC 24 | Oct 09 10:51:25 PM UTC 24 | 327592271 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1262816892 | Oct 09 10:51:14 PM UTC 24 | Oct 09 10:51:25 PM UTC 24 | 613084848 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.1583350569 | Oct 09 10:51:18 PM UTC 24 | Oct 09 10:51:27 PM UTC 24 | 233531391 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3619605964 | Oct 09 10:51:19 PM UTC 24 | Oct 09 10:51:28 PM UTC 24 | 124420382 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.3150125821 | Oct 09 10:51:20 PM UTC 24 | Oct 09 10:51:30 PM UTC 24 | 180903067 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3800091348 | Oct 09 10:51:18 PM UTC 24 | Oct 09 10:51:31 PM UTC 24 | 1118592777 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1683351101 | Oct 09 10:51:26 PM UTC 24 | Oct 09 10:51:32 PM UTC 24 | 346848182 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.461339533 | Oct 09 10:51:19 PM UTC 24 | Oct 09 10:51:32 PM UTC 24 | 1023642021 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.1080678087 | Oct 09 10:51:16 PM UTC 24 | Oct 09 10:51:34 PM UTC 24 | 247167737 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.455495569 | Oct 09 10:51:26 PM UTC 24 | Oct 09 10:51:34 PM UTC 24 | 457013505 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2166981689 | Oct 09 10:51:26 PM UTC 24 | Oct 09 10:51:35 PM UTC 24 | 238956231 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.1769031875 | Oct 09 10:51:11 PM UTC 24 | Oct 09 10:51:40 PM UTC 24 | 585072019 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.1834866420 | Oct 09 10:51:24 PM UTC 24 | Oct 09 10:51:40 PM UTC 24 | 703716516 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.2947115740 | Oct 09 10:51:32 PM UTC 24 | Oct 09 10:51:42 PM UTC 24 | 555725025 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.1915441956 | Oct 09 10:51:28 PM UTC 24 | Oct 09 10:51:42 PM UTC 24 | 289902297 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2036864684 | Oct 09 10:50:39 PM UTC 24 | Oct 09 10:51:44 PM UTC 24 | 247746492 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.387329238 | Oct 09 10:51:36 PM UTC 24 | Oct 09 10:51:44 PM UTC 24 | 164271360 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.907989110 | Oct 09 10:50:46 PM UTC 24 | Oct 09 10:51:44 PM UTC 24 | 405666255 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4227060045 | Oct 09 10:50:39 PM UTC 24 | Oct 09 10:51:47 PM UTC 24 | 6431543945 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3258770415 | Oct 09 10:51:34 PM UTC 24 | Oct 09 10:51:49 PM UTC 24 | 556192164 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2230367312 | Oct 09 10:50:41 PM UTC 24 | Oct 09 10:51:49 PM UTC 24 | 4959950153 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1266658541 | Oct 09 10:50:51 PM UTC 24 | Oct 09 10:51:50 PM UTC 24 | 1811468741 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.3997102159 | Oct 09 10:51:44 PM UTC 24 | Oct 09 10:51:52 PM UTC 24 | 518517633 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.355294987 | Oct 09 10:51:32 PM UTC 24 | Oct 09 10:51:52 PM UTC 24 | 542090269 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.977154752 | Oct 09 10:51:42 PM UTC 24 | Oct 09 10:51:52 PM UTC 24 | 562284633 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1459029928 | Oct 09 10:50:37 PM UTC 24 | Oct 09 10:51:54 PM UTC 24 | 4628119205 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.1103723919 | Oct 09 10:51:45 PM UTC 24 | Oct 09 10:51:54 PM UTC 24 | 1338786035 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3206248582 | Oct 09 10:50:51 PM UTC 24 | Oct 09 10:51:57 PM UTC 24 | 3737315225 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1204312759 | Oct 09 10:51:48 PM UTC 24 | Oct 09 10:52:00 PM UTC 24 | 378858315 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.1085136811 | Oct 09 10:51:43 PM UTC 24 | Oct 09 10:52:00 PM UTC 24 | 2100118467 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1760416728 | Oct 09 10:51:50 PM UTC 24 | Oct 09 10:52:00 PM UTC 24 | 164463733 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1226137354 | Oct 09 10:51:41 PM UTC 24 | Oct 09 10:52:01 PM UTC 24 | 1218069908 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.2000678598 | Oct 09 10:51:56 PM UTC 24 | Oct 09 10:52:04 PM UTC 24 | 372249573 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.700678159 | Oct 09 10:51:52 PM UTC 24 | Oct 09 10:52:04 PM UTC 24 | 591497690 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1312468506 | Oct 09 10:51:00 PM UTC 24 | Oct 09 10:52:05 PM UTC 24 | 2826027458 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2024205416 | Oct 09 10:51:54 PM UTC 24 | Oct 09 10:52:07 PM UTC 24 | 703438114 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.1905485220 | Oct 09 10:51:58 PM UTC 24 | Oct 09 10:52:09 PM UTC 24 | 173966277 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.3653910909 | Oct 09 10:52:02 PM UTC 24 | Oct 09 10:52:09 PM UTC 24 | 169379386 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3837741970 | Oct 09 10:51:50 PM UTC 24 | Oct 09 10:52:11 PM UTC 24 | 715096629 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.426150138 | Oct 09 10:52:05 PM UTC 24 | Oct 09 10:52:16 PM UTC 24 | 490136581 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.4190389128 | Oct 09 10:51:56 PM UTC 24 | Oct 09 10:52:17 PM UTC 24 | 4874013393 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.3557704537 | Oct 09 10:52:01 PM UTC 24 | Oct 09 10:52:19 PM UTC 24 | 1069171268 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.958577957 | Oct 09 10:50:42 PM UTC 24 | Oct 09 10:52:21 PM UTC 24 | 2988667631 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.730572723 | Oct 09 10:52:10 PM UTC 24 | Oct 09 10:52:22 PM UTC 24 | 1024158085 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.4123943879 | Oct 09 10:50:36 PM UTC 24 | Oct 09 10:52:23 PM UTC 24 | 733102055 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.3193597642 | Oct 09 10:52:09 PM UTC 24 | Oct 09 10:52:27 PM UTC 24 | 2097064930 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.1103568290 | Oct 09 10:52:17 PM UTC 24 | Oct 09 10:52:28 PM UTC 24 | 566153078 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.2212363884 | Oct 09 10:52:12 PM UTC 24 | Oct 09 10:52:29 PM UTC 24 | 245451542 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.3706313725 | Oct 09 10:50:44 PM UTC 24 | Oct 09 10:52:30 PM UTC 24 | 823412004 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.4084492960 | Oct 09 10:52:04 PM UTC 24 | Oct 09 10:52:30 PM UTC 24 | 340645130 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1248089502 | Oct 09 10:50:58 PM UTC 24 | Oct 09 10:52:31 PM UTC 24 | 1694752865 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.911638590 | Oct 09 10:52:23 PM UTC 24 | Oct 09 10:52:33 PM UTC 24 | 167281643 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.3926991611 | Oct 09 10:52:19 PM UTC 24 | Oct 09 10:52:35 PM UTC 24 | 378219108 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.1392740432 | Oct 09 10:50:34 PM UTC 24 | Oct 09 10:52:37 PM UTC 24 | 1383961110 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3069462963 | Oct 09 10:52:31 PM UTC 24 | Oct 09 10:52:37 PM UTC 24 | 579395333 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.1585137629 | Oct 09 10:52:28 PM UTC 24 | Oct 09 10:52:40 PM UTC 24 | 137297401 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2502946802 | Oct 09 10:52:24 PM UTC 24 | Oct 09 10:52:45 PM UTC 24 | 1217406370 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.541609602 | Oct 09 10:52:34 PM UTC 24 | Oct 09 10:52:46 PM UTC 24 | 181394069 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.1262945030 | Oct 09 10:52:32 PM UTC 24 | Oct 09 10:52:48 PM UTC 24 | 204226436 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.1347597680 | Oct 09 10:52:29 PM UTC 24 | Oct 09 10:52:49 PM UTC 24 | 1028801550 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.2127079400 | Oct 09 10:52:40 PM UTC 24 | Oct 09 10:52:49 PM UTC 24 | 990172762 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2771994484 | Oct 09 10:51:43 PM UTC 24 | Oct 09 10:52:49 PM UTC 24 | 8682072888 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2307770539 | Oct 09 10:50:34 PM UTC 24 | Oct 09 10:52:51 PM UTC 24 | 8723313611 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.140546690 | Oct 09 10:52:38 PM UTC 24 | Oct 09 10:52:52 PM UTC 24 | 372771132 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.2337215255 | Oct 09 10:52:46 PM UTC 24 | Oct 09 10:52:54 PM UTC 24 | 683544080 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2460287608 | Oct 09 10:51:09 PM UTC 24 | Oct 09 10:52:54 PM UTC 24 | 5464251106 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2403388606 | Oct 09 10:51:18 PM UTC 24 | Oct 09 10:52:55 PM UTC 24 | 7122977425 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.4261169665 | Oct 09 10:53:30 PM UTC 24 | Oct 09 10:53:38 PM UTC 24 | 385400396 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.3385747731 | Oct 09 10:52:50 PM UTC 24 | Oct 09 10:52:58 PM UTC 24 | 764409882 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.1634395729 | Oct 09 10:52:48 PM UTC 24 | Oct 09 10:53:00 PM UTC 24 | 426268282 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.2016636334 | Oct 09 10:52:52 PM UTC 24 | Oct 09 10:53:03 PM UTC 24 | 315656746 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.3085497059 | Oct 09 10:52:45 PM UTC 24 | Oct 09 10:53:04 PM UTC 24 | 210208423 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3830407698 | Oct 09 10:51:15 PM UTC 24 | Oct 09 10:53:04 PM UTC 24 | 5747863589 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3131830040 | Oct 09 10:52:56 PM UTC 24 | Oct 09 10:53:05 PM UTC 24 | 692343223 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3994146799 | Oct 09 10:52:55 PM UTC 24 | Oct 09 10:53:10 PM UTC 24 | 873296341 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1236131113 | Oct 09 10:53:01 PM UTC 24 | Oct 09 10:53:14 PM UTC 24 | 568559083 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.4089943276 | Oct 09 10:50:36 PM UTC 24 | Oct 09 10:53:14 PM UTC 24 | 10025932530 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.2629740011 | Oct 09 10:53:06 PM UTC 24 | Oct 09 10:53:15 PM UTC 24 | 556811767 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.568034743 | Oct 09 10:51:50 PM UTC 24 | Oct 09 10:53:15 PM UTC 24 | 11232438137 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.2395350699 | Oct 09 10:52:50 PM UTC 24 | Oct 09 10:53:17 PM UTC 24 | 2054913356 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1163465418 | Oct 09 10:51:21 PM UTC 24 | Oct 09 10:53:18 PM UTC 24 | 24343180008 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2534729416 | Oct 09 10:50:56 PM UTC 24 | Oct 09 10:53:19 PM UTC 24 | 3175501514 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.490222208 | Oct 09 10:53:11 PM UTC 24 | Oct 09 10:53:20 PM UTC 24 | 224540113 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.4121052207 | Oct 09 10:53:04 PM UTC 24 | Oct 09 10:53:22 PM UTC 24 | 1124950530 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.2626084223 | Oct 09 10:53:16 PM UTC 24 | Oct 09 10:53:23 PM UTC 24 | 592498399 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3576365111 | Oct 09 10:50:53 PM UTC 24 | Oct 09 10:53:24 PM UTC 24 | 2497332440 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.3336456291 | Oct 09 10:52:59 PM UTC 24 | Oct 09 10:53:24 PM UTC 24 | 4835194146 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3465494679 | Oct 09 10:51:55 PM UTC 24 | Oct 09 10:53:28 PM UTC 24 | 2825428114 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1023700458 | Oct 09 10:50:36 PM UTC 24 | Oct 09 10:53:28 PM UTC 24 | 12490265299 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2468787830 | Oct 09 10:50:34 PM UTC 24 | Oct 09 10:53:29 PM UTC 24 | 13268142130 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1786155489 | Oct 09 10:53:18 PM UTC 24 | Oct 09 10:53:29 PM UTC 24 | 563319961 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2240505968 | Oct 09 10:51:45 PM UTC 24 | Oct 09 10:53:29 PM UTC 24 | 6764039566 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.145030869 | Oct 09 10:53:23 PM UTC 24 | Oct 09 10:53:30 PM UTC 24 | 2526320436 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3145744391 | Oct 09 10:51:53 PM UTC 24 | Oct 09 10:53:31 PM UTC 24 | 8137022113 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.4151998670 | Oct 09 10:53:15 PM UTC 24 | Oct 09 10:53:34 PM UTC 24 | 535740298 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2925330047 | Oct 09 10:51:11 PM UTC 24 | Oct 09 10:53:34 PM UTC 24 | 4154624462 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.554762408 | Oct 09 10:53:09 PM UTC 24 | Oct 09 10:53:35 PM UTC 24 | 472812731 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.1540538812 | Oct 09 10:53:25 PM UTC 24 | Oct 09 10:53:36 PM UTC 24 | 136519333 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2876471391 | Oct 09 10:51:04 PM UTC 24 | Oct 09 10:53:36 PM UTC 24 | 2252205959 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.3166146952 | Oct 09 10:53:21 PM UTC 24 | Oct 09 10:53:36 PM UTC 24 | 546356471 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2645843843 | Oct 09 10:53:24 PM UTC 24 | Oct 09 10:53:39 PM UTC 24 | 665989219 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.106278633 | Oct 09 10:53:16 PM UTC 24 | Oct 09 10:53:38 PM UTC 24 | 948852143 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.3847662122 | Oct 09 10:53:30 PM UTC 24 | Oct 09 10:53:40 PM UTC 24 | 391514311 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.2090444001 | Oct 09 10:53:35 PM UTC 24 | Oct 09 10:53:42 PM UTC 24 | 371724037 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.2676032884 | Oct 09 10:53:29 PM UTC 24 | Oct 09 10:53:43 PM UTC 24 | 1068214851 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.544796065 | Oct 09 10:51:27 PM UTC 24 | Oct 09 10:53:44 PM UTC 24 | 2738362871 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.1335621072 | Oct 09 10:53:36 PM UTC 24 | Oct 09 10:53:44 PM UTC 24 | 179096865 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.1270278161 | Oct 09 10:53:18 PM UTC 24 | Oct 09 10:53:44 PM UTC 24 | 3424464784 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2527749412 | Oct 09 10:53:19 PM UTC 24 | Oct 09 10:55:00 PM UTC 24 | 6945193041 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.1759962205 | Oct 09 10:53:38 PM UTC 24 | Oct 09 10:53:46 PM UTC 24 | 400652471 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1569669406 | Oct 09 10:52:50 PM UTC 24 | Oct 09 10:53:47 PM UTC 24 | 5247998032 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.3316686447 | Oct 09 10:53:31 PM UTC 24 | Oct 09 10:53:49 PM UTC 24 | 1172518969 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1130565211 | Oct 09 10:52:10 PM UTC 24 | Oct 09 10:53:49 PM UTC 24 | 2714802416 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.420390187 | Oct 09 10:53:36 PM UTC 24 | Oct 09 10:53:50 PM UTC 24 | 786561055 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2769419126 | Oct 09 10:53:40 PM UTC 24 | Oct 09 10:53:51 PM UTC 24 | 155651693 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.695965844 | Oct 09 10:53:37 PM UTC 24 | Oct 09 10:53:52 PM UTC 24 | 206671012 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.1442561425 | Oct 09 10:53:30 PM UTC 24 | Oct 09 10:53:53 PM UTC 24 | 330123693 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2603346564 | Oct 09 10:50:46 PM UTC 24 | Oct 09 10:53:54 PM UTC 24 | 4992847020 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.1824356015 | Oct 09 10:53:45 PM UTC 24 | Oct 09 10:53:55 PM UTC 24 | 136345526 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.199305281 | Oct 09 10:53:45 PM UTC 24 | Oct 09 10:53:55 PM UTC 24 | 169646440 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2372341833 | Oct 09 10:53:39 PM UTC 24 | Oct 09 10:53:58 PM UTC 24 | 10740401971 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.1909295054 | Oct 09 10:53:50 PM UTC 24 | Oct 09 10:53:59 PM UTC 24 | 167412483 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.2363785895 | Oct 09 10:53:43 PM UTC 24 | Oct 09 10:54:00 PM UTC 24 | 296625798 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.972797515 | Oct 09 10:53:45 PM UTC 24 | Oct 09 10:54:01 PM UTC 24 | 692445325 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2739543427 | Oct 09 10:51:44 PM UTC 24 | Oct 09 10:54:02 PM UTC 24 | 3837335415 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.849792568 | Oct 09 10:53:52 PM UTC 24 | Oct 09 10:54:04 PM UTC 24 | 136357858 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.4069808940 | Oct 09 10:53:55 PM UTC 24 | Oct 09 10:54:04 PM UTC 24 | 123663885 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.4175370344 | Oct 09 10:53:52 PM UTC 24 | Oct 09 10:54:05 PM UTC 24 | 199176779 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.4243223905 | Oct 09 10:53:46 PM UTC 24 | Oct 09 10:54:05 PM UTC 24 | 401165146 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1563902319 | Oct 09 10:52:18 PM UTC 24 | Oct 09 10:54:09 PM UTC 24 | 6557580168 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.1149273838 | Oct 09 10:53:58 PM UTC 24 | Oct 09 10:54:09 PM UTC 24 | 575040444 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.2050407622 | Oct 09 10:54:02 PM UTC 24 | Oct 09 10:54:09 PM UTC 24 | 170686905 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.3357469588 | Oct 09 10:54:04 PM UTC 24 | Oct 09 10:54:12 PM UTC 24 | 136842498 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3570254287 | Oct 09 10:50:55 PM UTC 24 | Oct 09 10:54:14 PM UTC 24 | 20170758196 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.1645628852 | Oct 09 10:54:00 PM UTC 24 | Oct 09 10:54:16 PM UTC 24 | 729689711 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2289642008 | Oct 09 10:52:22 PM UTC 24 | Oct 09 10:54:17 PM UTC 24 | 1804249946 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1431405987 | Oct 09 10:54:02 PM UTC 24 | Oct 09 10:54:17 PM UTC 24 | 669850242 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3540439245 | Oct 09 10:51:10 PM UTC 24 | Oct 09 10:54:17 PM UTC 24 | 49387903834 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.1374068726 | Oct 09 10:53:53 PM UTC 24 | Oct 09 10:54:17 PM UTC 24 | 1925570800 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.3272352847 | Oct 09 10:53:56 PM UTC 24 | Oct 09 10:54:19 PM UTC 24 | 569596110 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.616560908 | Oct 09 10:54:11 PM UTC 24 | Oct 09 10:54:19 PM UTC 24 | 123897025 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.2350291597 | Oct 09 10:54:07 PM UTC 24 | Oct 09 10:54:21 PM UTC 24 | 299274595 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.3118710698 | Oct 09 10:54:11 PM UTC 24 | Oct 09 10:54:21 PM UTC 24 | 248010049 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.874535808 | Oct 09 10:51:25 PM UTC 24 | Oct 09 10:54:23 PM UTC 24 | 77156856667 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.90850137 | Oct 09 10:54:17 PM UTC 24 | Oct 09 10:54:26 PM UTC 24 | 124363036 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2753444430 | Oct 09 10:52:05 PM UTC 24 | Oct 09 10:54:26 PM UTC 24 | 10690827236 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1375520197 | Oct 09 10:54:20 PM UTC 24 | Oct 09 10:54:29 PM UTC 24 | 451141034 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.3369433628 | Oct 09 10:54:19 PM UTC 24 | Oct 09 10:54:30 PM UTC 24 | 3437194673 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.325376379 | Oct 09 10:51:34 PM UTC 24 | Oct 09 10:54:30 PM UTC 24 | 9978152008 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.1471633918 | Oct 09 10:54:19 PM UTC 24 | Oct 09 10:54:31 PM UTC 24 | 213596245 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.4081162451 | Oct 09 10:54:19 PM UTC 24 | Oct 09 10:54:31 PM UTC 24 | 180715229 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.429320209 | Oct 09 10:53:30 PM UTC 24 | Oct 09 10:54:32 PM UTC 24 | 4394763219 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.1350595656 | Oct 09 10:54:16 PM UTC 24 | Oct 09 10:54:32 PM UTC 24 | 1315795574 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.505613610 | Oct 09 10:54:22 PM UTC 24 | Oct 09 10:54:33 PM UTC 24 | 1254451846 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.458966282 | Oct 09 10:54:11 PM UTC 24 | Oct 09 10:54:36 PM UTC 24 | 317228639 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3947254930 | Oct 09 10:52:53 PM UTC 24 | Oct 09 10:54:38 PM UTC 24 | 10476242166 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3308788546 | Oct 09 10:51:33 PM UTC 24 | Oct 09 10:54:38 PM UTC 24 | 5305251679 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.3638273182 | Oct 09 10:54:30 PM UTC 24 | Oct 09 10:54:39 PM UTC 24 | 292281198 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.3505259475 | Oct 09 10:54:33 PM UTC 24 | Oct 09 10:54:41 PM UTC 24 | 771349045 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.4117656937 | Oct 09 10:54:21 PM UTC 24 | Oct 09 10:54:41 PM UTC 24 | 166140348 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.1772241024 | Oct 09 10:54:32 PM UTC 24 | Oct 09 10:54:42 PM UTC 24 | 132821465 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1981077195 | Oct 09 10:53:29 PM UTC 24 | Oct 09 10:54:44 PM UTC 24 | 2817276036 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2323351791 | Oct 09 10:54:32 PM UTC 24 | Oct 09 10:54:45 PM UTC 24 | 194243782 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2182821996 | Oct 09 10:54:26 PM UTC 24 | Oct 09 10:54:45 PM UTC 24 | 559130984 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1179759110 | Oct 09 10:54:37 PM UTC 24 | Oct 09 10:54:49 PM UTC 24 | 131522757 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.821857918 | Oct 09 10:54:42 PM UTC 24 | Oct 09 10:54:50 PM UTC 24 | 2091687005 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2766701004 | Oct 09 10:54:39 PM UTC 24 | Oct 09 10:54:51 PM UTC 24 | 704176093 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2258005919 | Oct 09 10:54:32 PM UTC 24 | Oct 09 10:54:51 PM UTC 24 | 536899039 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.3660774275 | Oct 09 10:54:42 PM UTC 24 | Oct 09 10:54:52 PM UTC 24 | 152601852 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1684300632 | Oct 09 10:53:22 PM UTC 24 | Oct 09 10:54:53 PM UTC 24 | 8078878128 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3237773400 | Oct 09 10:52:01 PM UTC 24 | Oct 09 10:54:53 PM UTC 24 | 2575323932 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.1816507148 | Oct 09 10:54:43 PM UTC 24 | Oct 09 10:54:53 PM UTC 24 | 313055176 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.4008077778 | Oct 09 10:54:34 PM UTC 24 | Oct 09 10:54:54 PM UTC 24 | 554268544 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2443892313 | Oct 09 10:52:31 PM UTC 24 | Oct 09 10:54:57 PM UTC 24 | 32931399436 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3629552076 | Oct 09 10:54:49 PM UTC 24 | Oct 09 10:54:57 PM UTC 24 | 220638619 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.916198887 | Oct 09 10:52:47 PM UTC 24 | Oct 09 10:54:57 PM UTC 24 | 4702815006 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.698138689 | Oct 09 10:54:46 PM UTC 24 | Oct 09 10:55:01 PM UTC 24 | 213629793 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1966560687 | Oct 09 10:54:52 PM UTC 24 | Oct 09 10:55:02 PM UTC 24 | 566820068 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2456850416 | Oct 09 10:53:41 PM UTC 24 | Oct 09 10:55:03 PM UTC 24 | 4152065135 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1371061537 | Oct 09 10:54:54 PM UTC 24 | Oct 09 10:55:03 PM UTC 24 | 557578901 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.471965551 | Oct 09 10:54:20 PM UTC 24 | Oct 09 10:55:03 PM UTC 24 | 973346506 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.195131534 | Oct 09 10:54:52 PM UTC 24 | Oct 09 10:55:04 PM UTC 24 | 655801434 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.1079500583 | Oct 09 10:54:54 PM UTC 24 | Oct 09 10:55:04 PM UTC 24 | 1965635076 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2549608389 | Oct 09 10:53:44 PM UTC 24 | Oct 09 10:55:04 PM UTC 24 | 2346006017 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1295549635 | Oct 09 10:54:59 PM UTC 24 | Oct 09 10:55:05 PM UTC 24 | 730415220 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.813829250 | Oct 09 10:54:53 PM UTC 24 | Oct 09 10:55:07 PM UTC 24 | 763870675 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.872065684 | Oct 09 10:52:28 PM UTC 24 | Oct 09 10:55:09 PM UTC 24 | 2011485124 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2756746266 | Oct 09 10:54:57 PM UTC 24 | Oct 09 10:55:09 PM UTC 24 | 1031333823 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.3274622140 | Oct 09 10:54:54 PM UTC 24 | Oct 09 10:55:11 PM UTC 24 | 2197773660 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3102816906 | Oct 09 10:53:15 PM UTC 24 | Oct 09 10:55:12 PM UTC 24 | 7598120226 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3594423286 | Oct 09 10:53:37 PM UTC 24 | Oct 09 10:55:12 PM UTC 24 | 5200635676 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.1642669880 | Oct 09 10:55:02 PM UTC 24 | Oct 09 10:55:12 PM UTC 24 | 176863484 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_10_08/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.1949837862 | Oct 09 10:55:04 PM UTC 24 | Oct 09 10:55:12 PM UTC 24 | 125301912 ps |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |