| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.84 | 99.36 | 92.13 | 97.67 | 100.00 | 98.55 | 98.06 | 99.06 |
| T305 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.823879805 | Oct 12 01:12:00 AM UTC 24 | Oct 12 01:12:10 AM UTC 24 | 166999268 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.1404612875 | Oct 12 01:11:56 AM UTC 24 | Oct 12 01:12:10 AM UTC 24 | 298103603 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.403994619 | Oct 12 01:11:59 AM UTC 24 | Oct 12 01:12:11 AM UTC 24 | 1067923908 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1499000164 | Oct 12 01:12:00 AM UTC 24 | Oct 12 01:12:12 AM UTC 24 | 177524573 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3487977744 | Oct 12 01:11:59 AM UTC 24 | Oct 12 01:12:13 AM UTC 24 | 1270488185 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.903422176 | Oct 12 01:09:23 AM UTC 24 | Oct 12 01:12:13 AM UTC 24 | 3665296107 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1934823738 | Oct 12 01:12:06 AM UTC 24 | Oct 12 01:12:14 AM UTC 24 | 604731327 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.3668090127 | Oct 12 01:12:08 AM UTC 24 | Oct 12 01:12:14 AM UTC 24 | 581807239 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.435578352 | Oct 12 01:12:01 AM UTC 24 | Oct 12 01:12:16 AM UTC 24 | 288165062 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2306384148 | Oct 12 01:12:08 AM UTC 24 | Oct 12 01:12:16 AM UTC 24 | 409879092 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.3112783886 | Oct 12 01:12:06 AM UTC 24 | Oct 12 01:12:16 AM UTC 24 | 180309963 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.576373911 | Oct 12 01:10:30 AM UTC 24 | Oct 12 01:12:17 AM UTC 24 | 2425033505 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1855037345 | Oct 12 01:10:32 AM UTC 24 | Oct 12 01:12:18 AM UTC 24 | 2289522702 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.1508396223 | Oct 12 01:12:12 AM UTC 24 | Oct 12 01:12:21 AM UTC 24 | 172209261 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.3704989206 | Oct 12 01:12:07 AM UTC 24 | Oct 12 01:12:23 AM UTC 24 | 731162964 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.1417476080 | Oct 12 01:12:00 AM UTC 24 | Oct 12 01:12:24 AM UTC 24 | 331342834 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3121772250 | Oct 12 01:12:06 AM UTC 24 | Oct 12 01:12:26 AM UTC 24 | 411145985 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.1091791240 | Oct 12 01:12:10 AM UTC 24 | Oct 12 01:12:27 AM UTC 24 | 535685119 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4227951491 | Oct 12 01:09:38 AM UTC 24 | Oct 12 01:12:28 AM UTC 24 | 2442540607 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.227652218 | Oct 12 01:10:43 AM UTC 24 | Oct 12 01:12:32 AM UTC 24 | 8324713681 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.344707870 | Oct 12 01:11:46 AM UTC 24 | Oct 12 01:12:35 AM UTC 24 | 1097959934 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2980276498 | Oct 12 01:09:54 AM UTC 24 | Oct 12 01:12:37 AM UTC 24 | 9269577474 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.3897106492 | Oct 12 01:12:08 AM UTC 24 | Oct 12 01:12:41 AM UTC 24 | 415076473 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4049086935 | Oct 12 01:11:20 AM UTC 24 | Oct 12 01:12:49 AM UTC 24 | 5289920928 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.158755853 | Oct 12 01:09:06 AM UTC 24 | Oct 12 01:12:49 AM UTC 24 | 6894982574 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3882255242 | Oct 12 01:09:47 AM UTC 24 | Oct 12 01:12:49 AM UTC 24 | 2450302723 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2472094997 | Oct 12 01:09:21 AM UTC 24 | Oct 12 01:12:58 AM UTC 24 | 14515509827 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1831276055 | Oct 12 01:11:15 AM UTC 24 | Oct 12 01:13:04 AM UTC 24 | 2476261908 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2467368886 | Oct 12 01:10:27 AM UTC 24 | Oct 12 01:13:04 AM UTC 24 | 40650044049 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3116463204 | Oct 12 01:10:55 AM UTC 24 | Oct 12 01:13:10 AM UTC 24 | 35569498122 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2967463262 | Oct 12 01:10:28 AM UTC 24 | Oct 12 01:13:13 AM UTC 24 | 19168034865 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3015433514 | Oct 12 01:11:09 AM UTC 24 | Oct 12 01:13:19 AM UTC 24 | 2926140808 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3858924263 | Oct 12 01:11:59 AM UTC 24 | Oct 12 01:13:28 AM UTC 24 | 1489737109 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3736658893 | Oct 12 01:10:05 AM UTC 24 | Oct 12 01:13:29 AM UTC 24 | 11960514257 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2920688501 | Oct 12 01:11:33 AM UTC 24 | Oct 12 01:13:34 AM UTC 24 | 2279339424 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2689184095 | Oct 12 01:11:24 AM UTC 24 | Oct 12 01:13:35 AM UTC 24 | 3080532688 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4262219971 | Oct 12 01:11:29 AM UTC 24 | Oct 12 01:13:37 AM UTC 24 | 3906693234 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.77602551 | Oct 12 01:11:40 AM UTC 24 | Oct 12 01:13:38 AM UTC 24 | 2479651677 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2752897686 | Oct 12 01:09:40 AM UTC 24 | Oct 12 01:13:39 AM UTC 24 | 12862091429 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2240385726 | Oct 12 01:11:55 AM UTC 24 | Oct 12 01:13:48 AM UTC 24 | 2365500395 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.4167939567 | Oct 12 01:11:56 AM UTC 24 | Oct 12 01:13:55 AM UTC 24 | 61966773656 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.4217174623 | Oct 12 01:10:48 AM UTC 24 | Oct 12 01:13:57 AM UTC 24 | 15180509072 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2934037059 | Oct 12 01:11:45 AM UTC 24 | Oct 12 01:14:00 AM UTC 24 | 2113405532 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.8048710 | Oct 12 01:12:08 AM UTC 24 | Oct 12 01:14:02 AM UTC 24 | 3983940751 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2715710419 | Oct 12 01:12:00 AM UTC 24 | Oct 12 01:14:06 AM UTC 24 | 4010391417 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2551976335 | Oct 12 01:11:11 AM UTC 24 | Oct 12 01:14:25 AM UTC 24 | 39066931149 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1181911963 | Oct 12 01:12:07 AM UTC 24 | Oct 12 01:14:38 AM UTC 24 | 2201063382 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3897469006 | Oct 12 01:10:12 AM UTC 24 | Oct 12 01:14:39 AM UTC 24 | 5905296504 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.708440910 | Oct 12 01:11:59 AM UTC 24 | Oct 12 01:14:41 AM UTC 24 | 3558227429 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3601775691 | Oct 12 01:10:47 AM UTC 24 | Oct 12 01:14:46 AM UTC 24 | 3899781366 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3917468446 | Oct 12 01:08:33 AM UTC 24 | Oct 12 01:14:54 AM UTC 24 | 4861707003 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2007336182 | Oct 12 01:11:51 AM UTC 24 | Oct 12 01:15:03 AM UTC 24 | 6010381962 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.329646597 | Oct 12 01:11:52 AM UTC 24 | Oct 12 01:15:05 AM UTC 24 | 19938935112 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3239496243 | Oct 12 01:10:42 AM UTC 24 | Oct 12 01:15:13 AM UTC 24 | 5445512640 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2944930428 | Oct 12 01:12:04 AM UTC 24 | Oct 12 01:15:33 AM UTC 24 | 24812916214 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3122173552 | Oct 12 01:12:08 AM UTC 24 | Oct 12 01:15:36 AM UTC 24 | 3408890157 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2834970137 | Oct 12 01:11:43 AM UTC 24 | Oct 12 01:15:44 AM UTC 24 | 41227630846 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2247408565 | Oct 12 01:12:15 AM UTC 24 | Oct 12 01:12:23 AM UTC 24 | 1693086795 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4289415276 | Oct 12 01:12:14 AM UTC 24 | Oct 12 01:12:23 AM UTC 24 | 299789080 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.875533096 | Oct 12 01:12:16 AM UTC 24 | Oct 12 01:12:24 AM UTC 24 | 385021767 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.411454162 | Oct 12 01:12:17 AM UTC 24 | Oct 12 01:12:26 AM UTC 24 | 1578143176 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.670418532 | Oct 12 01:12:17 AM UTC 24 | Oct 12 01:12:26 AM UTC 24 | 172385520 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.120939713 | Oct 12 01:12:18 AM UTC 24 | Oct 12 01:12:27 AM UTC 24 | 123531659 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.54088652 | Oct 12 01:12:17 AM UTC 24 | Oct 12 01:12:27 AM UTC 24 | 171774435 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.610163050 | Oct 12 01:12:18 AM UTC 24 | Oct 12 01:12:28 AM UTC 24 | 214149404 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3163454086 | Oct 12 01:12:21 AM UTC 24 | Oct 12 01:12:29 AM UTC 24 | 932546428 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3739197861 | Oct 12 01:12:25 AM UTC 24 | Oct 12 01:12:32 AM UTC 24 | 162541951 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1641254912 | Oct 12 01:12:27 AM UTC 24 | Oct 12 01:12:33 AM UTC 24 | 209978761 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1122499078 | Oct 12 01:12:25 AM UTC 24 | Oct 12 01:12:34 AM UTC 24 | 171223374 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3463296726 | Oct 12 01:12:28 AM UTC 24 | Oct 12 01:12:35 AM UTC 24 | 203412444 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1884257734 | Oct 12 01:12:27 AM UTC 24 | Oct 12 01:12:36 AM UTC 24 | 452232098 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.459300562 | Oct 12 01:12:27 AM UTC 24 | Oct 12 01:12:36 AM UTC 24 | 562494366 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2801399710 | Oct 12 01:12:28 AM UTC 24 | Oct 12 01:12:37 AM UTC 24 | 534568966 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1702486231 | Oct 12 01:12:28 AM UTC 24 | Oct 12 01:12:38 AM UTC 24 | 269353328 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1403714801 | Oct 12 01:12:29 AM UTC 24 | Oct 12 01:12:40 AM UTC 24 | 552999273 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.764468626 | Oct 12 01:12:33 AM UTC 24 | Oct 12 01:12:40 AM UTC 24 | 124417873 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.322758617 | Oct 12 01:12:33 AM UTC 24 | Oct 12 01:12:41 AM UTC 24 | 164101843 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2194081108 | Oct 12 01:12:23 AM UTC 24 | Oct 12 01:12:42 AM UTC 24 | 1938972749 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4003116336 | Oct 12 01:12:33 AM UTC 24 | Oct 12 01:12:43 AM UTC 24 | 391523311 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1839603819 | Oct 12 01:12:35 AM UTC 24 | Oct 12 01:12:43 AM UTC 24 | 125215570 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4128598824 | Oct 12 01:12:37 AM UTC 24 | Oct 12 01:12:45 AM UTC 24 | 139233133 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4110633451 | Oct 12 01:12:37 AM UTC 24 | Oct 12 01:12:45 AM UTC 24 | 127090045 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.747729293 | Oct 12 01:12:37 AM UTC 24 | Oct 12 01:12:45 AM UTC 24 | 532775874 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4065784547 | Oct 12 01:12:37 AM UTC 24 | Oct 12 01:12:46 AM UTC 24 | 535591060 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3038186759 | Oct 12 01:12:41 AM UTC 24 | Oct 12 01:12:47 AM UTC 24 | 125525461 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4287053201 | Oct 12 01:13:05 AM UTC 24 | Oct 12 01:13:14 AM UTC 24 | 336491513 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1795980756 | Oct 12 01:12:41 AM UTC 24 | Oct 12 01:12:47 AM UTC 24 | 1414114799 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3216111660 | Oct 12 01:12:41 AM UTC 24 | Oct 12 01:12:50 AM UTC 24 | 555415139 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.825444002 | Oct 12 01:12:42 AM UTC 24 | Oct 12 01:12:51 AM UTC 24 | 305401025 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4290877145 | Oct 12 01:12:13 AM UTC 24 | Oct 12 01:12:51 AM UTC 24 | 895859588 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.882761651 | Oct 12 01:12:44 AM UTC 24 | Oct 12 01:12:52 AM UTC 24 | 183436502 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.849875564 | Oct 12 01:12:44 AM UTC 24 | Oct 12 01:12:52 AM UTC 24 | 493354605 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3932817401 | Oct 12 01:12:38 AM UTC 24 | Oct 12 01:12:53 AM UTC 24 | 315828160 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3074701107 | Oct 12 01:12:41 AM UTC 24 | Oct 12 01:12:54 AM UTC 24 | 461997690 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1851422945 | Oct 12 01:12:42 AM UTC 24 | Oct 12 01:12:54 AM UTC 24 | 5489821327 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.828548222 | Oct 12 01:12:47 AM UTC 24 | Oct 12 01:12:54 AM UTC 24 | 140768733 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.977265423 | Oct 12 01:12:46 AM UTC 24 | Oct 12 01:12:54 AM UTC 24 | 294579105 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3001963930 | Oct 12 01:12:48 AM UTC 24 | Oct 12 01:12:56 AM UTC 24 | 299646831 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2855096405 | Oct 12 01:12:49 AM UTC 24 | Oct 12 01:12:56 AM UTC 24 | 173213826 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.583342898 | Oct 12 01:12:49 AM UTC 24 | Oct 12 01:12:57 AM UTC 24 | 336677636 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2148829475 | Oct 12 01:12:50 AM UTC 24 | Oct 12 01:12:57 AM UTC 24 | 327045785 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2645145297 | Oct 12 01:13:12 AM UTC 24 | Oct 12 01:13:23 AM UTC 24 | 372520414 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2836518508 | Oct 12 01:12:51 AM UTC 24 | Oct 12 01:12:59 AM UTC 24 | 300499741 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1768046252 | Oct 12 01:12:50 AM UTC 24 | Oct 12 01:12:59 AM UTC 24 | 293041130 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3178327868 | Oct 12 01:12:48 AM UTC 24 | Oct 12 01:13:00 AM UTC 24 | 133573870 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2649503733 | Oct 12 01:12:23 AM UTC 24 | Oct 12 01:13:02 AM UTC 24 | 7153797642 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3958028244 | Oct 12 01:12:55 AM UTC 24 | Oct 12 01:13:02 AM UTC 24 | 398677911 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1572418776 | Oct 12 01:12:29 AM UTC 24 | Oct 12 01:13:03 AM UTC 24 | 840608003 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.687879623 | Oct 12 01:12:55 AM UTC 24 | Oct 12 01:13:04 AM UTC 24 | 169941702 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1378988569 | Oct 12 01:12:57 AM UTC 24 | Oct 12 01:13:04 AM UTC 24 | 169729855 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3820862176 | Oct 12 01:12:53 AM UTC 24 | Oct 12 01:13:05 AM UTC 24 | 169874066 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.932701927 | Oct 12 01:12:55 AM UTC 24 | Oct 12 01:13:06 AM UTC 24 | 577603958 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4162655811 | Oct 12 01:13:01 AM UTC 24 | Oct 12 01:13:07 AM UTC 24 | 425814519 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2332037419 | Oct 12 01:12:58 AM UTC 24 | Oct 12 01:13:07 AM UTC 24 | 329496637 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.709301652 | Oct 12 01:12:58 AM UTC 24 | Oct 12 01:13:07 AM UTC 24 | 2512106653 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2007769834 | Oct 12 01:12:56 AM UTC 24 | Oct 12 01:13:07 AM UTC 24 | 653336717 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1595727379 | Oct 12 01:13:00 AM UTC 24 | Oct 12 01:13:08 AM UTC 24 | 126957449 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1739904483 | Oct 12 01:13:01 AM UTC 24 | Oct 12 01:13:10 AM UTC 24 | 302972862 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2245461693 | Oct 12 01:12:59 AM UTC 24 | Oct 12 01:13:10 AM UTC 24 | 299342938 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3129041868 | Oct 12 01:13:05 AM UTC 24 | Oct 12 01:13:11 AM UTC 24 | 2092965576 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2915157915 | Oct 12 01:12:38 AM UTC 24 | Oct 12 01:13:11 AM UTC 24 | 1163946458 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.414938766 | Oct 12 01:13:05 AM UTC 24 | Oct 12 01:13:11 AM UTC 24 | 372402548 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.268320 | Oct 12 01:13:07 AM UTC 24 | Oct 12 01:13:14 AM UTC 24 | 1693833361 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2018418324 | Oct 12 01:13:08 AM UTC 24 | Oct 12 01:13:16 AM UTC 24 | 183479553 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3110650221 | Oct 12 01:13:11 AM UTC 24 | Oct 12 01:13:16 AM UTC 24 | 213491648 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3798980784 | Oct 12 01:13:07 AM UTC 24 | Oct 12 01:13:17 AM UTC 24 | 167222823 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2322990977 | Oct 12 01:13:11 AM UTC 24 | Oct 12 01:13:18 AM UTC 24 | 209880038 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4253181553 | Oct 12 01:13:06 AM UTC 24 | Oct 12 01:13:18 AM UTC 24 | 294471157 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3839287048 | Oct 12 01:12:24 AM UTC 24 | Oct 12 01:13:18 AM UTC 24 | 435414369 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.865702628 | Oct 12 01:12:15 AM UTC 24 | Oct 12 01:13:19 AM UTC 24 | 552269284 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3380017909 | Oct 12 01:13:14 AM UTC 24 | Oct 12 01:13:20 AM UTC 24 | 385728994 ps | ||
| T404 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.132429723 | Oct 12 01:13:04 AM UTC 24 | Oct 12 01:13:20 AM UTC 24 | 550938450 ps | ||
| T405 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2466148757 | Oct 12 01:13:10 AM UTC 24 | Oct 12 01:13:21 AM UTC 24 | 370763209 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1397611279 | Oct 12 01:13:12 AM UTC 24 | Oct 12 01:13:22 AM UTC 24 | 134055908 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3286267976 | Oct 12 01:13:14 AM UTC 24 | Oct 12 01:13:24 AM UTC 24 | 2780324616 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.500920674 | Oct 12 01:12:59 AM UTC 24 | Oct 12 01:13:24 AM UTC 24 | 2144453797 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2395999594 | Oct 12 01:13:03 AM UTC 24 | Oct 12 01:13:24 AM UTC 24 | 7229678935 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1716416154 | Oct 12 01:12:39 AM UTC 24 | Oct 12 01:13:25 AM UTC 24 | 510421119 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.804476347 | Oct 12 01:13:16 AM UTC 24 | Oct 12 01:13:26 AM UTC 24 | 2127329709 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1459862846 | Oct 12 01:13:17 AM UTC 24 | Oct 12 01:13:26 AM UTC 24 | 291584151 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3527440009 | Oct 12 01:13:20 AM UTC 24 | Oct 12 01:13:26 AM UTC 24 | 206388979 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2674901949 | Oct 12 01:13:20 AM UTC 24 | Oct 12 01:13:27 AM UTC 24 | 558451794 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3804222278 | Oct 12 01:13:22 AM UTC 24 | Oct 12 01:13:29 AM UTC 24 | 2096628680 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.572340516 | Oct 12 01:13:20 AM UTC 24 | Oct 12 01:13:29 AM UTC 24 | 958968017 ps | ||
| T416 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1135702259 | Oct 12 01:13:22 AM UTC 24 | Oct 12 01:13:30 AM UTC 24 | 371206040 ps | ||
| T417 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.258604220 | Oct 12 01:13:23 AM UTC 24 | Oct 12 01:13:31 AM UTC 24 | 615231581 ps | ||
| T418 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3292694197 | Oct 12 01:13:21 AM UTC 24 | Oct 12 01:13:31 AM UTC 24 | 555872715 ps | ||
| T419 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2391179261 | Oct 12 01:13:05 AM UTC 24 | Oct 12 01:13:32 AM UTC 24 | 2452645191 ps | ||
| T420 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3917140420 | Oct 12 01:13:27 AM UTC 24 | Oct 12 01:13:33 AM UTC 24 | 2095498991 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2611069660 | Oct 12 01:12:46 AM UTC 24 | Oct 12 01:13:34 AM UTC 24 | 848761618 ps | ||
| T421 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3084685812 | Oct 12 01:13:27 AM UTC 24 | Oct 12 01:13:34 AM UTC 24 | 604173084 ps | ||
| T422 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2307130689 | Oct 12 01:13:27 AM UTC 24 | Oct 12 01:13:34 AM UTC 24 | 442436371 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.620514046 | Oct 12 01:13:25 AM UTC 24 | Oct 12 01:13:36 AM UTC 24 | 194175450 ps | ||
| T424 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3783669021 | Oct 12 01:13:28 AM UTC 24 | Oct 12 01:13:37 AM UTC 24 | 385879703 ps | ||
| T425 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3555651700 | Oct 12 01:13:29 AM UTC 24 | Oct 12 01:13:37 AM UTC 24 | 367664354 ps | ||
| T426 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.509426944 | Oct 12 01:13:31 AM UTC 24 | Oct 12 01:13:39 AM UTC 24 | 1692301490 ps | ||
| T427 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4242414211 | Oct 12 01:13:09 AM UTC 24 | Oct 12 01:13:39 AM UTC 24 | 595828447 ps | ||
| T428 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3832906535 | Oct 12 01:13:30 AM UTC 24 | Oct 12 01:13:39 AM UTC 24 | 168292659 ps | ||
| T429 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3061846871 | Oct 12 01:13:30 AM UTC 24 | Oct 12 01:13:39 AM UTC 24 | 445817705 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.751337952 | Oct 12 01:12:55 AM UTC 24 | Oct 12 01:13:40 AM UTC 24 | 7866872126 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2225491147 | Oct 12 01:13:12 AM UTC 24 | Oct 12 01:13:41 AM UTC 24 | 599221904 ps | ||
| T430 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.6523576 | Oct 12 01:13:21 AM UTC 24 | Oct 12 01:13:41 AM UTC 24 | 419876228 ps | ||
| T431 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1563587946 | Oct 12 01:12:52 AM UTC 24 | Oct 12 01:13:44 AM UTC 24 | 6292655499 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2517840141 | Oct 12 01:12:54 AM UTC 24 | Oct 12 01:13:45 AM UTC 24 | 865154408 ps | ||
| T432 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3218490980 | Oct 12 01:13:40 AM UTC 24 | Oct 12 01:13:47 AM UTC 24 | 170871660 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2130805284 | Oct 12 01:13:41 AM UTC 24 | Oct 12 01:13:47 AM UTC 24 | 602684637 ps | ||
| T433 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2506938944 | Oct 12 01:13:41 AM UTC 24 | Oct 12 01:13:48 AM UTC 24 | 597966560 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2271424086 | Oct 12 01:12:30 AM UTC 24 | Oct 12 01:13:48 AM UTC 24 | 399862098 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1957914671 | Oct 12 01:13:42 AM UTC 24 | Oct 12 01:13:49 AM UTC 24 | 307597937 ps | ||
| T434 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3347202414 | Oct 12 01:13:41 AM UTC 24 | Oct 12 01:13:49 AM UTC 24 | 213808988 ps | ||
| T435 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.833763117 | Oct 12 01:13:41 AM UTC 24 | Oct 12 01:13:50 AM UTC 24 | 170522677 ps | ||
| T436 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.729801701 | Oct 12 01:13:43 AM UTC 24 | Oct 12 01:13:50 AM UTC 24 | 384654849 ps | ||
| T437 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.657071580 | Oct 12 01:13:41 AM UTC 24 | Oct 12 01:13:50 AM UTC 24 | 205982670 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1455944078 | Oct 12 01:13:40 AM UTC 24 | Oct 12 01:13:50 AM UTC 24 | 537506249 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3316315064 | Oct 12 01:13:42 AM UTC 24 | Oct 12 01:13:51 AM UTC 24 | 1983298612 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1492434865 | Oct 12 01:13:42 AM UTC 24 | Oct 12 01:13:51 AM UTC 24 | 127898728 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3892386682 | Oct 12 01:13:42 AM UTC 24 | Oct 12 01:13:51 AM UTC 24 | 123811648 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1321216301 | Oct 12 01:13:42 AM UTC 24 | Oct 12 01:13:51 AM UTC 24 | 294504378 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2092267727 | Oct 12 01:13:27 AM UTC 24 | Oct 12 01:13:51 AM UTC 24 | 420130143 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3693228704 | Oct 12 01:13:07 AM UTC 24 | Oct 12 01:13:51 AM UTC 24 | 413549285 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2293091153 | Oct 12 01:13:42 AM UTC 24 | Oct 12 01:13:52 AM UTC 24 | 284646193 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1058445300 | Oct 12 01:13:43 AM UTC 24 | Oct 12 01:13:52 AM UTC 24 | 2630532876 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1683412043 | Oct 12 01:13:24 AM UTC 24 | Oct 12 01:13:56 AM UTC 24 | 583365101 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1123427068 | Oct 12 01:13:17 AM UTC 24 | Oct 12 01:13:57 AM UTC 24 | 1617455921 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1224897783 | Oct 12 01:13:13 AM UTC 24 | Oct 12 01:13:58 AM UTC 24 | 1177143929 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.99305664 | Oct 12 01:13:21 AM UTC 24 | Oct 12 01:14:03 AM UTC 24 | 283600059 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3003427946 | Oct 12 01:12:47 AM UTC 24 | Oct 12 01:14:06 AM UTC 24 | 591612720 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2067070744 | Oct 12 01:13:30 AM UTC 24 | Oct 12 01:14:07 AM UTC 24 | 3179320377 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4166010475 | Oct 12 01:13:25 AM UTC 24 | Oct 12 01:14:09 AM UTC 24 | 264993072 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2689019489 | Oct 12 01:12:57 AM UTC 24 | Oct 12 01:14:12 AM UTC 24 | 1177789294 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4101756023 | Oct 12 01:13:41 AM UTC 24 | Oct 12 01:14:15 AM UTC 24 | 1637695887 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3545980414 | Oct 12 01:13:42 AM UTC 24 | Oct 12 01:14:17 AM UTC 24 | 838028442 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4024303866 | Oct 12 01:13:04 AM UTC 24 | Oct 12 01:14:18 AM UTC 24 | 2232893768 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2263796799 | Oct 12 01:12:59 AM UTC 24 | Oct 12 01:14:22 AM UTC 24 | 328945785 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3769280786 | Oct 12 01:13:42 AM UTC 24 | Oct 12 01:14:24 AM UTC 24 | 649733378 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3764371761 | Oct 12 01:13:42 AM UTC 24 | Oct 12 01:14:27 AM UTC 24 | 7861132535 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.97584445 | Oct 12 01:13:11 AM UTC 24 | Oct 12 01:14:30 AM UTC 24 | 1172796174 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2823349797 | Oct 12 01:13:42 AM UTC 24 | Oct 12 01:14:33 AM UTC 24 | 1183570290 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4083591427 | Oct 12 01:13:29 AM UTC 24 | Oct 12 01:14:42 AM UTC 24 | 602472300 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.954364428 | Oct 12 01:13:18 AM UTC 24 | Oct 12 01:14:51 AM UTC 24 | 687759440 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2863108961 | Oct 12 01:13:40 AM UTC 24 | Oct 12 01:14:56 AM UTC 24 | 2479782773 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1797601239 | Oct 12 01:13:41 AM UTC 24 | Oct 12 01:15:06 AM UTC 24 | 1050966963 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.959927287 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 230778189 ps |
| CPU time | 8.74 seconds |
| Started | Oct 12 01:07:43 AM UTC 24 |
| Finished | Oct 12 01:07:53 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959927287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32k B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.959927287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.4211494848 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 8861464163 ps |
| CPU time | 128.97 seconds |
| Started | Oct 12 01:08:20 AM UTC 24 |
| Finished | Oct 12 01:10:31 AM UTC 24 |
| Peak memory | 232860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4211494848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.rom_ctrl_stress_all_with_rand_reset.4211494848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4113696502 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3493484370 ps |
| CPU time | 78 seconds |
| Started | Oct 12 01:07:45 AM UTC 24 |
| Finished | Oct 12 01:09:04 AM UTC 24 |
| Peak memory | 223848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113696502 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.4113696502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.337481268 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1676665133 ps |
| CPU time | 18.57 seconds |
| Started | Oct 12 01:07:46 AM UTC 24 |
| Finished | Oct 12 01:08:06 AM UTC 24 |
| Peak memory | 227392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337481268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.337481268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.936477263 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 892549853 ps |
| CPU time | 23.92 seconds |
| Started | Oct 12 01:07:54 AM UTC 24 |
| Finished | Oct 12 01:08:19 AM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936477263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.936477263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.4205657331 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 188385435 ps |
| CPU time | 6.17 seconds |
| Started | Oct 12 01:07:46 AM UTC 24 |
| Finished | Oct 12 01:07:53 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205657331 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4205657331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2271424086 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 399862098 ps |
| CPU time | 75.85 seconds |
| Started | Oct 12 01:12:30 AM UTC 24 |
| Finished | Oct 12 01:13:48 AM UTC 24 |
| Peak memory | 222056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271424086 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.2271424086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3261604608 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1037622991 ps |
| CPU time | 12.41 seconds |
| Started | Oct 12 01:07:50 AM UTC 24 |
| Finished | Oct 12 01:08:04 AM UTC 24 |
| Peak memory | 223456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261604608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3261604608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.761997025 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 13166614307 ps |
| CPU time | 100.68 seconds |
| Started | Oct 12 01:07:45 AM UTC 24 |
| Finished | Oct 12 01:09:28 AM UTC 24 |
| Peak memory | 234908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=761997025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.rom_ctrl_stress_all_with_rand_reset.761997025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2320333352 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 239146238 ps |
| CPU time | 15.9 seconds |
| Started | Oct 12 01:07:43 AM UTC 24 |
| Finished | Oct 12 01:08:01 AM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232033335 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.2320333352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.3853097240 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 290577197 ps |
| CPU time | 63.03 seconds |
| Started | Oct 12 01:07:51 AM UTC 24 |
| Finished | Oct 12 01:08:55 AM UTC 24 |
| Peak memory | 258784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853097240 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3853097240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.15941026 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 301727189 ps |
| CPU time | 9.13 seconds |
| Started | Oct 12 01:08:02 AM UTC 24 |
| Finished | Oct 12 01:08:12 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15941026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.15941026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4174076738 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1115646416 ps |
| CPU time | 59.31 seconds |
| Started | Oct 12 01:07:49 AM UTC 24 |
| Finished | Oct 12 01:08:50 AM UTC 24 |
| Peak memory | 254284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174076738 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.4174076738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4290877145 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 895859588 ps |
| CPU time | 37.47 seconds |
| Started | Oct 12 01:12:13 AM UTC 24 |
| Finished | Oct 12 01:12:51 AM UTC 24 |
| Peak memory | 220096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290877145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.4290877145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4166010475 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 264993072 ps |
| CPU time | 41.94 seconds |
| Started | Oct 12 01:13:25 AM UTC 24 |
| Finished | Oct 12 01:14:09 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166010475 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.4166010475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.49581866 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 574973573 ps |
| CPU time | 12.06 seconds |
| Started | Oct 12 01:07:45 AM UTC 24 |
| Finished | Oct 12 01:07:58 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49581866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_ TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.49581866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.394632454 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1032062188 ps |
| CPU time | 11.6 seconds |
| Started | Oct 12 01:08:32 AM UTC 24 |
| Finished | Oct 12 01:08:45 AM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394632454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.394632454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.97584445 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1172796174 ps |
| CPU time | 78 seconds |
| Started | Oct 12 01:13:11 AM UTC 24 |
| Finished | Oct 12 01:14:30 AM UTC 24 |
| Peak memory | 222392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97584445 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.97584445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2263796799 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 328945785 ps |
| CPU time | 80.98 seconds |
| Started | Oct 12 01:12:59 AM UTC 24 |
| Finished | Oct 12 01:14:22 AM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263796799 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.2263796799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3923010059 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2256006104 ps |
| CPU time | 90.42 seconds |
| Started | Oct 12 01:09:59 AM UTC 24 |
| Finished | Oct 12 01:11:31 AM UTC 24 |
| Peak memory | 232852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3923010059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3923010059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2225491147 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 599221904 ps |
| CPU time | 27.83 seconds |
| Started | Oct 12 01:13:12 AM UTC 24 |
| Finished | Oct 12 01:13:41 AM UTC 24 |
| Peak memory | 220100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225491147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.2225491147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.610163050 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 214149404 ps |
| CPU time | 8.35 seconds |
| Started | Oct 12 01:12:18 AM UTC 24 |
| Finished | Oct 12 01:12:28 AM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610163050 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.610163050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1695329646 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 499934545 ps |
| CPU time | 7.53 seconds |
| Started | Oct 12 01:08:43 AM UTC 24 |
| Finished | Oct 12 01:08:52 AM UTC 24 |
| Peak memory | 223596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695329646 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1695329646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.543299419 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1121977766 ps |
| CPU time | 10.38 seconds |
| Started | Oct 12 01:08:53 AM UTC 24 |
| Finished | Oct 12 01:09:05 AM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543299419 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.543299419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.152154305 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1370239581 ps |
| CPU time | 7.99 seconds |
| Started | Oct 12 01:10:28 AM UTC 24 |
| Finished | Oct 12 01:10:37 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152154305 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.152154305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1285801982 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 5635000665 ps |
| CPU time | 90.72 seconds |
| Started | Oct 12 01:08:43 AM UTC 24 |
| Finished | Oct 12 01:10:16 AM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1285801982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1285801982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2851049066 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1014855638 ps |
| CPU time | 12.18 seconds |
| Started | Oct 12 01:07:48 AM UTC 24 |
| Finished | Oct 12 01:08:01 AM UTC 24 |
| Peak memory | 223456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851049066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2851049066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.670418532 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 172385520 ps |
| CPU time | 7.67 seconds |
| Started | Oct 12 01:12:17 AM UTC 24 |
| Finished | Oct 12 01:12:26 AM UTC 24 |
| Peak memory | 220400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670418532 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.670418532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.54088652 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 171774435 ps |
| CPU time | 9.08 seconds |
| Started | Oct 12 01:12:17 AM UTC 24 |
| Finished | Oct 12 01:12:27 AM UTC 24 |
| Peak memory | 227712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54088652 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.54088652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3163454086 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 932546428 ps |
| CPU time | 6.97 seconds |
| Started | Oct 12 01:12:21 AM UTC 24 |
| Finished | Oct 12 01:12:29 AM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3163454086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r om_ctrl_csr_mem_rw_with_rand_reset.3163454086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.411454162 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1578143176 ps |
| CPU time | 7.3 seconds |
| Started | Oct 12 01:12:17 AM UTC 24 |
| Finished | Oct 12 01:12:26 AM UTC 24 |
| Peak memory | 220084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411454162 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.411454162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.875533096 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 385021767 ps |
| CPU time | 6.6 seconds |
| Started | Oct 12 01:12:16 AM UTC 24 |
| Finished | Oct 12 01:12:24 AM UTC 24 |
| Peak memory | 220024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875533096 -assert nopostpr oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.875533096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2247408565 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1693086795 ps |
| CPU time | 6.31 seconds |
| Started | Oct 12 01:12:15 AM UTC 24 |
| Finished | Oct 12 01:12:23 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247408565 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.2247408565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.120939713 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 123531659 ps |
| CPU time | 7.15 seconds |
| Started | Oct 12 01:12:18 AM UTC 24 |
| Finished | Oct 12 01:12:27 AM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120939713 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.120939713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4289415276 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 299789080 ps |
| CPU time | 7.99 seconds |
| Started | Oct 12 01:12:14 AM UTC 24 |
| Finished | Oct 12 01:12:23 AM UTC 24 |
| Peak memory | 227520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289415276 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4289415276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.865702628 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 552269284 ps |
| CPU time | 61.85 seconds |
| Started | Oct 12 01:12:15 AM UTC 24 |
| Finished | Oct 12 01:13:19 AM UTC 24 |
| Peak memory | 222052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865702628 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.865702628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3463296726 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 203412444 ps |
| CPU time | 6.25 seconds |
| Started | Oct 12 01:12:28 AM UTC 24 |
| Finished | Oct 12 01:12:35 AM UTC 24 |
| Peak memory | 220136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463296726 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.3463296726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1884257734 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 452232098 ps |
| CPU time | 8.01 seconds |
| Started | Oct 12 01:12:27 AM UTC 24 |
| Finished | Oct 12 01:12:36 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884257734 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.1884257734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.459300562 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 562494366 ps |
| CPU time | 8.23 seconds |
| Started | Oct 12 01:12:27 AM UTC 24 |
| Finished | Oct 12 01:12:36 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459300562 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.459300562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1702486231 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 269353328 ps |
| CPU time | 8.27 seconds |
| Started | Oct 12 01:12:28 AM UTC 24 |
| Finished | Oct 12 01:12:38 AM UTC 24 |
| Peak memory | 227508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1702486231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r om_ctrl_csr_mem_rw_with_rand_reset.1702486231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1641254912 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 209978761 ps |
| CPU time | 4.65 seconds |
| Started | Oct 12 01:12:27 AM UTC 24 |
| Finished | Oct 12 01:12:33 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641254912 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1641254912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3739197861 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 162541951 ps |
| CPU time | 6.61 seconds |
| Started | Oct 12 01:12:25 AM UTC 24 |
| Finished | Oct 12 01:12:32 AM UTC 24 |
| Peak memory | 220016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739197861 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.3739197861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1122499078 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 171223374 ps |
| CPU time | 8.69 seconds |
| Started | Oct 12 01:12:25 AM UTC 24 |
| Finished | Oct 12 01:12:34 AM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122499078 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.1122499078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2649503733 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 7153797642 ps |
| CPU time | 37.09 seconds |
| Started | Oct 12 01:12:23 AM UTC 24 |
| Finished | Oct 12 01:13:02 AM UTC 24 |
| Peak memory | 220480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649503733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.2649503733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2801399710 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 534568966 ps |
| CPU time | 7.56 seconds |
| Started | Oct 12 01:12:28 AM UTC 24 |
| Finished | Oct 12 01:12:37 AM UTC 24 |
| Peak memory | 227452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801399710 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.2801399710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2194081108 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 1938972749 ps |
| CPU time | 17.04 seconds |
| Started | Oct 12 01:12:23 AM UTC 24 |
| Finished | Oct 12 01:12:42 AM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194081108 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2194081108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3839287048 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 435414369 ps |
| CPU time | 53.09 seconds |
| Started | Oct 12 01:12:24 AM UTC 24 |
| Finished | Oct 12 01:13:18 AM UTC 24 |
| Peak memory | 222128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839287048 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.3839287048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1397611279 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 134055908 ps |
| CPU time | 8.62 seconds |
| Started | Oct 12 01:13:12 AM UTC 24 |
| Finished | Oct 12 01:13:22 AM UTC 24 |
| Peak memory | 227672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1397611279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. rom_ctrl_csr_mem_rw_with_rand_reset.1397611279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3110650221 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 213491648 ps |
| CPU time | 4.59 seconds |
| Started | Oct 12 01:13:11 AM UTC 24 |
| Finished | Oct 12 01:13:16 AM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110650221 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3110650221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4242414211 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 595828447 ps |
| CPU time | 29.27 seconds |
| Started | Oct 12 01:13:09 AM UTC 24 |
| Finished | Oct 12 01:13:39 AM UTC 24 |
| Peak memory | 220356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242414211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.4242414211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2322990977 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 209880038 ps |
| CPU time | 6.06 seconds |
| Started | Oct 12 01:13:11 AM UTC 24 |
| Finished | Oct 12 01:13:18 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322990977 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.2322990977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2466148757 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 370763209 ps |
| CPU time | 9.97 seconds |
| Started | Oct 12 01:13:10 AM UTC 24 |
| Finished | Oct 12 01:13:21 AM UTC 24 |
| Peak memory | 226564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466148757 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2466148757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.804476347 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2127329709 ps |
| CPU time | 8.22 seconds |
| Started | Oct 12 01:13:16 AM UTC 24 |
| Finished | Oct 12 01:13:26 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=804476347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.r om_ctrl_csr_mem_rw_with_rand_reset.804476347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3380017909 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 385728994 ps |
| CPU time | 5.03 seconds |
| Started | Oct 12 01:13:14 AM UTC 24 |
| Finished | Oct 12 01:13:20 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380017909 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3380017909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3286267976 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2780324616 ps |
| CPU time | 8.13 seconds |
| Started | Oct 12 01:13:14 AM UTC 24 |
| Finished | Oct 12 01:13:24 AM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286267976 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.3286267976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2645145297 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 372520414 ps |
| CPU time | 9.51 seconds |
| Started | Oct 12 01:13:12 AM UTC 24 |
| Finished | Oct 12 01:13:23 AM UTC 24 |
| Peak memory | 226564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645145297 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2645145297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1224897783 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1177143929 ps |
| CPU time | 43.53 seconds |
| Started | Oct 12 01:13:13 AM UTC 24 |
| Finished | Oct 12 01:13:58 AM UTC 24 |
| Peak memory | 222200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224897783 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.1224897783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.572340516 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 958968017 ps |
| CPU time | 7.89 seconds |
| Started | Oct 12 01:13:20 AM UTC 24 |
| Finished | Oct 12 01:13:29 AM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=572340516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.r om_ctrl_csr_mem_rw_with_rand_reset.572340516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3527440009 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 206388979 ps |
| CPU time | 5.48 seconds |
| Started | Oct 12 01:13:20 AM UTC 24 |
| Finished | Oct 12 01:13:26 AM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527440009 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3527440009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1123427068 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1617455921 ps |
| CPU time | 38.4 seconds |
| Started | Oct 12 01:13:17 AM UTC 24 |
| Finished | Oct 12 01:13:57 AM UTC 24 |
| Peak memory | 220100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123427068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.1123427068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2674901949 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 558451794 ps |
| CPU time | 6.13 seconds |
| Started | Oct 12 01:13:20 AM UTC 24 |
| Finished | Oct 12 01:13:27 AM UTC 24 |
| Peak memory | 226988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674901949 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.2674901949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1459862846 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 291584151 ps |
| CPU time | 7.15 seconds |
| Started | Oct 12 01:13:17 AM UTC 24 |
| Finished | Oct 12 01:13:26 AM UTC 24 |
| Peak memory | 227792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459862846 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1459862846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.954364428 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 687759440 ps |
| CPU time | 90.13 seconds |
| Started | Oct 12 01:13:18 AM UTC 24 |
| Finished | Oct 12 01:14:51 AM UTC 24 |
| Peak memory | 222128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954364428 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.954364428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.258604220 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 615231581 ps |
| CPU time | 6.59 seconds |
| Started | Oct 12 01:13:23 AM UTC 24 |
| Finished | Oct 12 01:13:31 AM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=258604220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.r om_ctrl_csr_mem_rw_with_rand_reset.258604220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3804222278 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2096628680 ps |
| CPU time | 5.5 seconds |
| Started | Oct 12 01:13:22 AM UTC 24 |
| Finished | Oct 12 01:13:29 AM UTC 24 |
| Peak memory | 227768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804222278 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3804222278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.6523576 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 419876228 ps |
| CPU time | 19.26 seconds |
| Started | Oct 12 01:13:21 AM UTC 24 |
| Finished | Oct 12 01:13:41 AM UTC 24 |
| Peak memory | 220352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6523576 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.6523576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1135702259 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 371206040 ps |
| CPU time | 6.42 seconds |
| Started | Oct 12 01:13:22 AM UTC 24 |
| Finished | Oct 12 01:13:30 AM UTC 24 |
| Peak memory | 227452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135702259 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.1135702259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3292694197 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 555872715 ps |
| CPU time | 9.33 seconds |
| Started | Oct 12 01:13:21 AM UTC 24 |
| Finished | Oct 12 01:13:31 AM UTC 24 |
| Peak memory | 226628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292694197 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3292694197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.99305664 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 283600059 ps |
| CPU time | 40.28 seconds |
| Started | Oct 12 01:13:21 AM UTC 24 |
| Finished | Oct 12 01:14:03 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99305664 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.99305664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2307130689 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 442436371 ps |
| CPU time | 6.46 seconds |
| Started | Oct 12 01:13:27 AM UTC 24 |
| Finished | Oct 12 01:13:34 AM UTC 24 |
| Peak memory | 227736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2307130689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. rom_ctrl_csr_mem_rw_with_rand_reset.2307130689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3084685812 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 604173084 ps |
| CPU time | 6.44 seconds |
| Started | Oct 12 01:13:27 AM UTC 24 |
| Finished | Oct 12 01:13:34 AM UTC 24 |
| Peak memory | 227576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084685812 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3084685812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1683412043 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 583365101 ps |
| CPU time | 30.38 seconds |
| Started | Oct 12 01:13:24 AM UTC 24 |
| Finished | Oct 12 01:13:56 AM UTC 24 |
| Peak memory | 220100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683412043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.1683412043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3917140420 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2095498991 ps |
| CPU time | 5.02 seconds |
| Started | Oct 12 01:13:27 AM UTC 24 |
| Finished | Oct 12 01:13:33 AM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917140420 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.3917140420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.620514046 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 194175450 ps |
| CPU time | 9.5 seconds |
| Started | Oct 12 01:13:25 AM UTC 24 |
| Finished | Oct 12 01:13:36 AM UTC 24 |
| Peak memory | 224512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620514046 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.620514046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3061846871 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 445817705 ps |
| CPU time | 7.83 seconds |
| Started | Oct 12 01:13:30 AM UTC 24 |
| Finished | Oct 12 01:13:39 AM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3061846871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. rom_ctrl_csr_mem_rw_with_rand_reset.3061846871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3555651700 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 367664354 ps |
| CPU time | 6.62 seconds |
| Started | Oct 12 01:13:29 AM UTC 24 |
| Finished | Oct 12 01:13:37 AM UTC 24 |
| Peak memory | 227444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555651700 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3555651700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2092267727 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 420130143 ps |
| CPU time | 22.93 seconds |
| Started | Oct 12 01:13:27 AM UTC 24 |
| Finished | Oct 12 01:13:51 AM UTC 24 |
| Peak memory | 220100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092267727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.2092267727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3832906535 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 168292659 ps |
| CPU time | 7.69 seconds |
| Started | Oct 12 01:13:30 AM UTC 24 |
| Finished | Oct 12 01:13:39 AM UTC 24 |
| Peak memory | 227452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832906535 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.3832906535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3783669021 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 385879703 ps |
| CPU time | 7.59 seconds |
| Started | Oct 12 01:13:28 AM UTC 24 |
| Finished | Oct 12 01:13:37 AM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783669021 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3783669021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4083591427 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 602472300 ps |
| CPU time | 70.92 seconds |
| Started | Oct 12 01:13:29 AM UTC 24 |
| Finished | Oct 12 01:14:42 AM UTC 24 |
| Peak memory | 222132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083591427 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.4083591427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2506938944 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 597966560 ps |
| CPU time | 5.7 seconds |
| Started | Oct 12 01:13:41 AM UTC 24 |
| Finished | Oct 12 01:13:48 AM UTC 24 |
| Peak memory | 227504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2506938944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. rom_ctrl_csr_mem_rw_with_rand_reset.2506938944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3218490980 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 170871660 ps |
| CPU time | 5.64 seconds |
| Started | Oct 12 01:13:40 AM UTC 24 |
| Finished | Oct 12 01:13:47 AM UTC 24 |
| Peak memory | 227448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218490980 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3218490980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2067070744 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 3179320377 ps |
| CPU time | 35.25 seconds |
| Started | Oct 12 01:13:30 AM UTC 24 |
| Finished | Oct 12 01:14:07 AM UTC 24 |
| Peak memory | 220228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067070744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.2067070744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1455944078 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 537506249 ps |
| CPU time | 9.13 seconds |
| Started | Oct 12 01:13:40 AM UTC 24 |
| Finished | Oct 12 01:13:50 AM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455944078 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.1455944078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.509426944 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1692301490 ps |
| CPU time | 6.42 seconds |
| Started | Oct 12 01:13:31 AM UTC 24 |
| Finished | Oct 12 01:13:39 AM UTC 24 |
| Peak memory | 224256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509426944 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.509426944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2863108961 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2479782773 ps |
| CPU time | 74.31 seconds |
| Started | Oct 12 01:13:40 AM UTC 24 |
| Finished | Oct 12 01:14:56 AM UTC 24 |
| Peak memory | 227820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863108961 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.2863108961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3347202414 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 213808988 ps |
| CPU time | 6.81 seconds |
| Started | Oct 12 01:13:41 AM UTC 24 |
| Finished | Oct 12 01:13:49 AM UTC 24 |
| Peak memory | 222372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3347202414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. rom_ctrl_csr_mem_rw_with_rand_reset.3347202414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2130805284 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 602684637 ps |
| CPU time | 5.06 seconds |
| Started | Oct 12 01:13:41 AM UTC 24 |
| Finished | Oct 12 01:13:47 AM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130805284 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2130805284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4101756023 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 1637695887 ps |
| CPU time | 32.72 seconds |
| Started | Oct 12 01:13:41 AM UTC 24 |
| Finished | Oct 12 01:14:15 AM UTC 24 |
| Peak memory | 220100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101756023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.4101756023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.833763117 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 170522677 ps |
| CPU time | 7.06 seconds |
| Started | Oct 12 01:13:41 AM UTC 24 |
| Finished | Oct 12 01:13:50 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833763117 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.833763117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.657071580 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 205982670 ps |
| CPU time | 7.52 seconds |
| Started | Oct 12 01:13:41 AM UTC 24 |
| Finished | Oct 12 01:13:50 AM UTC 24 |
| Peak memory | 226560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657071580 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.657071580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1797601239 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1050966963 ps |
| CPU time | 82.66 seconds |
| Started | Oct 12 01:13:41 AM UTC 24 |
| Finished | Oct 12 01:15:06 AM UTC 24 |
| Peak memory | 227460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797601239 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.1797601239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2293091153 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 284646193 ps |
| CPU time | 8.68 seconds |
| Started | Oct 12 01:13:42 AM UTC 24 |
| Finished | Oct 12 01:13:52 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2293091153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. rom_ctrl_csr_mem_rw_with_rand_reset.2293091153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1957914671 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 307597937 ps |
| CPU time | 5.86 seconds |
| Started | Oct 12 01:13:42 AM UTC 24 |
| Finished | Oct 12 01:13:49 AM UTC 24 |
| Peak memory | 220020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957914671 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1957914671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3764371761 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 7861132535 ps |
| CPU time | 44.11 seconds |
| Started | Oct 12 01:13:42 AM UTC 24 |
| Finished | Oct 12 01:14:27 AM UTC 24 |
| Peak memory | 220228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764371761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.3764371761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3316315064 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1983298612 ps |
| CPU time | 7.93 seconds |
| Started | Oct 12 01:13:42 AM UTC 24 |
| Finished | Oct 12 01:13:51 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316315064 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.3316315064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3892386682 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 123811648 ps |
| CPU time | 8.24 seconds |
| Started | Oct 12 01:13:42 AM UTC 24 |
| Finished | Oct 12 01:13:51 AM UTC 24 |
| Peak memory | 224260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892386682 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3892386682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3769280786 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 649733378 ps |
| CPU time | 41.31 seconds |
| Started | Oct 12 01:13:42 AM UTC 24 |
| Finished | Oct 12 01:14:24 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769280786 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.3769280786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1058445300 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2630532876 ps |
| CPU time | 7.82 seconds |
| Started | Oct 12 01:13:43 AM UTC 24 |
| Finished | Oct 12 01:13:52 AM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1058445300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. rom_ctrl_csr_mem_rw_with_rand_reset.1058445300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1321216301 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 294504378 ps |
| CPU time | 7.9 seconds |
| Started | Oct 12 01:13:42 AM UTC 24 |
| Finished | Oct 12 01:13:51 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321216301 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1321216301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3545980414 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 838028442 ps |
| CPU time | 33.59 seconds |
| Started | Oct 12 01:13:42 AM UTC 24 |
| Finished | Oct 12 01:14:17 AM UTC 24 |
| Peak memory | 220100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545980414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.3545980414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.729801701 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 384654849 ps |
| CPU time | 5.62 seconds |
| Started | Oct 12 01:13:43 AM UTC 24 |
| Finished | Oct 12 01:13:50 AM UTC 24 |
| Peak memory | 220084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729801701 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.729801701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1492434865 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 127898728 ps |
| CPU time | 7.83 seconds |
| Started | Oct 12 01:13:42 AM UTC 24 |
| Finished | Oct 12 01:13:51 AM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492434865 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1492434865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2823349797 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1183570290 ps |
| CPU time | 49.88 seconds |
| Started | Oct 12 01:13:42 AM UTC 24 |
| Finished | Oct 12 01:14:33 AM UTC 24 |
| Peak memory | 222136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823349797 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.2823349797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4065784547 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 535591060 ps |
| CPU time | 7.94 seconds |
| Started | Oct 12 01:12:37 AM UTC 24 |
| Finished | Oct 12 01:12:46 AM UTC 24 |
| Peak memory | 227444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065784547 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.4065784547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.747729293 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 532775874 ps |
| CPU time | 7.54 seconds |
| Started | Oct 12 01:12:37 AM UTC 24 |
| Finished | Oct 12 01:12:45 AM UTC 24 |
| Peak memory | 227452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747729293 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.747729293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4003116336 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 391523311 ps |
| CPU time | 7.77 seconds |
| Started | Oct 12 01:12:33 AM UTC 24 |
| Finished | Oct 12 01:12:43 AM UTC 24 |
| Peak memory | 227420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003116336 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.4003116336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4128598824 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 139233133 ps |
| CPU time | 6.84 seconds |
| Started | Oct 12 01:12:37 AM UTC 24 |
| Finished | Oct 12 01:12:45 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4128598824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r om_ctrl_csr_mem_rw_with_rand_reset.4128598824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1839603819 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 125215570 ps |
| CPU time | 6.26 seconds |
| Started | Oct 12 01:12:35 AM UTC 24 |
| Finished | Oct 12 01:12:43 AM UTC 24 |
| Peak memory | 220140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839603819 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1839603819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.322758617 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 164101843 ps |
| CPU time | 6.41 seconds |
| Started | Oct 12 01:12:33 AM UTC 24 |
| Finished | Oct 12 01:12:41 AM UTC 24 |
| Peak memory | 220024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322758617 -assert nopostpr oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.322758617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.764468626 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 124417873 ps |
| CPU time | 5.25 seconds |
| Started | Oct 12 01:12:33 AM UTC 24 |
| Finished | Oct 12 01:12:40 AM UTC 24 |
| Peak memory | 220016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764468626 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.764468626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1572418776 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 840608003 ps |
| CPU time | 32.03 seconds |
| Started | Oct 12 01:12:29 AM UTC 24 |
| Finished | Oct 12 01:13:03 AM UTC 24 |
| Peak memory | 220088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572418776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.1572418776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4110633451 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 127090045 ps |
| CPU time | 7.41 seconds |
| Started | Oct 12 01:12:37 AM UTC 24 |
| Finished | Oct 12 01:12:45 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110633451 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.4110633451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1403714801 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 552999273 ps |
| CPU time | 9.49 seconds |
| Started | Oct 12 01:12:29 AM UTC 24 |
| Finished | Oct 12 01:12:40 AM UTC 24 |
| Peak memory | 227520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403714801 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1403714801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.825444002 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 305401025 ps |
| CPU time | 7.41 seconds |
| Started | Oct 12 01:12:42 AM UTC 24 |
| Finished | Oct 12 01:12:51 AM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825444002 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.825444002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1851422945 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 5489821327 ps |
| CPU time | 10.16 seconds |
| Started | Oct 12 01:12:42 AM UTC 24 |
| Finished | Oct 12 01:12:54 AM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851422945 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.1851422945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3074701107 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 461997690 ps |
| CPU time | 11.28 seconds |
| Started | Oct 12 01:12:41 AM UTC 24 |
| Finished | Oct 12 01:12:54 AM UTC 24 |
| Peak memory | 227444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074701107 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.3074701107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.849875564 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 493354605 ps |
| CPU time | 7.57 seconds |
| Started | Oct 12 01:12:44 AM UTC 24 |
| Finished | Oct 12 01:12:52 AM UTC 24 |
| Peak memory | 227768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=849875564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.ro m_ctrl_csr_mem_rw_with_rand_reset.849875564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3216111660 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 555415139 ps |
| CPU time | 7.17 seconds |
| Started | Oct 12 01:12:41 AM UTC 24 |
| Finished | Oct 12 01:12:50 AM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216111660 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3216111660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3038186759 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 125525461 ps |
| CPU time | 4.93 seconds |
| Started | Oct 12 01:12:41 AM UTC 24 |
| Finished | Oct 12 01:12:47 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038186759 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.3038186759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1795980756 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 1414114799 ps |
| CPU time | 5.06 seconds |
| Started | Oct 12 01:12:41 AM UTC 24 |
| Finished | Oct 12 01:12:47 AM UTC 24 |
| Peak memory | 220016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795980756 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.1795980756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2915157915 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1163946458 ps |
| CPU time | 31.65 seconds |
| Started | Oct 12 01:12:38 AM UTC 24 |
| Finished | Oct 12 01:13:11 AM UTC 24 |
| Peak memory | 220416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915157915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.2915157915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.882761651 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 183436502 ps |
| CPU time | 7.25 seconds |
| Started | Oct 12 01:12:44 AM UTC 24 |
| Finished | Oct 12 01:12:52 AM UTC 24 |
| Peak memory | 227644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882761651 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.882761651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3932817401 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 315828160 ps |
| CPU time | 14.25 seconds |
| Started | Oct 12 01:12:38 AM UTC 24 |
| Finished | Oct 12 01:12:53 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932817401 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3932817401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1716416154 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 510421119 ps |
| CPU time | 44.67 seconds |
| Started | Oct 12 01:12:39 AM UTC 24 |
| Finished | Oct 12 01:13:25 AM UTC 24 |
| Peak memory | 220144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716416154 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.1716416154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2148829475 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 327045785 ps |
| CPU time | 5.87 seconds |
| Started | Oct 12 01:12:50 AM UTC 24 |
| Finished | Oct 12 01:12:57 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148829475 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.2148829475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2855096405 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 173213826 ps |
| CPU time | 6.25 seconds |
| Started | Oct 12 01:12:49 AM UTC 24 |
| Finished | Oct 12 01:12:56 AM UTC 24 |
| Peak memory | 220328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855096405 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.2855096405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3178327868 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 133573870 ps |
| CPU time | 10.46 seconds |
| Started | Oct 12 01:12:48 AM UTC 24 |
| Finished | Oct 12 01:13:00 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178327868 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.3178327868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2836518508 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 300499741 ps |
| CPU time | 6.25 seconds |
| Started | Oct 12 01:12:51 AM UTC 24 |
| Finished | Oct 12 01:12:59 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2836518508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r om_ctrl_csr_mem_rw_with_rand_reset.2836518508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.583342898 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 336677636 ps |
| CPU time | 6.85 seconds |
| Started | Oct 12 01:12:49 AM UTC 24 |
| Finished | Oct 12 01:12:57 AM UTC 24 |
| Peak memory | 220084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583342898 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.583342898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3001963930 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 299646831 ps |
| CPU time | 6.7 seconds |
| Started | Oct 12 01:12:48 AM UTC 24 |
| Finished | Oct 12 01:12:56 AM UTC 24 |
| Peak memory | 220016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001963930 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.3001963930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.828548222 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 140768733 ps |
| CPU time | 5.77 seconds |
| Started | Oct 12 01:12:47 AM UTC 24 |
| Finished | Oct 12 01:12:54 AM UTC 24 |
| Peak memory | 220144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828548222 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.828548222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2611069660 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 848761618 ps |
| CPU time | 46.33 seconds |
| Started | Oct 12 01:12:46 AM UTC 24 |
| Finished | Oct 12 01:13:34 AM UTC 24 |
| Peak memory | 220096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611069660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.2611069660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1768046252 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 293041130 ps |
| CPU time | 7.63 seconds |
| Started | Oct 12 01:12:50 AM UTC 24 |
| Finished | Oct 12 01:12:59 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768046252 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.1768046252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.977265423 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 294579105 ps |
| CPU time | 7.66 seconds |
| Started | Oct 12 01:12:46 AM UTC 24 |
| Finished | Oct 12 01:12:54 AM UTC 24 |
| Peak memory | 224320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977265423 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.977265423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3003427946 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 591612720 ps |
| CPU time | 77.41 seconds |
| Started | Oct 12 01:12:47 AM UTC 24 |
| Finished | Oct 12 01:14:06 AM UTC 24 |
| Peak memory | 222128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003427946 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.3003427946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3958028244 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 398677911 ps |
| CPU time | 6.54 seconds |
| Started | Oct 12 01:12:55 AM UTC 24 |
| Finished | Oct 12 01:13:02 AM UTC 24 |
| Peak memory | 227508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3958028244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r om_ctrl_csr_mem_rw_with_rand_reset.3958028244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.687879623 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 169941702 ps |
| CPU time | 7.96 seconds |
| Started | Oct 12 01:12:55 AM UTC 24 |
| Finished | Oct 12 01:13:04 AM UTC 24 |
| Peak memory | 227716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687879623 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.687879623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1563587946 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 6292655499 ps |
| CPU time | 50.14 seconds |
| Started | Oct 12 01:12:52 AM UTC 24 |
| Finished | Oct 12 01:13:44 AM UTC 24 |
| Peak memory | 220224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563587946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.1563587946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.932701927 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 577603958 ps |
| CPU time | 10.63 seconds |
| Started | Oct 12 01:12:55 AM UTC 24 |
| Finished | Oct 12 01:13:06 AM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932701927 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.932701927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3820862176 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 169874066 ps |
| CPU time | 11.46 seconds |
| Started | Oct 12 01:12:53 AM UTC 24 |
| Finished | Oct 12 01:13:05 AM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820862176 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3820862176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2517840141 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 865154408 ps |
| CPU time | 49.78 seconds |
| Started | Oct 12 01:12:54 AM UTC 24 |
| Finished | Oct 12 01:13:45 AM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517840141 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.2517840141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2332037419 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 329496637 ps |
| CPU time | 7.55 seconds |
| Started | Oct 12 01:12:58 AM UTC 24 |
| Finished | Oct 12 01:13:07 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2332037419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r om_ctrl_csr_mem_rw_with_rand_reset.2332037419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1378988569 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 169729855 ps |
| CPU time | 6.17 seconds |
| Started | Oct 12 01:12:57 AM UTC 24 |
| Finished | Oct 12 01:13:04 AM UTC 24 |
| Peak memory | 219904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378988569 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1378988569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.751337952 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 7866872126 ps |
| CPU time | 44.03 seconds |
| Started | Oct 12 01:12:55 AM UTC 24 |
| Finished | Oct 12 01:13:40 AM UTC 24 |
| Peak memory | 220232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751337952 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.751337952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.709301652 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2512106653 ps |
| CPU time | 7.56 seconds |
| Started | Oct 12 01:12:58 AM UTC 24 |
| Finished | Oct 12 01:13:07 AM UTC 24 |
| Peak memory | 227836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709301652 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.709301652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2007769834 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 653336717 ps |
| CPU time | 10.06 seconds |
| Started | Oct 12 01:12:56 AM UTC 24 |
| Finished | Oct 12 01:13:07 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007769834 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2007769834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2689019489 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1177789294 ps |
| CPU time | 73.65 seconds |
| Started | Oct 12 01:12:57 AM UTC 24 |
| Finished | Oct 12 01:14:12 AM UTC 24 |
| Peak memory | 222008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689019489 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.2689019489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4162655811 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 425814519 ps |
| CPU time | 5.17 seconds |
| Started | Oct 12 01:13:01 AM UTC 24 |
| Finished | Oct 12 01:13:07 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4162655811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r om_ctrl_csr_mem_rw_with_rand_reset.4162655811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1595727379 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 126957449 ps |
| CPU time | 6.76 seconds |
| Started | Oct 12 01:13:00 AM UTC 24 |
| Finished | Oct 12 01:13:08 AM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595727379 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1595727379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.500920674 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2144453797 ps |
| CPU time | 23.47 seconds |
| Started | Oct 12 01:12:59 AM UTC 24 |
| Finished | Oct 12 01:13:24 AM UTC 24 |
| Peak memory | 219988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500920674 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.500920674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1739904483 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 302972862 ps |
| CPU time | 8.21 seconds |
| Started | Oct 12 01:13:01 AM UTC 24 |
| Finished | Oct 12 01:13:10 AM UTC 24 |
| Peak memory | 227452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739904483 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.1739904483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2245461693 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 299342938 ps |
| CPU time | 9.82 seconds |
| Started | Oct 12 01:12:59 AM UTC 24 |
| Finished | Oct 12 01:13:10 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245461693 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2245461693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4287053201 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 336491513 ps |
| CPU time | 7.46 seconds |
| Started | Oct 12 01:13:05 AM UTC 24 |
| Finished | Oct 12 01:13:14 AM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4287053201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r om_ctrl_csr_mem_rw_with_rand_reset.4287053201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3129041868 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2092965576 ps |
| CPU time | 4.63 seconds |
| Started | Oct 12 01:13:05 AM UTC 24 |
| Finished | Oct 12 01:13:11 AM UTC 24 |
| Peak memory | 227704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129041868 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3129041868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2395999594 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 7229678935 ps |
| CPU time | 20.14 seconds |
| Started | Oct 12 01:13:03 AM UTC 24 |
| Finished | Oct 12 01:13:24 AM UTC 24 |
| Peak memory | 222528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395999594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.2395999594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.414938766 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 372402548 ps |
| CPU time | 5.17 seconds |
| Started | Oct 12 01:13:05 AM UTC 24 |
| Finished | Oct 12 01:13:11 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414938766 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.414938766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.132429723 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 550938450 ps |
| CPU time | 15.43 seconds |
| Started | Oct 12 01:13:04 AM UTC 24 |
| Finished | Oct 12 01:13:20 AM UTC 24 |
| Peak memory | 227532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132429723 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.132429723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4024303866 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 2232893768 ps |
| CPU time | 72.75 seconds |
| Started | Oct 12 01:13:04 AM UTC 24 |
| Finished | Oct 12 01:14:18 AM UTC 24 |
| Peak memory | 222256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024303866 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.4024303866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2018418324 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 183479553 ps |
| CPU time | 6.21 seconds |
| Started | Oct 12 01:13:08 AM UTC 24 |
| Finished | Oct 12 01:13:16 AM UTC 24 |
| Peak memory | 224232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2018418324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r om_ctrl_csr_mem_rw_with_rand_reset.2018418324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.268320 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 1693833361 ps |
| CPU time | 5.42 seconds |
| Started | Oct 12 01:13:07 AM UTC 24 |
| Finished | Oct 12 01:13:14 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268320 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.268320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2391179261 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2452645191 ps |
| CPU time | 25.35 seconds |
| Started | Oct 12 01:13:05 AM UTC 24 |
| Finished | Oct 12 01:13:32 AM UTC 24 |
| Peak memory | 220224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391179261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.2391179261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3798980784 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 167222823 ps |
| CPU time | 8.13 seconds |
| Started | Oct 12 01:13:07 AM UTC 24 |
| Finished | Oct 12 01:13:17 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798980784 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.3798980784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4253181553 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 294471157 ps |
| CPU time | 10.83 seconds |
| Started | Oct 12 01:13:06 AM UTC 24 |
| Finished | Oct 12 01:13:18 AM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253181553 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.4253181553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3693228704 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 413549285 ps |
| CPU time | 42.86 seconds |
| Started | Oct 12 01:13:07 AM UTC 24 |
| Finished | Oct 12 01:13:51 AM UTC 24 |
| Peak memory | 227428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693228704 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.3693228704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.2377304002 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 132986673 ps |
| CPU time | 8.21 seconds |
| Started | Oct 12 01:07:45 AM UTC 24 |
| Finished | Oct 12 01:07:54 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377304002 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2377304002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2362340920 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 226721227 ps |
| CPU time | 124.57 seconds |
| Started | Oct 12 01:07:46 AM UTC 24 |
| Finished | Oct 12 01:09:53 AM UTC 24 |
| Peak memory | 258792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362340920 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2362340920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3212931169 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 530618702 ps |
| CPU time | 7.47 seconds |
| Started | Oct 12 01:07:48 AM UTC 24 |
| Finished | Oct 12 01:07:56 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212931169 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3212931169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.658197038 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2076217860 ps |
| CPU time | 108.06 seconds |
| Started | Oct 12 01:07:48 AM UTC 24 |
| Finished | Oct 12 01:09:38 AM UTC 24 |
| Peak memory | 246120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658197038 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.658197038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.2070582473 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 419324056 ps |
| CPU time | 6.8 seconds |
| Started | Oct 12 01:07:46 AM UTC 24 |
| Finished | Oct 12 01:07:54 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070582473 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2070582473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.3648347325 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 183272854 ps |
| CPU time | 52.97 seconds |
| Started | Oct 12 01:07:48 AM UTC 24 |
| Finished | Oct 12 01:08:42 AM UTC 24 |
| Peak memory | 258780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648347325 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3648347325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.836445319 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 298056448 ps |
| CPU time | 8.75 seconds |
| Started | Oct 12 01:07:46 AM UTC 24 |
| Finished | Oct 12 01:07:56 AM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836445319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32k B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.836445319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.734931597 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 868513834 ps |
| CPU time | 6.14 seconds |
| Started | Oct 12 01:08:29 AM UTC 24 |
| Finished | Oct 12 01:08:36 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734931597 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.734931597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.693235041 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1193510173 ps |
| CPU time | 71.05 seconds |
| Started | Oct 12 01:08:27 AM UTC 24 |
| Finished | Oct 12 01:09:40 AM UTC 24 |
| Peak memory | 246704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693235041 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.693235041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.988879781 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 212127079 ps |
| CPU time | 14.05 seconds |
| Started | Oct 12 01:08:28 AM UTC 24 |
| Finished | Oct 12 01:08:43 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988879781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.988879781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.2832926373 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 178818970 ps |
| CPU time | 7.79 seconds |
| Started | Oct 12 01:08:25 AM UTC 24 |
| Finished | Oct 12 01:08:34 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832926373 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2832926373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.1251030488 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1070880496 ps |
| CPU time | 13.45 seconds |
| Started | Oct 12 01:08:25 AM UTC 24 |
| Finished | Oct 12 01:08:39 AM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125103048 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.1251030488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1623986266 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9781602964 ps |
| CPU time | 64.45 seconds |
| Started | Oct 12 01:08:28 AM UTC 24 |
| Finished | Oct 12 01:09:34 AM UTC 24 |
| Peak memory | 232852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1623986266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1623986266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.2987838755 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 170474431 ps |
| CPU time | 6.55 seconds |
| Started | Oct 12 01:08:35 AM UTC 24 |
| Finished | Oct 12 01:08:42 AM UTC 24 |
| Peak memory | 223344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987838755 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2987838755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2705771495 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 868805879 ps |
| CPU time | 58.78 seconds |
| Started | Oct 12 01:08:31 AM UTC 24 |
| Finished | Oct 12 01:09:32 AM UTC 24 |
| Peak memory | 258824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705771495 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.2705771495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.70260856 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 474097464 ps |
| CPU time | 8.55 seconds |
| Started | Oct 12 01:08:31 AM UTC 24 |
| Finished | Oct 12 01:08:41 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70260856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.70260856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.1165689294 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 328862050 ps |
| CPU time | 19.18 seconds |
| Started | Oct 12 01:08:30 AM UTC 24 |
| Finished | Oct 12 01:08:51 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116568929 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.1165689294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3917468446 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4861707003 ps |
| CPU time | 375.78 seconds |
| Started | Oct 12 01:08:33 AM UTC 24 |
| Finished | Oct 12 01:14:54 AM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3917468446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3917468446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.2684259201 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 163932496 ps |
| CPU time | 7.13 seconds |
| Started | Oct 12 01:08:38 AM UTC 24 |
| Finished | Oct 12 01:08:46 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684259201 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2684259201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.376124500 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 9203336132 ps |
| CPU time | 117.01 seconds |
| Started | Oct 12 01:08:35 AM UTC 24 |
| Finished | Oct 12 01:10:34 AM UTC 24 |
| Peak memory | 259208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376124500 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.376124500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.1566609357 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 299405522 ps |
| CPU time | 15.83 seconds |
| Started | Oct 12 01:08:37 AM UTC 24 |
| Finished | Oct 12 01:08:54 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566609357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1566609357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.3252489521 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 319778038 ps |
| CPU time | 9.39 seconds |
| Started | Oct 12 01:08:35 AM UTC 24 |
| Finished | Oct 12 01:08:45 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252489521 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3252489521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.2700074298 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 472410194 ps |
| CPU time | 27.75 seconds |
| Started | Oct 12 01:08:35 AM UTC 24 |
| Finished | Oct 12 01:09:04 AM UTC 24 |
| Peak memory | 227736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270007429 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.2700074298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1482824151 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 9195738197 ps |
| CPU time | 199.11 seconds |
| Started | Oct 12 01:08:37 AM UTC 24 |
| Finished | Oct 12 01:11:59 AM UTC 24 |
| Peak memory | 236948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1482824151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.rom_ctrl_stress_all_with_rand_reset.1482824151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2172141632 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 34372662349 ps |
| CPU time | 165.46 seconds |
| Started | Oct 12 01:08:40 AM UTC 24 |
| Finished | Oct 12 01:11:29 AM UTC 24 |
| Peak memory | 246548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172141632 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.2172141632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.3775480740 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 256437249 ps |
| CPU time | 15.08 seconds |
| Started | Oct 12 01:08:41 AM UTC 24 |
| Finished | Oct 12 01:08:58 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775480740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3775480740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.167024177 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 578519647 ps |
| CPU time | 8.44 seconds |
| Started | Oct 12 01:08:40 AM UTC 24 |
| Finished | Oct 12 01:08:50 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167024177 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.167024177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.27364214 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 636252793 ps |
| CPU time | 12.74 seconds |
| Started | Oct 12 01:08:39 AM UTC 24 |
| Finished | Oct 12 01:08:53 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27364214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.27364214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.439090928 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 127010014 ps |
| CPU time | 7.41 seconds |
| Started | Oct 12 01:08:50 AM UTC 24 |
| Finished | Oct 12 01:08:58 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439090928 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.439090928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3824505397 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 9374276607 ps |
| CPU time | 136.69 seconds |
| Started | Oct 12 01:08:46 AM UTC 24 |
| Finished | Oct 12 01:11:05 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824505397 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.3824505397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.3032743605 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 466673952 ps |
| CPU time | 17.02 seconds |
| Started | Oct 12 01:08:47 AM UTC 24 |
| Finished | Oct 12 01:09:05 AM UTC 24 |
| Peak memory | 223428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032743605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3032743605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.2785396656 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1245485447 ps |
| CPU time | 8.44 seconds |
| Started | Oct 12 01:08:46 AM UTC 24 |
| Finished | Oct 12 01:08:55 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785396656 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2785396656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.926322643 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 612816077 ps |
| CPU time | 16.66 seconds |
| Started | Oct 12 01:08:45 AM UTC 24 |
| Finished | Oct 12 01:09:02 AM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926322643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.926322643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.403401398 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2386613719 ps |
| CPU time | 149.76 seconds |
| Started | Oct 12 01:08:51 AM UTC 24 |
| Finished | Oct 12 01:11:24 AM UTC 24 |
| Peak memory | 244016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403401398 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.403401398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.371865805 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1344482683 ps |
| CPU time | 15.51 seconds |
| Started | Oct 12 01:08:53 AM UTC 24 |
| Finished | Oct 12 01:09:10 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371865805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.371865805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3147688106 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1841771495 ps |
| CPU time | 11.49 seconds |
| Started | Oct 12 01:08:51 AM UTC 24 |
| Finished | Oct 12 01:09:04 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147688106 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3147688106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.2703878252 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 383254833 ps |
| CPU time | 11.49 seconds |
| Started | Oct 12 01:08:51 AM UTC 24 |
| Finished | Oct 12 01:09:04 AM UTC 24 |
| Peak memory | 223508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270387825 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.2703878252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1331318041 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4994221169 ps |
| CPU time | 190.97 seconds |
| Started | Oct 12 01:08:53 AM UTC 24 |
| Finished | Oct 12 01:12:07 AM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1331318041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1331318041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.1676989549 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 791320836 ps |
| CPU time | 4.37 seconds |
| Started | Oct 12 01:09:03 AM UTC 24 |
| Finished | Oct 12 01:09:08 AM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676989549 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1676989549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.82041560 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 18260619765 ps |
| CPU time | 177.87 seconds |
| Started | Oct 12 01:08:57 AM UTC 24 |
| Finished | Oct 12 01:11:57 AM UTC 24 |
| Peak memory | 258936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82041560 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.82041560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.2195084313 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 426122982 ps |
| CPU time | 14.86 seconds |
| Started | Oct 12 01:08:59 AM UTC 24 |
| Finished | Oct 12 01:09:15 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195084313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2195084313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.2756764506 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 307824256 ps |
| CPU time | 8.23 seconds |
| Started | Oct 12 01:08:56 AM UTC 24 |
| Finished | Oct 12 01:09:05 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756764506 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2756764506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1032984977 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 652423519 ps |
| CPU time | 27.64 seconds |
| Started | Oct 12 01:08:55 AM UTC 24 |
| Finished | Oct 12 01:09:23 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103298497 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.1032984977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1977659813 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2204398690 ps |
| CPU time | 87.79 seconds |
| Started | Oct 12 01:09:00 AM UTC 24 |
| Finished | Oct 12 01:10:30 AM UTC 24 |
| Peak memory | 233028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1977659813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1977659813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1455012154 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2016969338 ps |
| CPU time | 7.52 seconds |
| Started | Oct 12 01:09:06 AM UTC 24 |
| Finished | Oct 12 01:09:15 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455012154 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1455012154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3955796729 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 9894575366 ps |
| CPU time | 154.27 seconds |
| Started | Oct 12 01:09:05 AM UTC 24 |
| Finished | Oct 12 01:11:43 AM UTC 24 |
| Peak memory | 225920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955796729 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.3955796729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.657331462 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 996577570 ps |
| CPU time | 13.66 seconds |
| Started | Oct 12 01:09:05 AM UTC 24 |
| Finished | Oct 12 01:09:21 AM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657331462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.657331462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.2268206898 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 229741108 ps |
| CPU time | 9.07 seconds |
| Started | Oct 12 01:09:05 AM UTC 24 |
| Finished | Oct 12 01:09:16 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268206898 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2268206898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3752164839 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 306720097 ps |
| CPU time | 13.35 seconds |
| Started | Oct 12 01:09:05 AM UTC 24 |
| Finished | Oct 12 01:09:20 AM UTC 24 |
| Peak memory | 223508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375216483 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.3752164839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.158755853 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 6894982574 ps |
| CPU time | 218.4 seconds |
| Started | Oct 12 01:09:06 AM UTC 24 |
| Finished | Oct 12 01:12:49 AM UTC 24 |
| Peak memory | 235084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=158755853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 17.rom_ctrl_stress_all_with_rand_reset.158755853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.1183853091 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 535036814 ps |
| CPU time | 7.6 seconds |
| Started | Oct 12 01:09:16 AM UTC 24 |
| Finished | Oct 12 01:09:25 AM UTC 24 |
| Peak memory | 223596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183853091 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1183853091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2754326407 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 2128279630 ps |
| CPU time | 122.07 seconds |
| Started | Oct 12 01:09:10 AM UTC 24 |
| Finished | Oct 12 01:11:15 AM UTC 24 |
| Peak memory | 258980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754326407 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.2754326407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.470096732 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 704955198 ps |
| CPU time | 10.75 seconds |
| Started | Oct 12 01:09:15 AM UTC 24 |
| Finished | Oct 12 01:09:27 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470096732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.470096732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.935033641 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 181861132 ps |
| CPU time | 10.99 seconds |
| Started | Oct 12 01:09:09 AM UTC 24 |
| Finished | Oct 12 01:09:22 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935033641 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.935033641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.2649515903 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2638970073 ps |
| CPU time | 19.5 seconds |
| Started | Oct 12 01:09:06 AM UTC 24 |
| Finished | Oct 12 01:09:27 AM UTC 24 |
| Peak memory | 227868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264951590 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.2649515903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.4206310706 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 21734866888 ps |
| CPU time | 65.53 seconds |
| Started | Oct 12 01:09:16 AM UTC 24 |
| Finished | Oct 12 01:10:23 AM UTC 24 |
| Peak memory | 241044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4206310706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.rom_ctrl_stress_all_with_rand_reset.4206310706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.652414662 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 537081946 ps |
| CPU time | 5.9 seconds |
| Started | Oct 12 01:09:23 AM UTC 24 |
| Finished | Oct 12 01:09:30 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652414662 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.652414662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3252729157 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2093013371 ps |
| CPU time | 58.84 seconds |
| Started | Oct 12 01:09:18 AM UTC 24 |
| Finished | Oct 12 01:10:19 AM UTC 24 |
| Peak memory | 255148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252729157 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.3252729157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.2011569591 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 295031113 ps |
| CPU time | 17.13 seconds |
| Started | Oct 12 01:09:21 AM UTC 24 |
| Finished | Oct 12 01:09:40 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011569591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2011569591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.641707284 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 175995371 ps |
| CPU time | 10.89 seconds |
| Started | Oct 12 01:09:17 AM UTC 24 |
| Finished | Oct 12 01:09:29 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641707284 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.641707284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2210880801 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 309567576 ps |
| CPU time | 13.48 seconds |
| Started | Oct 12 01:09:17 AM UTC 24 |
| Finished | Oct 12 01:09:32 AM UTC 24 |
| Peak memory | 223440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221088080 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.2210880801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2472094997 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 14515509827 ps |
| CPU time | 213.69 seconds |
| Started | Oct 12 01:09:21 AM UTC 24 |
| Finished | Oct 12 01:12:58 AM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2472094997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2472094997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.3633744104 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 298914868 ps |
| CPU time | 5.6 seconds |
| Started | Oct 12 01:07:52 AM UTC 24 |
| Finished | Oct 12 01:07:58 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633744104 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3633744104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1088631783 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 132004913 ps |
| CPU time | 8.44 seconds |
| Started | Oct 12 01:07:49 AM UTC 24 |
| Finished | Oct 12 01:07:59 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088631783 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1088631783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.2714828731 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1037667393 ps |
| CPU time | 8.96 seconds |
| Started | Oct 12 01:07:49 AM UTC 24 |
| Finished | Oct 12 01:07:59 AM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714828731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2714828731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.490619637 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 464317571 ps |
| CPU time | 21.72 seconds |
| Started | Oct 12 01:07:49 AM UTC 24 |
| Finished | Oct 12 01:08:12 AM UTC 24 |
| Peak memory | 227816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490619637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.490619637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4141841614 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5067193122 ps |
| CPU time | 92.7 seconds |
| Started | Oct 12 01:07:51 AM UTC 24 |
| Finished | Oct 12 01:09:25 AM UTC 24 |
| Peak memory | 235164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4141841614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.rom_ctrl_stress_all_with_rand_reset.4141841614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.2540466322 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 282989701 ps |
| CPU time | 7.71 seconds |
| Started | Oct 12 01:09:25 AM UTC 24 |
| Finished | Oct 12 01:09:34 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540466322 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2540466322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.903422176 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3665296107 ps |
| CPU time | 167.75 seconds |
| Started | Oct 12 01:09:23 AM UTC 24 |
| Finished | Oct 12 01:12:13 AM UTC 24 |
| Peak memory | 260272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903422176 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.903422176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.811106804 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 289079433 ps |
| CPU time | 11.99 seconds |
| Started | Oct 12 01:09:24 AM UTC 24 |
| Finished | Oct 12 01:09:37 AM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811106804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.811106804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.3450274398 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 677759500 ps |
| CPU time | 9.87 seconds |
| Started | Oct 12 01:09:23 AM UTC 24 |
| Finished | Oct 12 01:09:34 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450274398 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3450274398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.3680156180 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1511229350 ps |
| CPU time | 17.54 seconds |
| Started | Oct 12 01:09:23 AM UTC 24 |
| Finished | Oct 12 01:09:42 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368015618 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.3680156180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1219488217 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1696897670 ps |
| CPU time | 120.78 seconds |
| Started | Oct 12 01:09:25 AM UTC 24 |
| Finished | Oct 12 01:11:28 AM UTC 24 |
| Peak memory | 230932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1219488217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1219488217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.212373876 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 385755744 ps |
| CPU time | 6.13 seconds |
| Started | Oct 12 01:09:29 AM UTC 24 |
| Finished | Oct 12 01:09:36 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212373876 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.212373876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2842711078 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2129371975 ps |
| CPU time | 80.22 seconds |
| Started | Oct 12 01:09:27 AM UTC 24 |
| Finished | Oct 12 01:10:49 AM UTC 24 |
| Peak memory | 259252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842711078 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.2842711078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.3448527699 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 704783934 ps |
| CPU time | 11.41 seconds |
| Started | Oct 12 01:09:29 AM UTC 24 |
| Finished | Oct 12 01:09:41 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448527699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3448527699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.940336471 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2109923251 ps |
| CPU time | 12.56 seconds |
| Started | Oct 12 01:09:27 AM UTC 24 |
| Finished | Oct 12 01:09:41 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940336471 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.940336471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.1059790110 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 320273681 ps |
| CPU time | 18.71 seconds |
| Started | Oct 12 01:09:26 AM UTC 24 |
| Finished | Oct 12 01:09:46 AM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105979011 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.1059790110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.457848337 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1077032283 ps |
| CPU time | 54.94 seconds |
| Started | Oct 12 01:09:29 AM UTC 24 |
| Finished | Oct 12 01:10:25 AM UTC 24 |
| Peak memory | 232988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=457848337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 21.rom_ctrl_stress_all_with_rand_reset.457848337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3317847344 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 125094957 ps |
| CPU time | 7.92 seconds |
| Started | Oct 12 01:09:35 AM UTC 24 |
| Finished | Oct 12 01:09:44 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317847344 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3317847344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1742548648 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3096300062 ps |
| CPU time | 151.69 seconds |
| Started | Oct 12 01:09:33 AM UTC 24 |
| Finished | Oct 12 01:12:07 AM UTC 24 |
| Peak memory | 259316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742548648 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.1742548648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.509788816 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 297997566 ps |
| CPU time | 12.43 seconds |
| Started | Oct 12 01:09:33 AM UTC 24 |
| Finished | Oct 12 01:09:47 AM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509788816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.509788816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.271981877 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 429867923 ps |
| CPU time | 8.52 seconds |
| Started | Oct 12 01:09:31 AM UTC 24 |
| Finished | Oct 12 01:09:40 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271981877 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.271981877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2950509059 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1476445318 ps |
| CPU time | 13.43 seconds |
| Started | Oct 12 01:09:30 AM UTC 24 |
| Finished | Oct 12 01:09:44 AM UTC 24 |
| Peak memory | 223572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295050905 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.2950509059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.4254049246 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1553358543 ps |
| CPU time | 60.23 seconds |
| Started | Oct 12 01:09:35 AM UTC 24 |
| Finished | Oct 12 01:10:37 AM UTC 24 |
| Peak memory | 232788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4254049246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 22.rom_ctrl_stress_all_with_rand_reset.4254049246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.4001902657 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 169703038 ps |
| CPU time | 8.08 seconds |
| Started | Oct 12 01:09:41 AM UTC 24 |
| Finished | Oct 12 01:09:50 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001902657 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.4001902657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4227951491 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2442540607 ps |
| CPU time | 166.84 seconds |
| Started | Oct 12 01:09:38 AM UTC 24 |
| Finished | Oct 12 01:12:28 AM UTC 24 |
| Peak memory | 239968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227951491 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.4227951491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.403737791 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 385933179 ps |
| CPU time | 14.86 seconds |
| Started | Oct 12 01:09:38 AM UTC 24 |
| Finished | Oct 12 01:09:54 AM UTC 24 |
| Peak memory | 223720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403737791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.403737791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3613628099 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 173574934 ps |
| CPU time | 7.31 seconds |
| Started | Oct 12 01:09:37 AM UTC 24 |
| Finished | Oct 12 01:09:46 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613628099 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3613628099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.1269695961 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 158769704 ps |
| CPU time | 9.81 seconds |
| Started | Oct 12 01:09:35 AM UTC 24 |
| Finished | Oct 12 01:09:46 AM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126969596 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.1269695961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2752897686 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 12862091429 ps |
| CPU time | 234.89 seconds |
| Started | Oct 12 01:09:40 AM UTC 24 |
| Finished | Oct 12 01:13:39 AM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2752897686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2752897686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.365642151 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 288452487 ps |
| CPU time | 6.78 seconds |
| Started | Oct 12 01:09:45 AM UTC 24 |
| Finished | Oct 12 01:09:53 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365642151 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.365642151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2649252684 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2865171712 ps |
| CPU time | 89.72 seconds |
| Started | Oct 12 01:09:42 AM UTC 24 |
| Finished | Oct 12 01:11:13 AM UTC 24 |
| Peak memory | 260380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649252684 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.2649252684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.2995592363 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 923741353 ps |
| CPU time | 14.33 seconds |
| Started | Oct 12 01:09:43 AM UTC 24 |
| Finished | Oct 12 01:09:58 AM UTC 24 |
| Peak memory | 223640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995592363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2995592363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.2879005916 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 588870787 ps |
| CPU time | 8.61 seconds |
| Started | Oct 12 01:09:42 AM UTC 24 |
| Finished | Oct 12 01:09:51 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879005916 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2879005916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.1786743515 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1238447609 ps |
| CPU time | 14.04 seconds |
| Started | Oct 12 01:09:42 AM UTC 24 |
| Finished | Oct 12 01:09:57 AM UTC 24 |
| Peak memory | 223632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178674351 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.1786743515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.219649429 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2177236579 ps |
| CPU time | 125.67 seconds |
| Started | Oct 12 01:09:45 AM UTC 24 |
| Finished | Oct 12 01:11:53 AM UTC 24 |
| Peak memory | 232860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=219649429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 24.rom_ctrl_stress_all_with_rand_reset.219649429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3794348371 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 133969904 ps |
| CPU time | 7.17 seconds |
| Started | Oct 12 01:09:50 AM UTC 24 |
| Finished | Oct 12 01:09:59 AM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794348371 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3794348371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.660021580 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 9701744548 ps |
| CPU time | 120.54 seconds |
| Started | Oct 12 01:09:47 AM UTC 24 |
| Finished | Oct 12 01:11:50 AM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660021580 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.660021580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3736231820 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 371742739 ps |
| CPU time | 14.35 seconds |
| Started | Oct 12 01:09:47 AM UTC 24 |
| Finished | Oct 12 01:10:03 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736231820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3736231820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.3693790105 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 1121426124 ps |
| CPU time | 9.39 seconds |
| Started | Oct 12 01:09:46 AM UTC 24 |
| Finished | Oct 12 01:09:57 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693790105 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3693790105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.1696296510 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 662044986 ps |
| CPU time | 15.38 seconds |
| Started | Oct 12 01:09:46 AM UTC 24 |
| Finished | Oct 12 01:10:03 AM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169629651 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.1696296510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3882255242 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2450302723 ps |
| CPU time | 178.61 seconds |
| Started | Oct 12 01:09:47 AM UTC 24 |
| Finished | Oct 12 01:12:49 AM UTC 24 |
| Peak memory | 243284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3882255242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3882255242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.356952675 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 359092215 ps |
| CPU time | 4.28 seconds |
| Started | Oct 12 01:09:57 AM UTC 24 |
| Finished | Oct 12 01:10:02 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356952675 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.356952675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2980276498 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 9269577474 ps |
| CPU time | 161.06 seconds |
| Started | Oct 12 01:09:54 AM UTC 24 |
| Finished | Oct 12 01:12:37 AM UTC 24 |
| Peak memory | 259216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980276498 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.2980276498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1010371769 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2304966013 ps |
| CPU time | 12.84 seconds |
| Started | Oct 12 01:09:54 AM UTC 24 |
| Finished | Oct 12 01:10:08 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010371769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1010371769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2839647767 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 548928560 ps |
| CPU time | 5.87 seconds |
| Started | Oct 12 01:09:52 AM UTC 24 |
| Finished | Oct 12 01:09:59 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839647767 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2839647767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2172914609 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2240489341 ps |
| CPU time | 18.3 seconds |
| Started | Oct 12 01:09:51 AM UTC 24 |
| Finished | Oct 12 01:10:11 AM UTC 24 |
| Peak memory | 227668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217291460 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.2172914609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3813568536 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 170508160 ps |
| CPU time | 8.39 seconds |
| Started | Oct 12 01:10:00 AM UTC 24 |
| Finished | Oct 12 01:10:10 AM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813568536 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3813568536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.46581813 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 7186254614 ps |
| CPU time | 119.41 seconds |
| Started | Oct 12 01:09:58 AM UTC 24 |
| Finished | Oct 12 01:12:00 AM UTC 24 |
| Peak memory | 255212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46581813 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.46581813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.750234876 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 207058940 ps |
| CPU time | 10.75 seconds |
| Started | Oct 12 01:09:59 AM UTC 24 |
| Finished | Oct 12 01:10:11 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750234876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.750234876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.2375928831 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 643911007 ps |
| CPU time | 9.05 seconds |
| Started | Oct 12 01:09:58 AM UTC 24 |
| Finished | Oct 12 01:10:08 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375928831 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2375928831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.2270747910 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1214420799 ps |
| CPU time | 22.06 seconds |
| Started | Oct 12 01:09:58 AM UTC 24 |
| Finished | Oct 12 01:10:21 AM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227074791 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.2270747910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.2550218323 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 557160981 ps |
| CPU time | 4.89 seconds |
| Started | Oct 12 01:10:08 AM UTC 24 |
| Finished | Oct 12 01:10:14 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550218323 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2550218323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.918924150 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 10360104512 ps |
| CPU time | 98.51 seconds |
| Started | Oct 12 01:10:03 AM UTC 24 |
| Finished | Oct 12 01:11:44 AM UTC 24 |
| Peak memory | 258900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918924150 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.918924150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.3040059292 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 569165376 ps |
| CPU time | 17 seconds |
| Started | Oct 12 01:10:03 AM UTC 24 |
| Finished | Oct 12 01:10:22 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040059292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3040059292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.4067059522 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 386608264 ps |
| CPU time | 7.63 seconds |
| Started | Oct 12 01:10:03 AM UTC 24 |
| Finished | Oct 12 01:10:12 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067059522 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4067059522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3628186294 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 679230656 ps |
| CPU time | 16 seconds |
| Started | Oct 12 01:10:00 AM UTC 24 |
| Finished | Oct 12 01:10:17 AM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362818629 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.3628186294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3736658893 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 11960514257 ps |
| CPU time | 201.36 seconds |
| Started | Oct 12 01:10:05 AM UTC 24 |
| Finished | Oct 12 01:13:29 AM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3736658893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3736658893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.4058810330 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 526824236 ps |
| CPU time | 6.05 seconds |
| Started | Oct 12 01:10:13 AM UTC 24 |
| Finished | Oct 12 01:10:20 AM UTC 24 |
| Peak memory | 223596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058810330 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4058810330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3751172220 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1866534914 ps |
| CPU time | 106.46 seconds |
| Started | Oct 12 01:10:11 AM UTC 24 |
| Finished | Oct 12 01:11:59 AM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751172220 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.3751172220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3611973320 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1416413212 ps |
| CPU time | 15.87 seconds |
| Started | Oct 12 01:10:12 AM UTC 24 |
| Finished | Oct 12 01:10:29 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611973320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3611973320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.4108852455 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 597004491 ps |
| CPU time | 9.42 seconds |
| Started | Oct 12 01:10:09 AM UTC 24 |
| Finished | Oct 12 01:10:19 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108852455 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4108852455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.4163390016 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1167154914 ps |
| CPU time | 15.63 seconds |
| Started | Oct 12 01:10:09 AM UTC 24 |
| Finished | Oct 12 01:10:26 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416339001 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.4163390016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3897469006 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 5905296504 ps |
| CPU time | 263.22 seconds |
| Started | Oct 12 01:10:12 AM UTC 24 |
| Finished | Oct 12 01:14:39 AM UTC 24 |
| Peak memory | 235140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3897469006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3897469006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.4281755851 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 170130280 ps |
| CPU time | 8.48 seconds |
| Started | Oct 12 01:07:57 AM UTC 24 |
| Finished | Oct 12 01:08:07 AM UTC 24 |
| Peak memory | 223324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281755851 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4281755851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2380684022 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6628811771 ps |
| CPU time | 113.41 seconds |
| Started | Oct 12 01:07:55 AM UTC 24 |
| Finished | Oct 12 01:09:51 AM UTC 24 |
| Peak memory | 258304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380684022 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.2380684022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.1803759847 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 554790939 ps |
| CPU time | 11.11 seconds |
| Started | Oct 12 01:07:55 AM UTC 24 |
| Finished | Oct 12 01:08:07 AM UTC 24 |
| Peak memory | 223456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803759847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1803759847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.1291978305 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 322335573 ps |
| CPU time | 6.87 seconds |
| Started | Oct 12 01:07:54 AM UTC 24 |
| Finished | Oct 12 01:08:02 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291978305 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1291978305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.2093734372 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2619087563 ps |
| CPU time | 107.94 seconds |
| Started | Oct 12 01:07:55 AM UTC 24 |
| Finished | Oct 12 01:09:45 AM UTC 24 |
| Peak memory | 259368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093734372 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2093734372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.2422687025 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 425253604 ps |
| CPU time | 7.07 seconds |
| Started | Oct 12 01:07:53 AM UTC 24 |
| Finished | Oct 12 01:08:01 AM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422687025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2422687025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.118066026 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8468706129 ps |
| CPU time | 128.99 seconds |
| Started | Oct 12 01:07:55 AM UTC 24 |
| Finished | Oct 12 01:10:06 AM UTC 24 |
| Peak memory | 234984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=118066026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 3.rom_ctrl_stress_all_with_rand_reset.118066026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.556357166 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 176688820 ps |
| CPU time | 8.45 seconds |
| Started | Oct 12 01:10:28 AM UTC 24 |
| Finished | Oct 12 01:10:37 AM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556357166 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.556357166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3214713008 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1269952409 ps |
| CPU time | 62.52 seconds |
| Started | Oct 12 01:10:27 AM UTC 24 |
| Finished | Oct 12 01:11:32 AM UTC 24 |
| Peak memory | 223844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214713008 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.3214713008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.2588680988 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2111477439 ps |
| CPU time | 11.13 seconds |
| Started | Oct 12 01:10:27 AM UTC 24 |
| Finished | Oct 12 01:10:40 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588680988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2588680988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.770915388 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 706131719 ps |
| CPU time | 5.98 seconds |
| Started | Oct 12 01:10:26 AM UTC 24 |
| Finished | Oct 12 01:10:33 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770915388 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.770915388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.2950539001 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 171594791 ps |
| CPU time | 18.23 seconds |
| Started | Oct 12 01:10:14 AM UTC 24 |
| Finished | Oct 12 01:10:34 AM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295053900 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.2950539001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2467368886 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 40650044049 ps |
| CPU time | 154.32 seconds |
| Started | Oct 12 01:10:27 AM UTC 24 |
| Finished | Oct 12 01:13:04 AM UTC 24 |
| Peak memory | 247120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2467368886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2467368886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3392905342 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 209500358 ps |
| CPU time | 6.97 seconds |
| Started | Oct 12 01:10:28 AM UTC 24 |
| Finished | Oct 12 01:10:36 AM UTC 24 |
| Peak memory | 223532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392905342 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3392905342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2967463262 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 19168034865 ps |
| CPU time | 162.27 seconds |
| Started | Oct 12 01:10:28 AM UTC 24 |
| Finished | Oct 12 01:13:13 AM UTC 24 |
| Peak memory | 244000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967463262 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.2967463262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.3844167250 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 300695062 ps |
| CPU time | 17.31 seconds |
| Started | Oct 12 01:10:28 AM UTC 24 |
| Finished | Oct 12 01:10:46 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844167250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3844167250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.4059998242 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 224144802 ps |
| CPU time | 8.36 seconds |
| Started | Oct 12 01:10:28 AM UTC 24 |
| Finished | Oct 12 01:10:37 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059998242 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4059998242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.145750829 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 894764847 ps |
| CPU time | 13.84 seconds |
| Started | Oct 12 01:10:28 AM UTC 24 |
| Finished | Oct 12 01:10:43 AM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145750829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.145750829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.785872604 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 288988715 ps |
| CPU time | 13.61 seconds |
| Started | Oct 12 01:10:28 AM UTC 24 |
| Finished | Oct 12 01:10:43 AM UTC 24 |
| Peak memory | 230292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=785872604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 31.rom_ctrl_stress_all_with_rand_reset.785872604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.2115956387 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 299534176 ps |
| CPU time | 6.84 seconds |
| Started | Oct 12 01:10:34 AM UTC 24 |
| Finished | Oct 12 01:10:42 AM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115956387 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2115956387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.576373911 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2425033505 ps |
| CPU time | 105.12 seconds |
| Started | Oct 12 01:10:30 AM UTC 24 |
| Finished | Oct 12 01:12:17 AM UTC 24 |
| Peak memory | 225892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576373911 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.576373911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.717068475 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 206614838 ps |
| CPU time | 11.5 seconds |
| Started | Oct 12 01:10:30 AM UTC 24 |
| Finished | Oct 12 01:10:43 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717068475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.717068475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.191399963 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 183104955 ps |
| CPU time | 11.47 seconds |
| Started | Oct 12 01:10:28 AM UTC 24 |
| Finished | Oct 12 01:10:41 AM UTC 24 |
| Peak memory | 223436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191399963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.191399963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1855037345 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 2289522702 ps |
| CPU time | 103.53 seconds |
| Started | Oct 12 01:10:32 AM UTC 24 |
| Finished | Oct 12 01:12:18 AM UTC 24 |
| Peak memory | 232852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1855037345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1855037345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.1920087783 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 124476009 ps |
| CPU time | 7.26 seconds |
| Started | Oct 12 01:10:38 AM UTC 24 |
| Finished | Oct 12 01:10:46 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920087783 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1920087783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2386801235 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2510161965 ps |
| CPU time | 79.07 seconds |
| Started | Oct 12 01:10:36 AM UTC 24 |
| Finished | Oct 12 01:11:57 AM UTC 24 |
| Peak memory | 260244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386801235 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.2386801235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2937079165 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 732065157 ps |
| CPU time | 12.37 seconds |
| Started | Oct 12 01:10:38 AM UTC 24 |
| Finished | Oct 12 01:10:51 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937079165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2937079165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.1264694613 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 152114603 ps |
| CPU time | 7.35 seconds |
| Started | Oct 12 01:10:34 AM UTC 24 |
| Finished | Oct 12 01:10:43 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264694613 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1264694613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.3707284627 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 395224357 ps |
| CPU time | 17.49 seconds |
| Started | Oct 12 01:10:34 AM UTC 24 |
| Finished | Oct 12 01:10:53 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370728462 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.3707284627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.425786199 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 1743451578 ps |
| CPU time | 80.7 seconds |
| Started | Oct 12 01:10:38 AM UTC 24 |
| Finished | Oct 12 01:12:00 AM UTC 24 |
| Peak memory | 232796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=425786199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 33.rom_ctrl_stress_all_with_rand_reset.425786199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.173372654 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2095737935 ps |
| CPU time | 11.17 seconds |
| Started | Oct 12 01:10:43 AM UTC 24 |
| Finished | Oct 12 01:10:55 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173372654 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.173372654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3239496243 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 5445512640 ps |
| CPU time | 266.71 seconds |
| Started | Oct 12 01:10:42 AM UTC 24 |
| Finished | Oct 12 01:15:13 AM UTC 24 |
| Peak memory | 225892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239496243 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.3239496243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2524718205 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 292998797 ps |
| CPU time | 13.21 seconds |
| Started | Oct 12 01:10:43 AM UTC 24 |
| Finished | Oct 12 01:10:57 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524718205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2524718205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.810545654 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 313305405 ps |
| CPU time | 5.38 seconds |
| Started | Oct 12 01:10:41 AM UTC 24 |
| Finished | Oct 12 01:10:48 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810545654 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.810545654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1442821846 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 458112704 ps |
| CPU time | 26.65 seconds |
| Started | Oct 12 01:10:38 AM UTC 24 |
| Finished | Oct 12 01:11:06 AM UTC 24 |
| Peak memory | 229668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144282184 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.1442821846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.227652218 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 8324713681 ps |
| CPU time | 107.09 seconds |
| Started | Oct 12 01:10:43 AM UTC 24 |
| Finished | Oct 12 01:12:32 AM UTC 24 |
| Peak memory | 232860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=227652218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 34.rom_ctrl_stress_all_with_rand_reset.227652218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.4036853227 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 474974701 ps |
| CPU time | 5.68 seconds |
| Started | Oct 12 01:10:51 AM UTC 24 |
| Finished | Oct 12 01:10:57 AM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036853227 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.4036853227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3601775691 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3899781366 ps |
| CPU time | 234.69 seconds |
| Started | Oct 12 01:10:47 AM UTC 24 |
| Finished | Oct 12 01:14:46 AM UTC 24 |
| Peak memory | 259228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601775691 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.3601775691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.3110108018 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 19881295844 ps |
| CPU time | 18.8 seconds |
| Started | Oct 12 01:10:47 AM UTC 24 |
| Finished | Oct 12 01:11:07 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110108018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3110108018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.1699079859 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 1041593851 ps |
| CPU time | 8.32 seconds |
| Started | Oct 12 01:10:44 AM UTC 24 |
| Finished | Oct 12 01:10:54 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699079859 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1699079859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.849579131 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1072176745 ps |
| CPU time | 20.12 seconds |
| Started | Oct 12 01:10:44 AM UTC 24 |
| Finished | Oct 12 01:11:06 AM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849579131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.849579131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.4217174623 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 15180509072 ps |
| CPU time | 185.25 seconds |
| Started | Oct 12 01:10:48 AM UTC 24 |
| Finished | Oct 12 01:13:57 AM UTC 24 |
| Peak memory | 248204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4217174623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 35.rom_ctrl_stress_all_with_rand_reset.4217174623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.2724644078 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 498705835 ps |
| CPU time | 7.1 seconds |
| Started | Oct 12 01:10:58 AM UTC 24 |
| Finished | Oct 12 01:11:06 AM UTC 24 |
| Peak memory | 223596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724644078 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2724644078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3116463204 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 35569498122 ps |
| CPU time | 132.55 seconds |
| Started | Oct 12 01:10:55 AM UTC 24 |
| Finished | Oct 12 01:13:10 AM UTC 24 |
| Peak memory | 255212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116463204 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.3116463204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1053408806 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 298347710 ps |
| CPU time | 13.88 seconds |
| Started | Oct 12 01:10:56 AM UTC 24 |
| Finished | Oct 12 01:11:11 AM UTC 24 |
| Peak memory | 223640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053408806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1053408806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.1895739378 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 222330926 ps |
| CPU time | 9.24 seconds |
| Started | Oct 12 01:10:54 AM UTC 24 |
| Finished | Oct 12 01:11:04 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895739378 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1895739378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1988392022 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 473154166 ps |
| CPU time | 23.47 seconds |
| Started | Oct 12 01:10:52 AM UTC 24 |
| Finished | Oct 12 01:11:16 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198839202 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.1988392022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.1857782070 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 169435418 ps |
| CPU time | 8.49 seconds |
| Started | Oct 12 01:11:09 AM UTC 24 |
| Finished | Oct 12 01:11:19 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857782070 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1857782070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3015433514 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 2926140808 ps |
| CPU time | 127.97 seconds |
| Started | Oct 12 01:11:09 AM UTC 24 |
| Finished | Oct 12 01:13:19 AM UTC 24 |
| Peak memory | 259224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015433514 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.3015433514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2494800331 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1068298639 ps |
| CPU time | 16.13 seconds |
| Started | Oct 12 01:11:09 AM UTC 24 |
| Finished | Oct 12 01:11:26 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494800331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2494800331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.4066191814 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 529795790 ps |
| CPU time | 9.9 seconds |
| Started | Oct 12 01:11:09 AM UTC 24 |
| Finished | Oct 12 01:11:20 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066191814 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4066191814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.181978318 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 633327667 ps |
| CPU time | 21.74 seconds |
| Started | Oct 12 01:11:08 AM UTC 24 |
| Finished | Oct 12 01:11:31 AM UTC 24 |
| Peak memory | 227872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181978318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.181978318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2204359553 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1507841663 ps |
| CPU time | 33.06 seconds |
| Started | Oct 12 01:11:09 AM UTC 24 |
| Finished | Oct 12 01:11:43 AM UTC 24 |
| Peak memory | 230744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2204359553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2204359553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.2905781909 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 171614696 ps |
| CPU time | 8.21 seconds |
| Started | Oct 12 01:11:18 AM UTC 24 |
| Finished | Oct 12 01:11:27 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905781909 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2905781909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2551976335 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 39066931149 ps |
| CPU time | 190.2 seconds |
| Started | Oct 12 01:11:11 AM UTC 24 |
| Finished | Oct 12 01:14:25 AM UTC 24 |
| Peak memory | 259220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551976335 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.2551976335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2040535643 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 212164396 ps |
| CPU time | 14.28 seconds |
| Started | Oct 12 01:11:14 AM UTC 24 |
| Finished | Oct 12 01:11:30 AM UTC 24 |
| Peak memory | 223640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040535643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2040535643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.3280878374 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 274230590 ps |
| CPU time | 7.05 seconds |
| Started | Oct 12 01:11:09 AM UTC 24 |
| Finished | Oct 12 01:11:17 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280878374 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3280878374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.2453056301 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 4440554427 ps |
| CPU time | 22.89 seconds |
| Started | Oct 12 01:11:09 AM UTC 24 |
| Finished | Oct 12 01:11:33 AM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245305630 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.2453056301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1831276055 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 2476261908 ps |
| CPU time | 106.64 seconds |
| Started | Oct 12 01:11:15 AM UTC 24 |
| Finished | Oct 12 01:13:04 AM UTC 24 |
| Peak memory | 232916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1831276055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1831276055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.2677006595 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 535970211 ps |
| CPU time | 7.51 seconds |
| Started | Oct 12 01:11:27 AM UTC 24 |
| Finished | Oct 12 01:11:36 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677006595 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2677006595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4049086935 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5289920928 ps |
| CPU time | 87.01 seconds |
| Started | Oct 12 01:11:20 AM UTC 24 |
| Finished | Oct 12 01:12:49 AM UTC 24 |
| Peak memory | 225892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049086935 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.4049086935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.3501248056 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 1074028013 ps |
| CPU time | 16.77 seconds |
| Started | Oct 12 01:11:21 AM UTC 24 |
| Finished | Oct 12 01:11:39 AM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501248056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3501248056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.3262924599 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 448380223 ps |
| CPU time | 6.97 seconds |
| Started | Oct 12 01:11:20 AM UTC 24 |
| Finished | Oct 12 01:11:28 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262924599 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3262924599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.27577081 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2163679042 ps |
| CPU time | 24.64 seconds |
| Started | Oct 12 01:11:19 AM UTC 24 |
| Finished | Oct 12 01:11:45 AM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27577081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.27577081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2689184095 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3080532688 ps |
| CPU time | 128.44 seconds |
| Started | Oct 12 01:11:24 AM UTC 24 |
| Finished | Oct 12 01:13:35 AM UTC 24 |
| Peak memory | 232916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2689184095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 39.rom_ctrl_stress_all_with_rand_reset.2689184095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2576885867 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 165478304 ps |
| CPU time | 6.07 seconds |
| Started | Oct 12 01:08:01 AM UTC 24 |
| Finished | Oct 12 01:08:08 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576885867 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2576885867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2456480776 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 7014413496 ps |
| CPU time | 122.05 seconds |
| Started | Oct 12 01:08:00 AM UTC 24 |
| Finished | Oct 12 01:10:04 AM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456480776 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.2456480776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.2498725974 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1071799986 ps |
| CPU time | 14.73 seconds |
| Started | Oct 12 01:08:00 AM UTC 24 |
| Finished | Oct 12 01:08:16 AM UTC 24 |
| Peak memory | 223356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498725974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2498725974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.2452621977 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 406052064 ps |
| CPU time | 5.8 seconds |
| Started | Oct 12 01:07:59 AM UTC 24 |
| Finished | Oct 12 01:08:05 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452621977 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2452621977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.283385693 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 383089789 ps |
| CPU time | 139.66 seconds |
| Started | Oct 12 01:08:00 AM UTC 24 |
| Finished | Oct 12 01:10:22 AM UTC 24 |
| Peak memory | 258692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283385693 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.283385693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1918588547 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 307618794 ps |
| CPU time | 9.73 seconds |
| Started | Oct 12 01:07:57 AM UTC 24 |
| Finished | Oct 12 01:08:08 AM UTC 24 |
| Peak memory | 223684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918588547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1918588547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3164552251 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 240981119 ps |
| CPU time | 11.64 seconds |
| Started | Oct 12 01:07:59 AM UTC 24 |
| Finished | Oct 12 01:08:11 AM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316455225 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.3164552251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.1006909003 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 209715895 ps |
| CPU time | 6.82 seconds |
| Started | Oct 12 01:11:31 AM UTC 24 |
| Finished | Oct 12 01:11:39 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006909003 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1006909003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4262219971 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3906693234 ps |
| CPU time | 125.14 seconds |
| Started | Oct 12 01:11:29 AM UTC 24 |
| Finished | Oct 12 01:13:37 AM UTC 24 |
| Peak memory | 243996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262219971 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.4262219971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.439705670 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 380434982 ps |
| CPU time | 14.68 seconds |
| Started | Oct 12 01:11:29 AM UTC 24 |
| Finished | Oct 12 01:11:45 AM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439705670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.439705670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3216723618 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 572469724 ps |
| CPU time | 6.77 seconds |
| Started | Oct 12 01:11:28 AM UTC 24 |
| Finished | Oct 12 01:11:36 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216723618 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3216723618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.3075921532 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 334793326 ps |
| CPU time | 24.78 seconds |
| Started | Oct 12 01:11:28 AM UTC 24 |
| Finished | Oct 12 01:11:54 AM UTC 24 |
| Peak memory | 229652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307592153 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.3075921532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.4161808160 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 4366195825 ps |
| CPU time | 21.34 seconds |
| Started | Oct 12 01:11:30 AM UTC 24 |
| Finished | Oct 12 01:11:53 AM UTC 24 |
| Peak memory | 230740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4161808160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 40.rom_ctrl_stress_all_with_rand_reset.4161808160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3002206109 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 205917681 ps |
| CPU time | 6.5 seconds |
| Started | Oct 12 01:11:37 AM UTC 24 |
| Finished | Oct 12 01:11:44 AM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002206109 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3002206109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2920688501 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 2279339424 ps |
| CPU time | 119.62 seconds |
| Started | Oct 12 01:11:33 AM UTC 24 |
| Finished | Oct 12 01:13:34 AM UTC 24 |
| Peak memory | 259176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920688501 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.2920688501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2229107056 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 477596873 ps |
| CPU time | 15.36 seconds |
| Started | Oct 12 01:11:35 AM UTC 24 |
| Finished | Oct 12 01:11:51 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229107056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2229107056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2920593913 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 541607163 ps |
| CPU time | 12.09 seconds |
| Started | Oct 12 01:11:33 AM UTC 24 |
| Finished | Oct 12 01:11:46 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920593913 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2920593913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.164713894 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 715178005 ps |
| CPU time | 8.74 seconds |
| Started | Oct 12 01:11:32 AM UTC 24 |
| Finished | Oct 12 01:11:41 AM UTC 24 |
| Peak memory | 223632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164713894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.164713894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2575946059 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 5251658312 ps |
| CPU time | 29.3 seconds |
| Started | Oct 12 01:11:37 AM UTC 24 |
| Finished | Oct 12 01:12:07 AM UTC 24 |
| Peak memory | 230764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2575946059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2575946059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.2393870413 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1582095660 ps |
| CPU time | 7.18 seconds |
| Started | Oct 12 01:11:43 AM UTC 24 |
| Finished | Oct 12 01:11:52 AM UTC 24 |
| Peak memory | 223596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393870413 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2393870413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.77602551 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2479651677 ps |
| CPU time | 115.78 seconds |
| Started | Oct 12 01:11:40 AM UTC 24 |
| Finished | Oct 12 01:13:38 AM UTC 24 |
| Peak memory | 259216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77602551 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.77602551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1270794998 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 733503061 ps |
| CPU time | 14.11 seconds |
| Started | Oct 12 01:11:42 AM UTC 24 |
| Finished | Oct 12 01:11:58 AM UTC 24 |
| Peak memory | 223460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270794998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1270794998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.4101022165 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 399555776 ps |
| CPU time | 7.79 seconds |
| Started | Oct 12 01:11:39 AM UTC 24 |
| Finished | Oct 12 01:11:48 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101022165 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4101022165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1703894576 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 418546870 ps |
| CPU time | 18.77 seconds |
| Started | Oct 12 01:11:38 AM UTC 24 |
| Finished | Oct 12 01:11:58 AM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170389457 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.1703894576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2834970137 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 41227630846 ps |
| CPU time | 237.35 seconds |
| Started | Oct 12 01:11:43 AM UTC 24 |
| Finished | Oct 12 01:15:44 AM UTC 24 |
| Peak memory | 248204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2834970137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2834970137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1088525955 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 293126344 ps |
| CPU time | 7.87 seconds |
| Started | Oct 12 01:11:46 AM UTC 24 |
| Finished | Oct 12 01:11:55 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088525955 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1088525955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2934037059 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2113405532 ps |
| CPU time | 132.5 seconds |
| Started | Oct 12 01:11:45 AM UTC 24 |
| Finished | Oct 12 01:14:00 AM UTC 24 |
| Peak memory | 259160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934037059 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.2934037059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.1802801424 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1570692489 ps |
| CPU time | 20.09 seconds |
| Started | Oct 12 01:11:46 AM UTC 24 |
| Finished | Oct 12 01:12:07 AM UTC 24 |
| Peak memory | 223640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802801424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1802801424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.539279357 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 232017615 ps |
| CPU time | 9.22 seconds |
| Started | Oct 12 01:11:45 AM UTC 24 |
| Finished | Oct 12 01:11:55 AM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539279357 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.539279357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.1232422392 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 533572119 ps |
| CPU time | 13.64 seconds |
| Started | Oct 12 01:11:45 AM UTC 24 |
| Finished | Oct 12 01:11:59 AM UTC 24 |
| Peak memory | 223456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123242239 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.1232422392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.344707870 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 1097959934 ps |
| CPU time | 47.99 seconds |
| Started | Oct 12 01:11:46 AM UTC 24 |
| Finished | Oct 12 01:12:35 AM UTC 24 |
| Peak memory | 230748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=344707870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 43.rom_ctrl_stress_all_with_rand_reset.344707870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1428310285 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2014903911 ps |
| CPU time | 8.74 seconds |
| Started | Oct 12 01:11:53 AM UTC 24 |
| Finished | Oct 12 01:12:03 AM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428310285 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1428310285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2007336182 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 6010381962 ps |
| CPU time | 188.84 seconds |
| Started | Oct 12 01:11:51 AM UTC 24 |
| Finished | Oct 12 01:15:03 AM UTC 24 |
| Peak memory | 255016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007336182 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.2007336182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2305588460 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 210124098 ps |
| CPU time | 11.68 seconds |
| Started | Oct 12 01:11:52 AM UTC 24 |
| Finished | Oct 12 01:12:05 AM UTC 24 |
| Peak memory | 223336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305588460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2305588460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3482620713 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 136997408 ps |
| CPU time | 7.83 seconds |
| Started | Oct 12 01:11:49 AM UTC 24 |
| Finished | Oct 12 01:11:58 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482620713 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3482620713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1239950862 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 389546439 ps |
| CPU time | 10.31 seconds |
| Started | Oct 12 01:11:47 AM UTC 24 |
| Finished | Oct 12 01:11:58 AM UTC 24 |
| Peak memory | 223440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123995086 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.1239950862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.329646597 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 19938935112 ps |
| CPU time | 189.61 seconds |
| Started | Oct 12 01:11:52 AM UTC 24 |
| Finished | Oct 12 01:15:05 AM UTC 24 |
| Peak memory | 236752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=329646597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 44.rom_ctrl_stress_all_with_rand_reset.329646597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.698312613 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 451597776 ps |
| CPU time | 5.84 seconds |
| Started | Oct 12 01:11:58 AM UTC 24 |
| Finished | Oct 12 01:12:05 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698312613 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.698312613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2240385726 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2365500395 ps |
| CPU time | 111.64 seconds |
| Started | Oct 12 01:11:55 AM UTC 24 |
| Finished | Oct 12 01:13:48 AM UTC 24 |
| Peak memory | 259000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240385726 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.2240385726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.1404612875 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 298103603 ps |
| CPU time | 13.13 seconds |
| Started | Oct 12 01:11:56 AM UTC 24 |
| Finished | Oct 12 01:12:10 AM UTC 24 |
| Peak memory | 223640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404612875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1404612875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.2802506469 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 312168126 ps |
| CPU time | 9.74 seconds |
| Started | Oct 12 01:11:53 AM UTC 24 |
| Finished | Oct 12 01:12:04 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802506469 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2802506469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.4161278283 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 210332534 ps |
| CPU time | 11.49 seconds |
| Started | Oct 12 01:11:53 AM UTC 24 |
| Finished | Oct 12 01:12:06 AM UTC 24 |
| Peak memory | 223508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416127828 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.4161278283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.4167939567 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 61966773656 ps |
| CPU time | 116.91 seconds |
| Started | Oct 12 01:11:56 AM UTC 24 |
| Finished | Oct 12 01:13:55 AM UTC 24 |
| Peak memory | 248464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4167939567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 45.rom_ctrl_stress_all_with_rand_reset.4167939567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.823879805 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 166999268 ps |
| CPU time | 8.38 seconds |
| Started | Oct 12 01:12:00 AM UTC 24 |
| Finished | Oct 12 01:12:10 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823879805 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.823879805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.708440910 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 3558227429 ps |
| CPU time | 159.63 seconds |
| Started | Oct 12 01:11:59 AM UTC 24 |
| Finished | Oct 12 01:14:41 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708440910 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.708440910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.403994619 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1067923908 ps |
| CPU time | 11.24 seconds |
| Started | Oct 12 01:11:59 AM UTC 24 |
| Finished | Oct 12 01:12:11 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403994619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.403994619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1426612415 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 638147307 ps |
| CPU time | 5.66 seconds |
| Started | Oct 12 01:11:59 AM UTC 24 |
| Finished | Oct 12 01:12:06 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426612415 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1426612415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3487977744 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1270488185 ps |
| CPU time | 12.82 seconds |
| Started | Oct 12 01:11:59 AM UTC 24 |
| Finished | Oct 12 01:12:13 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348797774 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.3487977744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3858924263 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1489737109 ps |
| CPU time | 86.48 seconds |
| Started | Oct 12 01:11:59 AM UTC 24 |
| Finished | Oct 12 01:13:28 AM UTC 24 |
| Peak memory | 230740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3858924263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 46.rom_ctrl_stress_all_with_rand_reset.3858924263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1934823738 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 604731327 ps |
| CPU time | 7.55 seconds |
| Started | Oct 12 01:12:06 AM UTC 24 |
| Finished | Oct 12 01:12:14 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934823738 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1934823738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2715710419 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 4010391417 ps |
| CPU time | 123.84 seconds |
| Started | Oct 12 01:12:00 AM UTC 24 |
| Finished | Oct 12 01:14:06 AM UTC 24 |
| Peak memory | 244000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715710419 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.2715710419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.435578352 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 288165062 ps |
| CPU time | 13.2 seconds |
| Started | Oct 12 01:12:01 AM UTC 24 |
| Finished | Oct 12 01:12:16 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435578352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.435578352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1499000164 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 177524573 ps |
| CPU time | 10.23 seconds |
| Started | Oct 12 01:12:00 AM UTC 24 |
| Finished | Oct 12 01:12:12 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499000164 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1499000164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.1417476080 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 331342834 ps |
| CPU time | 22.45 seconds |
| Started | Oct 12 01:12:00 AM UTC 24 |
| Finished | Oct 12 01:12:24 AM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141747608 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.1417476080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2944930428 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 24812916214 ps |
| CPU time | 206.6 seconds |
| Started | Oct 12 01:12:04 AM UTC 24 |
| Finished | Oct 12 01:15:33 AM UTC 24 |
| Peak memory | 247188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2944930428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2944930428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.3668090127 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 581807239 ps |
| CPU time | 5.37 seconds |
| Started | Oct 12 01:12:08 AM UTC 24 |
| Finished | Oct 12 01:12:14 AM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668090127 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3668090127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1181911963 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 2201063382 ps |
| CPU time | 148.29 seconds |
| Started | Oct 12 01:12:07 AM UTC 24 |
| Finished | Oct 12 01:14:38 AM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181911963 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.1181911963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.3704989206 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 731162964 ps |
| CPU time | 14.57 seconds |
| Started | Oct 12 01:12:07 AM UTC 24 |
| Finished | Oct 12 01:12:23 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704989206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3704989206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.3112783886 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 180309963 ps |
| CPU time | 9.64 seconds |
| Started | Oct 12 01:12:06 AM UTC 24 |
| Finished | Oct 12 01:12:16 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112783886 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3112783886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3121772250 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 411145985 ps |
| CPU time | 18.85 seconds |
| Started | Oct 12 01:12:06 AM UTC 24 |
| Finished | Oct 12 01:12:26 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312177225 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.3121772250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3122173552 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 3408890157 ps |
| CPU time | 204.7 seconds |
| Started | Oct 12 01:12:08 AM UTC 24 |
| Finished | Oct 12 01:15:36 AM UTC 24 |
| Peak memory | 243092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3122173552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 48.rom_ctrl_stress_all_with_rand_reset.3122173552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.1508396223 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 172209261 ps |
| CPU time | 7.11 seconds |
| Started | Oct 12 01:12:12 AM UTC 24 |
| Finished | Oct 12 01:12:21 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508396223 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1508396223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.8048710 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3983940751 ps |
| CPU time | 111.65 seconds |
| Started | Oct 12 01:12:08 AM UTC 24 |
| Finished | Oct 12 01:14:02 AM UTC 24 |
| Peak memory | 256284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8048710 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.8048710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.1091791240 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 535685119 ps |
| CPU time | 14.64 seconds |
| Started | Oct 12 01:12:10 AM UTC 24 |
| Finished | Oct 12 01:12:27 AM UTC 24 |
| Peak memory | 223640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091791240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1091791240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2306384148 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 409879092 ps |
| CPU time | 7.04 seconds |
| Started | Oct 12 01:12:08 AM UTC 24 |
| Finished | Oct 12 01:12:16 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306384148 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2306384148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.3897106492 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 415076473 ps |
| CPU time | 31.14 seconds |
| Started | Oct 12 01:12:08 AM UTC 24 |
| Finished | Oct 12 01:12:41 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389710649 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.3897106492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2168400809 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 166297001 ps |
| CPU time | 6.46 seconds |
| Started | Oct 12 01:08:05 AM UTC 24 |
| Finished | Oct 12 01:08:13 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168400809 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2168400809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1365894457 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 7640398582 ps |
| CPU time | 180.8 seconds |
| Started | Oct 12 01:08:03 AM UTC 24 |
| Finished | Oct 12 01:11:07 AM UTC 24 |
| Peak memory | 255208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365894457 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.1365894457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.760971672 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 837014099 ps |
| CPU time | 12.85 seconds |
| Started | Oct 12 01:08:04 AM UTC 24 |
| Finished | Oct 12 01:08:18 AM UTC 24 |
| Peak memory | 223452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760971672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.760971672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3423665728 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1966270342 ps |
| CPU time | 10.45 seconds |
| Started | Oct 12 01:08:02 AM UTC 24 |
| Finished | Oct 12 01:08:14 AM UTC 24 |
| Peak memory | 223712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423665728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3423665728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.171552651 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 165502194 ps |
| CPU time | 7.04 seconds |
| Started | Oct 12 01:08:02 AM UTC 24 |
| Finished | Oct 12 01:08:10 AM UTC 24 |
| Peak memory | 223636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171552651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.171552651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.3545447443 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 125313046 ps |
| CPU time | 6.98 seconds |
| Started | Oct 12 01:08:11 AM UTC 24 |
| Finished | Oct 12 01:08:19 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545447443 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3545447443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3408024295 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1671946263 ps |
| CPU time | 105.47 seconds |
| Started | Oct 12 01:08:09 AM UTC 24 |
| Finished | Oct 12 01:09:56 AM UTC 24 |
| Peak memory | 258904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408024295 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.3408024295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3331716226 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1031446436 ps |
| CPU time | 11.55 seconds |
| Started | Oct 12 01:08:09 AM UTC 24 |
| Finished | Oct 12 01:08:21 AM UTC 24 |
| Peak memory | 223648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331716226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3331716226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.1992014115 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 740716326 ps |
| CPU time | 7.6 seconds |
| Started | Oct 12 01:08:08 AM UTC 24 |
| Finished | Oct 12 01:08:16 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992014115 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1992014115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.2048459340 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 137834366 ps |
| CPU time | 6.87 seconds |
| Started | Oct 12 01:08:07 AM UTC 24 |
| Finished | Oct 12 01:08:15 AM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048459340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2048459340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.3291827488 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1139177203 ps |
| CPU time | 15.85 seconds |
| Started | Oct 12 01:08:07 AM UTC 24 |
| Finished | Oct 12 01:08:24 AM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329182748 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.3291827488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3185241667 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 4341636988 ps |
| CPU time | 204.81 seconds |
| Started | Oct 12 01:08:09 AM UTC 24 |
| Finished | Oct 12 01:11:37 AM UTC 24 |
| Peak memory | 247196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3185241667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3185241667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.1124403001 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 298966803 ps |
| CPU time | 5.14 seconds |
| Started | Oct 12 01:08:15 AM UTC 24 |
| Finished | Oct 12 01:08:21 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124403001 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1124403001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.675971202 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1388212292 ps |
| CPU time | 103.64 seconds |
| Started | Oct 12 01:08:13 AM UTC 24 |
| Finished | Oct 12 01:09:59 AM UTC 24 |
| Peak memory | 259272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675971202 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.675971202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.570907820 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 298428579 ps |
| CPU time | 13.7 seconds |
| Started | Oct 12 01:08:13 AM UTC 24 |
| Finished | Oct 12 01:08:28 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570907820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.570907820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1433277521 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 135136287 ps |
| CPU time | 7.52 seconds |
| Started | Oct 12 01:08:13 AM UTC 24 |
| Finished | Oct 12 01:08:22 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433277521 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1433277521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.1533469667 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 307348709 ps |
| CPU time | 9.64 seconds |
| Started | Oct 12 01:08:12 AM UTC 24 |
| Finished | Oct 12 01:08:23 AM UTC 24 |
| Peak memory | 223712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533469667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1533469667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2144537896 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 487872766 ps |
| CPU time | 18.78 seconds |
| Started | Oct 12 01:08:13 AM UTC 24 |
| Finished | Oct 12 01:08:33 AM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214453789 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.2144537896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3175938390 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 10290475492 ps |
| CPU time | 121.31 seconds |
| Started | Oct 12 01:08:14 AM UTC 24 |
| Finished | Oct 12 01:10:18 AM UTC 24 |
| Peak memory | 234908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3175938390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3175938390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3580756739 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 124008736 ps |
| CPU time | 6.39 seconds |
| Started | Oct 12 01:08:20 AM UTC 24 |
| Finished | Oct 12 01:08:27 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580756739 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3580756739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2221150158 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1899007259 ps |
| CPU time | 97.51 seconds |
| Started | Oct 12 01:08:18 AM UTC 24 |
| Finished | Oct 12 01:09:57 AM UTC 24 |
| Peak memory | 258804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221150158 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.2221150158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.1807281505 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 306132759 ps |
| CPU time | 14.09 seconds |
| Started | Oct 12 01:08:19 AM UTC 24 |
| Finished | Oct 12 01:08:34 AM UTC 24 |
| Peak memory | 223456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807281505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1807281505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1284824833 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 400525625 ps |
| CPU time | 8.48 seconds |
| Started | Oct 12 01:08:18 AM UTC 24 |
| Finished | Oct 12 01:08:27 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284824833 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1284824833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2441772601 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 755875266 ps |
| CPU time | 8.87 seconds |
| Started | Oct 12 01:08:16 AM UTC 24 |
| Finished | Oct 12 01:08:26 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441772601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2441772601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3266118423 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2083886813 ps |
| CPU time | 14.67 seconds |
| Started | Oct 12 01:08:17 AM UTC 24 |
| Finished | Oct 12 01:08:32 AM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326611842 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.3266118423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1339583249 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 166765210 ps |
| CPU time | 7.1 seconds |
| Started | Oct 12 01:08:24 AM UTC 24 |
| Finished | Oct 12 01:08:32 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339583249 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1339583249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1929010393 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4393315151 ps |
| CPU time | 57.44 seconds |
| Started | Oct 12 01:08:22 AM UTC 24 |
| Finished | Oct 12 01:09:21 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929010393 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.1929010393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1968582979 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1036477286 ps |
| CPU time | 14.58 seconds |
| Started | Oct 12 01:08:22 AM UTC 24 |
| Finished | Oct 12 01:08:38 AM UTC 24 |
| Peak memory | 223456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968582979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1968582979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3165247661 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 136985371 ps |
| CPU time | 7.02 seconds |
| Started | Oct 12 01:08:22 AM UTC 24 |
| Finished | Oct 12 01:08:31 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165247661 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3165247661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2352214862 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 424506294 ps |
| CPU time | 8.67 seconds |
| Started | Oct 12 01:08:20 AM UTC 24 |
| Finished | Oct 12 01:08:30 AM UTC 24 |
| Peak memory | 223508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352214862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2352214862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.4241653374 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 262302750 ps |
| CPU time | 13.79 seconds |
| Started | Oct 12 01:08:21 AM UTC 24 |
| Finished | Oct 12 01:08:36 AM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424165337 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.4241653374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all/latest |
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