| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.84 | 99.36 | 92.13 | 97.67 | 100.00 | 98.55 | 98.06 | 99.06 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 63.72 | 63.72 | 94.52 | 94.52 | 73.03 | 73.03 | 45.23 | 45.23 | 40.00 | 40.00 | 88.41 | 88.41 | 93.58 | 93.58 | 11.24 | 11.24 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.959927287 |
| 74.55 | 10.84 | 94.90 | 0.38 | 79.63 | 6.60 | 47.23 | 2.00 | 40.00 | 0.00 | 89.86 | 1.45 | 95.07 | 1.49 | 75.18 | 63.93 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.4211494848 |
| 83.81 | 9.26 | 94.90 | 0.00 | 82.30 | 2.67 | 68.50 | 21.27 | 80.00 | 40.00 | 90.58 | 0.72 | 95.22 | 0.15 | 75.18 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4113696502 |
| 89.88 | 6.07 | 95.29 | 0.38 | 85.25 | 2.95 | 86.12 | 17.62 | 93.33 | 13.33 | 92.39 | 1.81 | 95.52 | 0.30 | 81.26 | 6.09 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.337481268 |
| 91.69 | 1.81 | 95.41 | 0.13 | 85.53 | 0.28 | 90.88 | 4.75 | 100.00 | 6.67 | 92.75 | 0.36 | 95.52 | 0.00 | 81.73 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.936477263 |
| 93.15 | 1.46 | 98.85 | 3.44 | 87.78 | 2.25 | 92.00 | 1.12 | 100.00 | 0.00 | 94.20 | 1.45 | 95.82 | 0.30 | 83.37 | 1.64 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.4205657331 |
| 94.28 | 1.13 | 99.11 | 0.25 | 88.48 | 0.70 | 92.00 | 0.00 | 100.00 | 0.00 | 95.29 | 1.09 | 95.82 | 0.00 | 89.23 | 5.85 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2271424086 |
| 95.00 | 0.72 | 99.36 | 0.25 | 89.19 | 0.70 | 94.00 | 2.00 | 100.00 | 0.00 | 97.10 | 1.81 | 96.12 | 0.30 | 89.23 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3261604608 |
| 95.69 | 0.69 | 99.36 | 0.00 | 90.45 | 1.26 | 94.00 | 0.00 | 100.00 | 0.00 | 97.83 | 0.72 | 96.12 | 0.00 | 92.04 | 2.81 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.761997025 |
| 96.20 | 0.51 | 99.36 | 0.00 | 90.45 | 0.00 | 96.17 | 2.17 | 100.00 | 0.00 | 97.83 | 0.00 | 96.12 | 0.00 | 93.44 | 1.41 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2320333352 |
| 96.55 | 0.35 | 99.36 | 0.00 | 91.15 | 0.70 | 96.22 | 0.05 | 100.00 | 0.00 | 97.83 | 0.00 | 96.42 | 0.30 | 94.85 | 1.41 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.3853097240 |
| 96.77 | 0.22 | 99.36 | 0.00 | 91.15 | 0.00 | 96.22 | 0.00 | 100.00 | 0.00 | 97.83 | 0.00 | 96.57 | 0.15 | 96.25 | 1.41 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.15941026 |
| 96.97 | 0.20 | 99.36 | 0.00 | 91.71 | 0.56 | 97.05 | 0.82 | 100.00 | 0.00 | 97.83 | 0.00 | 96.57 | 0.00 | 96.25 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4174076738 |
| 97.13 | 0.16 | 99.36 | 0.00 | 91.71 | 0.00 | 97.05 | 0.00 | 100.00 | 0.00 | 97.83 | 0.00 | 97.46 | 0.90 | 96.49 | 0.23 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4290877145 |
| 97.26 | 0.13 | 99.36 | 0.00 | 91.71 | 0.00 | 97.05 | 0.00 | 100.00 | 0.00 | 97.83 | 0.00 | 97.46 | 0.00 | 97.42 | 0.94 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4166010475 |
| 97.36 | 0.10 | 99.36 | 0.00 | 91.85 | 0.14 | 97.22 | 0.17 | 100.00 | 0.00 | 98.19 | 0.36 | 97.46 | 0.00 | 97.42 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.49581866 |
| 97.44 | 0.08 | 99.36 | 0.00 | 91.99 | 0.14 | 97.30 | 0.07 | 100.00 | 0.00 | 98.55 | 0.36 | 97.46 | 0.00 | 97.42 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.394632454 |
| 97.51 | 0.07 | 99.36 | 0.00 | 91.99 | 0.00 | 97.30 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.46 | 0.00 | 97.89 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.97584445 |
| 97.58 | 0.07 | 99.36 | 0.00 | 91.99 | 0.00 | 97.30 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.46 | 0.00 | 98.36 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2263796799 |
| 97.64 | 0.06 | 99.36 | 0.00 | 91.99 | 0.00 | 97.50 | 0.20 | 100.00 | 0.00 | 98.55 | 0.00 | 97.46 | 0.00 | 98.59 | 0.23 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3923010059 |
| 97.68 | 0.04 | 99.36 | 0.00 | 91.99 | 0.00 | 97.50 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.76 | 0.30 | 98.59 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2225491147 |
| 97.72 | 0.04 | 99.36 | 0.00 | 92.13 | 0.14 | 97.50 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.15 | 98.59 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.610163050 |
| 97.76 | 0.04 | 99.36 | 0.00 | 92.13 | 0.00 | 97.55 | 0.05 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 98.83 | 0.23 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1695329646 |
| 97.80 | 0.03 | 99.36 | 0.00 | 92.13 | 0.00 | 97.55 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.23 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.543299419 |
| 97.82 | 0.02 | 99.36 | 0.00 | 92.13 | 0.00 | 97.55 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 98.06 | 0.15 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.152154305 |
| 97.83 | 0.01 | 99.36 | 0.00 | 92.13 | 0.00 | 97.65 | 0.10 | 100.00 | 0.00 | 98.55 | 0.00 | 98.06 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1285801982 |
| 97.84 | 0.01 | 99.36 | 0.00 | 92.13 | 0.00 | 97.67 | 0.03 | 100.00 | 0.00 | 98.55 | 0.00 | 98.06 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2851049066 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.670418532 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.54088652 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3163454086 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.411454162 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.875533096 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2247408565 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.120939713 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4289415276 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.865702628 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3463296726 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1884257734 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.459300562 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1702486231 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1641254912 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3739197861 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1122499078 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2649503733 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2801399710 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2194081108 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3839287048 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1397611279 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3110650221 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4242414211 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2322990977 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2466148757 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.804476347 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3380017909 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3286267976 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2645145297 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1224897783 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.572340516 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3527440009 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1123427068 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2674901949 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1459862846 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.954364428 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.258604220 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3804222278 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.6523576 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1135702259 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3292694197 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.99305664 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2307130689 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3084685812 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1683412043 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3917140420 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.620514046 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3061846871 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3555651700 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2092267727 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3832906535 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3783669021 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4083591427 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2506938944 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3218490980 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2067070744 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1455944078 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.509426944 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2863108961 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3347202414 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2130805284 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4101756023 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.833763117 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.657071580 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1797601239 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2293091153 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1957914671 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3764371761 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3316315064 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3892386682 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3769280786 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1058445300 |
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| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4262219971 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.439705670 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3216723618 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.3075921532 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.4161808160 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3002206109 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2920688501 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2229107056 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2920593913 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.164713894 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2575946059 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.2393870413 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.77602551 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1270794998 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.4101022165 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1703894576 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2834970137 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1088525955 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2934037059 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.1802801424 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.539279357 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.1232422392 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.344707870 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1428310285 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2007336182 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2305588460 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3482620713 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1239950862 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.329646597 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.698312613 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2240385726 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.1404612875 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.2802506469 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.4161278283 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.4167939567 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.823879805 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.708440910 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.403994619 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1426612415 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.3487977744 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3858924263 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1934823738 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2715710419 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.435578352 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1499000164 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.1417476080 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2944930428 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.3668090127 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1181911963 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.3704989206 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.3112783886 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3121772250 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3122173552 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.1508396223 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.8048710 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.1091791240 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2306384148 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.3897106492 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2168400809 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1365894457 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.760971672 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3423665728 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.171552651 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.3545447443 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3408024295 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3331716226 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.1992014115 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.2048459340 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.3291827488 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3185241667 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.1124403001 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.675971202 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.570907820 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1433277521 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.1533469667 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2144537896 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3175938390 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3580756739 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2221150158 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.1807281505 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1284824833 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2441772601 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3266118423 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1339583249 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1929010393 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1968582979 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3165247661 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2352214862 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.4241653374 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.959927287 | Oct 12 01:07:43 AM UTC 24 | Oct 12 01:07:53 AM UTC 24 | 230778189 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.4205657331 | Oct 12 01:07:46 AM UTC 24 | Oct 12 01:07:53 AM UTC 24 | 188385435 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.2377304002 | Oct 12 01:07:45 AM UTC 24 | Oct 12 01:07:54 AM UTC 24 | 132986673 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.2070582473 | Oct 12 01:07:46 AM UTC 24 | Oct 12 01:07:54 AM UTC 24 | 419324056 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.836445319 | Oct 12 01:07:46 AM UTC 24 | Oct 12 01:07:56 AM UTC 24 | 298056448 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3212931169 | Oct 12 01:07:48 AM UTC 24 | Oct 12 01:07:56 AM UTC 24 | 530618702 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.49581866 | Oct 12 01:07:45 AM UTC 24 | Oct 12 01:07:58 AM UTC 24 | 574973573 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.3633744104 | Oct 12 01:07:52 AM UTC 24 | Oct 12 01:07:58 AM UTC 24 | 298914868 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1088631783 | Oct 12 01:07:49 AM UTC 24 | Oct 12 01:07:59 AM UTC 24 | 132004913 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.2714828731 | Oct 12 01:07:49 AM UTC 24 | Oct 12 01:07:59 AM UTC 24 | 1037667393 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2320333352 | Oct 12 01:07:43 AM UTC 24 | Oct 12 01:08:01 AM UTC 24 | 239146238 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2851049066 | Oct 12 01:07:48 AM UTC 24 | Oct 12 01:08:01 AM UTC 24 | 1014855638 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.2422687025 | Oct 12 01:07:53 AM UTC 24 | Oct 12 01:08:01 AM UTC 24 | 425253604 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.1291978305 | Oct 12 01:07:54 AM UTC 24 | Oct 12 01:08:02 AM UTC 24 | 322335573 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.3261604608 | Oct 12 01:07:50 AM UTC 24 | Oct 12 01:08:04 AM UTC 24 | 1037622991 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.2452621977 | Oct 12 01:07:59 AM UTC 24 | Oct 12 01:08:05 AM UTC 24 | 406052064 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.337481268 | Oct 12 01:07:46 AM UTC 24 | Oct 12 01:08:06 AM UTC 24 | 1676665133 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.4281755851 | Oct 12 01:07:57 AM UTC 24 | Oct 12 01:08:07 AM UTC 24 | 170130280 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.1803759847 | Oct 12 01:07:55 AM UTC 24 | Oct 12 01:08:07 AM UTC 24 | 554790939 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2576885867 | Oct 12 01:08:01 AM UTC 24 | Oct 12 01:08:08 AM UTC 24 | 165478304 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.1918588547 | Oct 12 01:07:57 AM UTC 24 | Oct 12 01:08:08 AM UTC 24 | 307618794 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.171552651 | Oct 12 01:08:02 AM UTC 24 | Oct 12 01:08:10 AM UTC 24 | 165502194 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3164552251 | Oct 12 01:07:59 AM UTC 24 | Oct 12 01:08:11 AM UTC 24 | 240981119 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.490619637 | Oct 12 01:07:49 AM UTC 24 | Oct 12 01:08:12 AM UTC 24 | 464317571 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.15941026 | Oct 12 01:08:02 AM UTC 24 | Oct 12 01:08:12 AM UTC 24 | 301727189 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2168400809 | Oct 12 01:08:05 AM UTC 24 | Oct 12 01:08:13 AM UTC 24 | 166297001 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3423665728 | Oct 12 01:08:02 AM UTC 24 | Oct 12 01:08:14 AM UTC 24 | 1966270342 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.2048459340 | Oct 12 01:08:07 AM UTC 24 | Oct 12 01:08:15 AM UTC 24 | 137834366 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.2498725974 | Oct 12 01:08:00 AM UTC 24 | Oct 12 01:08:16 AM UTC 24 | 1071799986 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.1992014115 | Oct 12 01:08:08 AM UTC 24 | Oct 12 01:08:16 AM UTC 24 | 740716326 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.760971672 | Oct 12 01:08:04 AM UTC 24 | Oct 12 01:08:18 AM UTC 24 | 837014099 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.3545447443 | Oct 12 01:08:11 AM UTC 24 | Oct 12 01:08:19 AM UTC 24 | 125313046 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.936477263 | Oct 12 01:07:54 AM UTC 24 | Oct 12 01:08:19 AM UTC 24 | 892549853 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.1124403001 | Oct 12 01:08:15 AM UTC 24 | Oct 12 01:08:21 AM UTC 24 | 298966803 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3331716226 | Oct 12 01:08:09 AM UTC 24 | Oct 12 01:08:21 AM UTC 24 | 1031446436 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1433277521 | Oct 12 01:08:13 AM UTC 24 | Oct 12 01:08:22 AM UTC 24 | 135136287 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.1533469667 | Oct 12 01:08:12 AM UTC 24 | Oct 12 01:08:23 AM UTC 24 | 307348709 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.3291827488 | Oct 12 01:08:07 AM UTC 24 | Oct 12 01:08:24 AM UTC 24 | 1139177203 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2441772601 | Oct 12 01:08:16 AM UTC 24 | Oct 12 01:08:26 AM UTC 24 | 755875266 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.1284824833 | Oct 12 01:08:18 AM UTC 24 | Oct 12 01:08:27 AM UTC 24 | 400525625 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3580756739 | Oct 12 01:08:20 AM UTC 24 | Oct 12 01:08:27 AM UTC 24 | 124008736 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.570907820 | Oct 12 01:08:13 AM UTC 24 | Oct 12 01:08:28 AM UTC 24 | 298428579 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2352214862 | Oct 12 01:08:20 AM UTC 24 | Oct 12 01:08:30 AM UTC 24 | 424506294 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3165247661 | Oct 12 01:08:22 AM UTC 24 | Oct 12 01:08:31 AM UTC 24 | 136985371 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1339583249 | Oct 12 01:08:24 AM UTC 24 | Oct 12 01:08:32 AM UTC 24 | 166765210 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.3266118423 | Oct 12 01:08:17 AM UTC 24 | Oct 12 01:08:32 AM UTC 24 | 2083886813 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.1566609357 | Oct 12 01:08:37 AM UTC 24 | Oct 12 01:08:54 AM UTC 24 | 299405522 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2144537896 | Oct 12 01:08:13 AM UTC 24 | Oct 12 01:08:33 AM UTC 24 | 487872766 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.2832926373 | Oct 12 01:08:25 AM UTC 24 | Oct 12 01:08:34 AM UTC 24 | 178818970 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.1807281505 | Oct 12 01:08:19 AM UTC 24 | Oct 12 01:08:34 AM UTC 24 | 306132759 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.4241653374 | Oct 12 01:08:21 AM UTC 24 | Oct 12 01:08:36 AM UTC 24 | 262302750 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.734931597 | Oct 12 01:08:29 AM UTC 24 | Oct 12 01:08:36 AM UTC 24 | 868513834 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.1968582979 | Oct 12 01:08:22 AM UTC 24 | Oct 12 01:08:38 AM UTC 24 | 1036477286 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.1251030488 | Oct 12 01:08:25 AM UTC 24 | Oct 12 01:08:39 AM UTC 24 | 1070880496 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.70260856 | Oct 12 01:08:31 AM UTC 24 | Oct 12 01:08:41 AM UTC 24 | 474097464 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.3648347325 | Oct 12 01:07:48 AM UTC 24 | Oct 12 01:08:42 AM UTC 24 | 183272854 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.2987838755 | Oct 12 01:08:35 AM UTC 24 | Oct 12 01:08:42 AM UTC 24 | 170474431 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.988879781 | Oct 12 01:08:28 AM UTC 24 | Oct 12 01:08:43 AM UTC 24 | 212127079 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.3775480740 | Oct 12 01:08:41 AM UTC 24 | Oct 12 01:08:58 AM UTC 24 | 256437249 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.394632454 | Oct 12 01:08:32 AM UTC 24 | Oct 12 01:08:45 AM UTC 24 | 1032062188 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.3252489521 | Oct 12 01:08:35 AM UTC 24 | Oct 12 01:08:45 AM UTC 24 | 319778038 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.2785396656 | Oct 12 01:08:46 AM UTC 24 | Oct 12 01:08:55 AM UTC 24 | 1245485447 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.2684259201 | Oct 12 01:08:38 AM UTC 24 | Oct 12 01:08:46 AM UTC 24 | 163932496 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.167024177 | Oct 12 01:08:40 AM UTC 24 | Oct 12 01:08:50 AM UTC 24 | 578519647 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4174076738 | Oct 12 01:07:49 AM UTC 24 | Oct 12 01:08:50 AM UTC 24 | 1115646416 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.1165689294 | Oct 12 01:08:30 AM UTC 24 | Oct 12 01:08:51 AM UTC 24 | 328862050 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1695329646 | Oct 12 01:08:43 AM UTC 24 | Oct 12 01:08:52 AM UTC 24 | 499934545 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.3853097240 | Oct 12 01:07:51 AM UTC 24 | Oct 12 01:08:55 AM UTC 24 | 290577197 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.27364214 | Oct 12 01:08:39 AM UTC 24 | Oct 12 01:08:53 AM UTC 24 | 636252793 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.439090928 | Oct 12 01:08:50 AM UTC 24 | Oct 12 01:08:58 AM UTC 24 | 127010014 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.926322643 | Oct 12 01:08:45 AM UTC 24 | Oct 12 01:09:02 AM UTC 24 | 612816077 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.2700074298 | Oct 12 01:08:35 AM UTC 24 | Oct 12 01:09:04 AM UTC 24 | 472410194 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3147688106 | Oct 12 01:08:51 AM UTC 24 | Oct 12 01:09:04 AM UTC 24 | 1841771495 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.2703878252 | Oct 12 01:08:51 AM UTC 24 | Oct 12 01:09:04 AM UTC 24 | 383254833 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4113696502 | Oct 12 01:07:45 AM UTC 24 | Oct 12 01:09:04 AM UTC 24 | 3493484370 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.543299419 | Oct 12 01:08:53 AM UTC 24 | Oct 12 01:09:05 AM UTC 24 | 1121977766 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.2756764506 | Oct 12 01:08:56 AM UTC 24 | Oct 12 01:09:05 AM UTC 24 | 307824256 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.3032743605 | Oct 12 01:08:47 AM UTC 24 | Oct 12 01:09:05 AM UTC 24 | 466673952 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.1676989549 | Oct 12 01:09:03 AM UTC 24 | Oct 12 01:09:08 AM UTC 24 | 791320836 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.371865805 | Oct 12 01:08:53 AM UTC 24 | Oct 12 01:09:10 AM UTC 24 | 1344482683 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.2195084313 | Oct 12 01:08:59 AM UTC 24 | Oct 12 01:09:15 AM UTC 24 | 426122982 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1455012154 | Oct 12 01:09:06 AM UTC 24 | Oct 12 01:09:15 AM UTC 24 | 2016969338 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.2268206898 | Oct 12 01:09:05 AM UTC 24 | Oct 12 01:09:16 AM UTC 24 | 229741108 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3752164839 | Oct 12 01:09:05 AM UTC 24 | Oct 12 01:09:20 AM UTC 24 | 306720097 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.657331462 | Oct 12 01:09:05 AM UTC 24 | Oct 12 01:09:21 AM UTC 24 | 996577570 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1929010393 | Oct 12 01:08:22 AM UTC 24 | Oct 12 01:09:21 AM UTC 24 | 4393315151 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.935033641 | Oct 12 01:09:09 AM UTC 24 | Oct 12 01:09:22 AM UTC 24 | 181861132 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1032984977 | Oct 12 01:08:55 AM UTC 24 | Oct 12 01:09:23 AM UTC 24 | 652423519 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.1183853091 | Oct 12 01:09:16 AM UTC 24 | Oct 12 01:09:25 AM UTC 24 | 535036814 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4141841614 | Oct 12 01:07:51 AM UTC 24 | Oct 12 01:09:25 AM UTC 24 | 5067193122 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.4211494848 | Oct 12 01:08:20 AM UTC 24 | Oct 12 01:10:31 AM UTC 24 | 8861464163 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.470096732 | Oct 12 01:09:15 AM UTC 24 | Oct 12 01:09:27 AM UTC 24 | 704955198 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.2649515903 | Oct 12 01:09:06 AM UTC 24 | Oct 12 01:09:27 AM UTC 24 | 2638970073 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.761997025 | Oct 12 01:07:45 AM UTC 24 | Oct 12 01:09:28 AM UTC 24 | 13166614307 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.641707284 | Oct 12 01:09:17 AM UTC 24 | Oct 12 01:09:29 AM UTC 24 | 175995371 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.652414662 | Oct 12 01:09:23 AM UTC 24 | Oct 12 01:09:30 AM UTC 24 | 537081946 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2210880801 | Oct 12 01:09:17 AM UTC 24 | Oct 12 01:09:32 AM UTC 24 | 309567576 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2705771495 | Oct 12 01:08:31 AM UTC 24 | Oct 12 01:09:32 AM UTC 24 | 868805879 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.3450274398 | Oct 12 01:09:23 AM UTC 24 | Oct 12 01:09:34 AM UTC 24 | 677759500 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1623986266 | Oct 12 01:08:28 AM UTC 24 | Oct 12 01:09:34 AM UTC 24 | 9781602964 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.2540466322 | Oct 12 01:09:25 AM UTC 24 | Oct 12 01:09:34 AM UTC 24 | 282989701 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.212373876 | Oct 12 01:09:29 AM UTC 24 | Oct 12 01:09:36 AM UTC 24 | 385755744 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.811106804 | Oct 12 01:09:24 AM UTC 24 | Oct 12 01:09:37 AM UTC 24 | 289079433 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.658197038 | Oct 12 01:07:48 AM UTC 24 | Oct 12 01:09:38 AM UTC 24 | 2076217860 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.693235041 | Oct 12 01:08:27 AM UTC 24 | Oct 12 01:09:40 AM UTC 24 | 1193510173 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.2011569591 | Oct 12 01:09:21 AM UTC 24 | Oct 12 01:09:40 AM UTC 24 | 295031113 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.271981877 | Oct 12 01:09:31 AM UTC 24 | Oct 12 01:09:40 AM UTC 24 | 429867923 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.940336471 | Oct 12 01:09:27 AM UTC 24 | Oct 12 01:09:41 AM UTC 24 | 2109923251 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.3448527699 | Oct 12 01:09:29 AM UTC 24 | Oct 12 01:09:41 AM UTC 24 | 704783934 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.3680156180 | Oct 12 01:09:23 AM UTC 24 | Oct 12 01:09:42 AM UTC 24 | 1511229350 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2950509059 | Oct 12 01:09:30 AM UTC 24 | Oct 12 01:09:44 AM UTC 24 | 1476445318 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.3317847344 | Oct 12 01:09:35 AM UTC 24 | Oct 12 01:09:44 AM UTC 24 | 125094957 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.2093734372 | Oct 12 01:07:55 AM UTC 24 | Oct 12 01:09:45 AM UTC 24 | 2619087563 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3613628099 | Oct 12 01:09:37 AM UTC 24 | Oct 12 01:09:46 AM UTC 24 | 173574934 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.1059790110 | Oct 12 01:09:26 AM UTC 24 | Oct 12 01:09:46 AM UTC 24 | 320273681 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.1269695961 | Oct 12 01:09:35 AM UTC 24 | Oct 12 01:09:46 AM UTC 24 | 158769704 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.509788816 | Oct 12 01:09:33 AM UTC 24 | Oct 12 01:09:47 AM UTC 24 | 297997566 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.4001902657 | Oct 12 01:09:41 AM UTC 24 | Oct 12 01:09:50 AM UTC 24 | 169703038 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2380684022 | Oct 12 01:07:55 AM UTC 24 | Oct 12 01:09:51 AM UTC 24 | 6628811771 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.2879005916 | Oct 12 01:09:42 AM UTC 24 | Oct 12 01:09:51 AM UTC 24 | 588870787 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.365642151 | Oct 12 01:09:45 AM UTC 24 | Oct 12 01:09:53 AM UTC 24 | 288452487 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.2362340920 | Oct 12 01:07:46 AM UTC 24 | Oct 12 01:09:53 AM UTC 24 | 226721227 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.403737791 | Oct 12 01:09:38 AM UTC 24 | Oct 12 01:09:54 AM UTC 24 | 385933179 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3408024295 | Oct 12 01:08:09 AM UTC 24 | Oct 12 01:09:56 AM UTC 24 | 1671946263 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.3693790105 | Oct 12 01:09:46 AM UTC 24 | Oct 12 01:09:57 AM UTC 24 | 1121426124 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.1786743515 | Oct 12 01:09:42 AM UTC 24 | Oct 12 01:09:57 AM UTC 24 | 1238447609 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2221150158 | Oct 12 01:08:18 AM UTC 24 | Oct 12 01:09:57 AM UTC 24 | 1899007259 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.2995592363 | Oct 12 01:09:43 AM UTC 24 | Oct 12 01:09:58 AM UTC 24 | 923741353 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3794348371 | Oct 12 01:09:50 AM UTC 24 | Oct 12 01:09:59 AM UTC 24 | 133969904 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.675971202 | Oct 12 01:08:13 AM UTC 24 | Oct 12 01:09:59 AM UTC 24 | 1388212292 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2839647767 | Oct 12 01:09:52 AM UTC 24 | Oct 12 01:09:59 AM UTC 24 | 548928560 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.356952675 | Oct 12 01:09:57 AM UTC 24 | Oct 12 01:10:02 AM UTC 24 | 359092215 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.1696296510 | Oct 12 01:09:46 AM UTC 24 | Oct 12 01:10:03 AM UTC 24 | 662044986 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3736231820 | Oct 12 01:09:47 AM UTC 24 | Oct 12 01:10:03 AM UTC 24 | 371742739 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2456480776 | Oct 12 01:08:00 AM UTC 24 | Oct 12 01:10:04 AM UTC 24 | 7014413496 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.118066026 | Oct 12 01:07:55 AM UTC 24 | Oct 12 01:10:06 AM UTC 24 | 8468706129 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1010371769 | Oct 12 01:09:54 AM UTC 24 | Oct 12 01:10:08 AM UTC 24 | 2304966013 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.2375928831 | Oct 12 01:09:58 AM UTC 24 | Oct 12 01:10:08 AM UTC 24 | 643911007 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3813568536 | Oct 12 01:10:00 AM UTC 24 | Oct 12 01:10:10 AM UTC 24 | 170508160 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2172914609 | Oct 12 01:09:51 AM UTC 24 | Oct 12 01:10:11 AM UTC 24 | 2240489341 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.750234876 | Oct 12 01:09:59 AM UTC 24 | Oct 12 01:10:11 AM UTC 24 | 207058940 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.4067059522 | Oct 12 01:10:03 AM UTC 24 | Oct 12 01:10:12 AM UTC 24 | 386608264 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.2550218323 | Oct 12 01:10:08 AM UTC 24 | Oct 12 01:10:14 AM UTC 24 | 557160981 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1285801982 | Oct 12 01:08:43 AM UTC 24 | Oct 12 01:10:16 AM UTC 24 | 5635000665 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3628186294 | Oct 12 01:10:00 AM UTC 24 | Oct 12 01:10:17 AM UTC 24 | 679230656 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3175938390 | Oct 12 01:08:14 AM UTC 24 | Oct 12 01:10:18 AM UTC 24 | 10290475492 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3252729157 | Oct 12 01:09:18 AM UTC 24 | Oct 12 01:10:19 AM UTC 24 | 2093013371 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.4108852455 | Oct 12 01:10:09 AM UTC 24 | Oct 12 01:10:19 AM UTC 24 | 597004491 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.4058810330 | Oct 12 01:10:13 AM UTC 24 | Oct 12 01:10:20 AM UTC 24 | 526824236 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.2270747910 | Oct 12 01:09:58 AM UTC 24 | Oct 12 01:10:21 AM UTC 24 | 1214420799 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.3040059292 | Oct 12 01:10:03 AM UTC 24 | Oct 12 01:10:22 AM UTC 24 | 569165376 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.283385693 | Oct 12 01:08:00 AM UTC 24 | Oct 12 01:10:22 AM UTC 24 | 383089789 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.4206310706 | Oct 12 01:09:16 AM UTC 24 | Oct 12 01:10:23 AM UTC 24 | 21734866888 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.457848337 | Oct 12 01:09:29 AM UTC 24 | Oct 12 01:10:25 AM UTC 24 | 1077032283 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.4163390016 | Oct 12 01:10:09 AM UTC 24 | Oct 12 01:10:26 AM UTC 24 | 1167154914 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3611973320 | Oct 12 01:10:12 AM UTC 24 | Oct 12 01:10:29 AM UTC 24 | 1416413212 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1977659813 | Oct 12 01:09:00 AM UTC 24 | Oct 12 01:10:30 AM UTC 24 | 2204398690 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.770915388 | Oct 12 01:10:26 AM UTC 24 | Oct 12 01:10:33 AM UTC 24 | 706131719 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.2950539001 | Oct 12 01:10:14 AM UTC 24 | Oct 12 01:10:34 AM UTC 24 | 171594791 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.376124500 | Oct 12 01:08:35 AM UTC 24 | Oct 12 01:10:34 AM UTC 24 | 9203336132 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3392905342 | Oct 12 01:10:28 AM UTC 24 | Oct 12 01:10:36 AM UTC 24 | 209500358 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.152154305 | Oct 12 01:10:28 AM UTC 24 | Oct 12 01:10:37 AM UTC 24 | 1370239581 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.4059998242 | Oct 12 01:10:28 AM UTC 24 | Oct 12 01:10:37 AM UTC 24 | 224144802 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.4254049246 | Oct 12 01:09:35 AM UTC 24 | Oct 12 01:10:37 AM UTC 24 | 1553358543 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.556357166 | Oct 12 01:10:28 AM UTC 24 | Oct 12 01:10:37 AM UTC 24 | 176688820 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.2588680988 | Oct 12 01:10:27 AM UTC 24 | Oct 12 01:10:40 AM UTC 24 | 2111477439 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.191399963 | Oct 12 01:10:28 AM UTC 24 | Oct 12 01:10:41 AM UTC 24 | 183104955 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.2115956387 | Oct 12 01:10:34 AM UTC 24 | Oct 12 01:10:42 AM UTC 24 | 299534176 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.785872604 | Oct 12 01:10:28 AM UTC 24 | Oct 12 01:10:43 AM UTC 24 | 288988715 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.145750829 | Oct 12 01:10:28 AM UTC 24 | Oct 12 01:10:43 AM UTC 24 | 894764847 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.717068475 | Oct 12 01:10:30 AM UTC 24 | Oct 12 01:10:43 AM UTC 24 | 206614838 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.1264694613 | Oct 12 01:10:34 AM UTC 24 | Oct 12 01:10:43 AM UTC 24 | 152114603 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.1920087783 | Oct 12 01:10:38 AM UTC 24 | Oct 12 01:10:46 AM UTC 24 | 124476009 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.3844167250 | Oct 12 01:10:28 AM UTC 24 | Oct 12 01:10:46 AM UTC 24 | 300695062 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.810545654 | Oct 12 01:10:41 AM UTC 24 | Oct 12 01:10:48 AM UTC 24 | 313305405 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2842711078 | Oct 12 01:09:27 AM UTC 24 | Oct 12 01:10:49 AM UTC 24 | 2129371975 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2937079165 | Oct 12 01:10:38 AM UTC 24 | Oct 12 01:10:51 AM UTC 24 | 732065157 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.3707284627 | Oct 12 01:10:34 AM UTC 24 | Oct 12 01:10:53 AM UTC 24 | 395224357 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.1699079859 | Oct 12 01:10:44 AM UTC 24 | Oct 12 01:10:54 AM UTC 24 | 1041593851 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.173372654 | Oct 12 01:10:43 AM UTC 24 | Oct 12 01:10:55 AM UTC 24 | 2095737935 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2524718205 | Oct 12 01:10:43 AM UTC 24 | Oct 12 01:10:57 AM UTC 24 | 292998797 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.4036853227 | Oct 12 01:10:51 AM UTC 24 | Oct 12 01:10:57 AM UTC 24 | 474974701 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.1895739378 | Oct 12 01:10:54 AM UTC 24 | Oct 12 01:11:04 AM UTC 24 | 222330926 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3824505397 | Oct 12 01:08:46 AM UTC 24 | Oct 12 01:11:05 AM UTC 24 | 9374276607 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.849579131 | Oct 12 01:10:44 AM UTC 24 | Oct 12 01:11:06 AM UTC 24 | 1072176745 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1442821846 | Oct 12 01:10:38 AM UTC 24 | Oct 12 01:11:06 AM UTC 24 | 458112704 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.2724644078 | Oct 12 01:10:58 AM UTC 24 | Oct 12 01:11:06 AM UTC 24 | 498705835 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1365894457 | Oct 12 01:08:03 AM UTC 24 | Oct 12 01:11:07 AM UTC 24 | 7640398582 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.3110108018 | Oct 12 01:10:47 AM UTC 24 | Oct 12 01:11:07 AM UTC 24 | 19881295844 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1053408806 | Oct 12 01:10:56 AM UTC 24 | Oct 12 01:11:11 AM UTC 24 | 298347710 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2649252684 | Oct 12 01:09:42 AM UTC 24 | Oct 12 01:11:13 AM UTC 24 | 2865171712 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2754326407 | Oct 12 01:09:10 AM UTC 24 | Oct 12 01:11:15 AM UTC 24 | 2128279630 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1988392022 | Oct 12 01:10:52 AM UTC 24 | Oct 12 01:11:16 AM UTC 24 | 473154166 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.3280878374 | Oct 12 01:11:09 AM UTC 24 | Oct 12 01:11:17 AM UTC 24 | 274230590 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.1857782070 | Oct 12 01:11:09 AM UTC 24 | Oct 12 01:11:19 AM UTC 24 | 169435418 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.4066191814 | Oct 12 01:11:09 AM UTC 24 | Oct 12 01:11:20 AM UTC 24 | 529795790 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.403401398 | Oct 12 01:08:51 AM UTC 24 | Oct 12 01:11:24 AM UTC 24 | 2386613719 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2494800331 | Oct 12 01:11:09 AM UTC 24 | Oct 12 01:11:26 AM UTC 24 | 1068298639 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.2905781909 | Oct 12 01:11:18 AM UTC 24 | Oct 12 01:11:27 AM UTC 24 | 171614696 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.3262924599 | Oct 12 01:11:20 AM UTC 24 | Oct 12 01:11:28 AM UTC 24 | 448380223 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1219488217 | Oct 12 01:09:25 AM UTC 24 | Oct 12 01:11:28 AM UTC 24 | 1696897670 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2172141632 | Oct 12 01:08:40 AM UTC 24 | Oct 12 01:11:29 AM UTC 24 | 34372662349 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2040535643 | Oct 12 01:11:14 AM UTC 24 | Oct 12 01:11:30 AM UTC 24 | 212164396 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.181978318 | Oct 12 01:11:08 AM UTC 24 | Oct 12 01:11:31 AM UTC 24 | 633327667 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3923010059 | Oct 12 01:09:59 AM UTC 24 | Oct 12 01:11:31 AM UTC 24 | 2256006104 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3214713008 | Oct 12 01:10:27 AM UTC 24 | Oct 12 01:11:32 AM UTC 24 | 1269952409 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.2453056301 | Oct 12 01:11:09 AM UTC 24 | Oct 12 01:11:33 AM UTC 24 | 4440554427 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.2677006595 | Oct 12 01:11:27 AM UTC 24 | Oct 12 01:11:36 AM UTC 24 | 535970211 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3216723618 | Oct 12 01:11:28 AM UTC 24 | Oct 12 01:11:36 AM UTC 24 | 572469724 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3185241667 | Oct 12 01:08:09 AM UTC 24 | Oct 12 01:11:37 AM UTC 24 | 4341636988 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.3501248056 | Oct 12 01:11:21 AM UTC 24 | Oct 12 01:11:39 AM UTC 24 | 1074028013 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.1006909003 | Oct 12 01:11:31 AM UTC 24 | Oct 12 01:11:39 AM UTC 24 | 209715895 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.164713894 | Oct 12 01:11:32 AM UTC 24 | Oct 12 01:11:41 AM UTC 24 | 715178005 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1703894576 | Oct 12 01:11:38 AM UTC 24 | Oct 12 01:11:58 AM UTC 24 | 418546870 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3955796729 | Oct 12 01:09:05 AM UTC 24 | Oct 12 01:11:43 AM UTC 24 | 9894575366 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2204359553 | Oct 12 01:11:09 AM UTC 24 | Oct 12 01:11:43 AM UTC 24 | 1507841663 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.918924150 | Oct 12 01:10:03 AM UTC 24 | Oct 12 01:11:44 AM UTC 24 | 10360104512 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.3002206109 | Oct 12 01:11:37 AM UTC 24 | Oct 12 01:11:44 AM UTC 24 | 205917681 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.27577081 | Oct 12 01:11:19 AM UTC 24 | Oct 12 01:11:45 AM UTC 24 | 2163679042 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.439705670 | Oct 12 01:11:29 AM UTC 24 | Oct 12 01:11:45 AM UTC 24 | 380434982 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2920593913 | Oct 12 01:11:33 AM UTC 24 | Oct 12 01:11:46 AM UTC 24 | 541607163 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.4101022165 | Oct 12 01:11:39 AM UTC 24 | Oct 12 01:11:48 AM UTC 24 | 399555776 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.660021580 | Oct 12 01:09:47 AM UTC 24 | Oct 12 01:11:50 AM UTC 24 | 9701744548 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2229107056 | Oct 12 01:11:35 AM UTC 24 | Oct 12 01:11:51 AM UTC 24 | 477596873 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.2393870413 | Oct 12 01:11:43 AM UTC 24 | Oct 12 01:11:52 AM UTC 24 | 1582095660 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.219649429 | Oct 12 01:09:45 AM UTC 24 | Oct 12 01:11:53 AM UTC 24 | 2177236579 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.4161808160 | Oct 12 01:11:30 AM UTC 24 | Oct 12 01:11:53 AM UTC 24 | 4366195825 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.3075921532 | Oct 12 01:11:28 AM UTC 24 | Oct 12 01:11:54 AM UTC 24 | 334793326 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1088525955 | Oct 12 01:11:46 AM UTC 24 | Oct 12 01:11:55 AM UTC 24 | 293126344 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.539279357 | Oct 12 01:11:45 AM UTC 24 | Oct 12 01:11:55 AM UTC 24 | 232017615 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.82041560 | Oct 12 01:08:57 AM UTC 24 | Oct 12 01:11:57 AM UTC 24 | 18260619765 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2386801235 | Oct 12 01:10:36 AM UTC 24 | Oct 12 01:11:57 AM UTC 24 | 2510161965 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1270794998 | Oct 12 01:11:42 AM UTC 24 | Oct 12 01:11:58 AM UTC 24 | 733503061 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3482620713 | Oct 12 01:11:49 AM UTC 24 | Oct 12 01:11:58 AM UTC 24 | 136997408 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1239950862 | Oct 12 01:11:47 AM UTC 24 | Oct 12 01:11:58 AM UTC 24 | 389546439 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1482824151 | Oct 12 01:08:37 AM UTC 24 | Oct 12 01:11:59 AM UTC 24 | 9195738197 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.1232422392 | Oct 12 01:11:45 AM UTC 24 | Oct 12 01:11:59 AM UTC 24 | 533572119 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3751172220 | Oct 12 01:10:11 AM UTC 24 | Oct 12 01:11:59 AM UTC 24 | 1866534914 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.46581813 | Oct 12 01:09:58 AM UTC 24 | Oct 12 01:12:00 AM UTC 24 | 7186254614 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.425786199 | Oct 12 01:10:38 AM UTC 24 | Oct 12 01:12:00 AM UTC 24 | 1743451578 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.1428310285 | Oct 12 01:11:53 AM UTC 24 | Oct 12 01:12:03 AM UTC 24 | 2014903911 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.2802506469 | Oct 12 01:11:53 AM UTC 24 | Oct 12 01:12:04 AM UTC 24 | 312168126 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.698312613 | Oct 12 01:11:58 AM UTC 24 | Oct 12 01:12:05 AM UTC 24 | 451597776 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.2305588460 | Oct 12 01:11:52 AM UTC 24 | Oct 12 01:12:05 AM UTC 24 | 210124098 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.1426612415 | Oct 12 01:11:59 AM UTC 24 | Oct 12 01:12:06 AM UTC 24 | 638147307 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.4161278283 | Oct 12 01:11:53 AM UTC 24 | Oct 12 01:12:06 AM UTC 24 | 210332534 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.1802801424 | Oct 12 01:11:46 AM UTC 24 | Oct 12 01:12:07 AM UTC 24 | 1570692489 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1742548648 | Oct 12 01:09:33 AM UTC 24 | Oct 12 01:12:07 AM UTC 24 | 3096300062 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2575946059 | Oct 12 01:11:37 AM UTC 24 | Oct 12 01:12:07 AM UTC 24 | 5251658312 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1331318041 | Oct 12 01:08:53 AM UTC 24 | Oct 12 01:12:07 AM UTC 24 | 4994221169 ps |
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