| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.83 | 99.36 | 92.28 | 97.67 | 100.00 | 98.55 | 97.91 | 99.06 |
| T303 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.839574561 | Oct 15 12:41:32 AM UTC 24 | Oct 15 12:41:40 AM UTC 24 | 485647143 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2752616584 | Oct 15 12:41:33 AM UTC 24 | Oct 15 12:41:43 AM UTC 24 | 411261435 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.1483232020 | Oct 15 12:41:25 AM UTC 24 | Oct 15 12:41:43 AM UTC 24 | 548402621 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.2148522913 | Oct 15 12:41:36 AM UTC 24 | Oct 15 12:41:43 AM UTC 24 | 123490109 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2572035141 | Oct 15 12:38:18 AM UTC 24 | Oct 15 12:41:47 AM UTC 24 | 3434292994 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.3304356417 | Oct 15 12:41:37 AM UTC 24 | Oct 15 12:41:47 AM UTC 24 | 577392769 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.658818012 | Oct 15 12:39:56 AM UTC 24 | Oct 15 12:41:48 AM UTC 24 | 3374312008 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.4263947355 | Oct 15 12:41:34 AM UTC 24 | Oct 15 12:41:48 AM UTC 24 | 372268137 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.4196902961 | Oct 15 12:41:30 AM UTC 24 | Oct 15 12:41:48 AM UTC 24 | 300753004 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1661886276 | Oct 15 12:41:41 AM UTC 24 | Oct 15 12:41:49 AM UTC 24 | 128038340 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.1634963681 | Oct 15 12:41:33 AM UTC 24 | Oct 15 12:41:52 AM UTC 24 | 416473396 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.3407551691 | Oct 15 12:41:37 AM UTC 24 | Oct 15 12:41:52 AM UTC 24 | 207678099 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.1584394806 | Oct 15 12:41:41 AM UTC 24 | Oct 15 12:41:55 AM UTC 24 | 1033175730 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.2684862688 | Oct 15 12:41:44 AM UTC 24 | Oct 15 12:41:55 AM UTC 24 | 181043060 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2323258500 | Oct 15 12:41:50 AM UTC 24 | Oct 15 12:41:58 AM UTC 24 | 513796680 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.2737483467 | Oct 15 12:41:49 AM UTC 24 | Oct 15 12:41:59 AM UTC 24 | 2090785583 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2813002347 | Oct 15 12:40:14 AM UTC 24 | Oct 15 12:42:00 AM UTC 24 | 29857303569 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3119141866 | Oct 15 12:41:44 AM UTC 24 | Oct 15 12:44:12 AM UTC 24 | 2358064076 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.1412023872 | Oct 15 12:41:56 AM UTC 24 | Oct 15 12:42:04 AM UTC 24 | 357925459 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.2944703818 | Oct 15 12:41:48 AM UTC 24 | Oct 15 12:42:05 AM UTC 24 | 206504995 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1321944786 | Oct 15 12:39:59 AM UTC 24 | Oct 15 12:42:07 AM UTC 24 | 8163201024 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.2442662675 | Oct 15 12:41:53 AM UTC 24 | Oct 15 12:42:07 AM UTC 24 | 213734129 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.39078221 | Oct 15 12:39:25 AM UTC 24 | Oct 15 12:42:07 AM UTC 24 | 3035782289 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2729291016 | Oct 15 12:38:59 AM UTC 24 | Oct 15 12:42:09 AM UTC 24 | 12809627110 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1917271387 | Oct 15 12:41:44 AM UTC 24 | Oct 15 12:42:11 AM UTC 24 | 342534248 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2069755804 | Oct 15 12:39:56 AM UTC 24 | Oct 15 12:42:14 AM UTC 24 | 9832520932 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1852417180 | Oct 15 12:39:36 AM UTC 24 | Oct 15 12:42:16 AM UTC 24 | 25405286856 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.1820227408 | Oct 15 12:41:49 AM UTC 24 | Oct 15 12:42:18 AM UTC 24 | 1305292903 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1513250280 | Oct 15 12:40:33 AM UTC 24 | Oct 15 12:42:20 AM UTC 24 | 15278725910 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1398555202 | Oct 15 12:40:26 AM UTC 24 | Oct 15 12:42:23 AM UTC 24 | 5992027046 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2912398239 | Oct 15 12:39:38 AM UTC 24 | Oct 15 12:42:27 AM UTC 24 | 2042763275 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.4087175169 | Oct 15 12:37:55 AM UTC 24 | Oct 15 12:42:35 AM UTC 24 | 12332675719 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.502727669 | Oct 15 12:41:25 AM UTC 24 | Oct 15 12:42:36 AM UTC 24 | 1793969847 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1636385964 | Oct 15 12:40:31 AM UTC 24 | Oct 15 12:42:39 AM UTC 24 | 3312651221 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2103290800 | Oct 15 12:40:11 AM UTC 24 | Oct 15 12:42:43 AM UTC 24 | 3856507711 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3776053489 | Oct 15 12:40:53 AM UTC 24 | Oct 15 12:42:47 AM UTC 24 | 6147989507 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1752679133 | Oct 15 12:41:23 AM UTC 24 | Oct 15 12:42:48 AM UTC 24 | 1430925023 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1441032170 | Oct 15 12:39:28 AM UTC 24 | Oct 15 12:42:50 AM UTC 24 | 4345667872 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.928529991 | Oct 15 12:41:09 AM UTC 24 | Oct 15 12:42:50 AM UTC 24 | 6381682750 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2694860189 | Oct 15 12:40:20 AM UTC 24 | Oct 15 12:42:54 AM UTC 24 | 4299533654 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2084476312 | Oct 15 12:41:20 AM UTC 24 | Oct 15 12:42:56 AM UTC 24 | 17238280002 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1774985802 | Oct 15 12:41:41 AM UTC 24 | Oct 15 12:42:56 AM UTC 24 | 1948375288 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1166323097 | Oct 15 12:41:08 AM UTC 24 | Oct 15 12:42:57 AM UTC 24 | 10465986634 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2576473634 | Oct 15 12:40:51 AM UTC 24 | Oct 15 12:43:07 AM UTC 24 | 2587457326 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2397932194 | Oct 15 12:40:38 AM UTC 24 | Oct 15 12:43:12 AM UTC 24 | 4179702232 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3520272828 | Oct 15 12:40:37 AM UTC 24 | Oct 15 12:43:16 AM UTC 24 | 8502488514 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3743665737 | Oct 15 12:40:44 AM UTC 24 | Oct 15 12:43:22 AM UTC 24 | 13574657702 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1991632005 | Oct 15 12:40:46 AM UTC 24 | Oct 15 12:43:30 AM UTC 24 | 4408002762 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2008037338 | Oct 15 12:41:16 AM UTC 24 | Oct 15 12:43:41 AM UTC 24 | 5555498904 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.511639436 | Oct 15 12:41:51 AM UTC 24 | Oct 15 12:43:44 AM UTC 24 | 3213688792 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3498566085 | Oct 15 12:41:33 AM UTC 24 | Oct 15 12:43:46 AM UTC 24 | 1990177757 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3216797935 | Oct 15 12:39:30 AM UTC 24 | Oct 15 12:43:54 AM UTC 24 | 20088729141 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1532628044 | Oct 15 12:41:09 AM UTC 24 | Oct 15 12:43:58 AM UTC 24 | 4450048910 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.6052643 | Oct 15 12:40:16 AM UTC 24 | Oct 15 12:43:58 AM UTC 24 | 4624291889 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1178811686 | Oct 15 12:41:38 AM UTC 24 | Oct 15 12:44:04 AM UTC 24 | 7958243383 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.4131710215 | Oct 15 12:40:29 AM UTC 24 | Oct 15 12:44:14 AM UTC 24 | 19842274560 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3712108837 | Oct 15 12:41:53 AM UTC 24 | Oct 15 12:44:14 AM UTC 24 | 3952229849 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.304484947 | Oct 15 12:41:29 AM UTC 24 | Oct 15 12:44:17 AM UTC 24 | 20798119615 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3935704358 | Oct 15 12:41:11 AM UTC 24 | Oct 15 12:44:32 AM UTC 24 | 3010660947 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2615966575 | Oct 15 12:41:35 AM UTC 24 | Oct 15 12:44:47 AM UTC 24 | 5141822350 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.17250984 | Oct 15 12:41:32 AM UTC 24 | Oct 15 12:46:03 AM UTC 24 | 14250298112 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1852174236 | Oct 15 12:23:04 AM UTC 24 | Oct 15 12:23:11 AM UTC 24 | 1692625062 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.768815192 | Oct 15 12:23:04 AM UTC 24 | Oct 15 12:23:12 AM UTC 24 | 292507480 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3928935084 | Oct 15 12:23:05 AM UTC 24 | Oct 15 12:23:13 AM UTC 24 | 299093478 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3254643792 | Oct 15 12:23:05 AM UTC 24 | Oct 15 12:23:14 AM UTC 24 | 385497697 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.962834359 | Oct 15 12:23:05 AM UTC 24 | Oct 15 12:23:14 AM UTC 24 | 126335957 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2592831161 | Oct 15 12:23:04 AM UTC 24 | Oct 15 12:23:16 AM UTC 24 | 206600367 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1212086573 | Oct 15 12:23:05 AM UTC 24 | Oct 15 12:23:19 AM UTC 24 | 583369656 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3699341991 | Oct 15 12:23:12 AM UTC 24 | Oct 15 12:23:21 AM UTC 24 | 297468731 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2798617622 | Oct 15 12:23:17 AM UTC 24 | Oct 15 12:23:24 AM UTC 24 | 1273829438 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2994465272 | Oct 15 12:23:12 AM UTC 24 | Oct 15 12:23:25 AM UTC 24 | 173844087 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.164089446 | Oct 15 12:23:20 AM UTC 24 | Oct 15 12:23:27 AM UTC 24 | 288232224 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1912471835 | Oct 15 12:23:15 AM UTC 24 | Oct 15 12:23:31 AM UTC 24 | 596109205 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1929995364 | Oct 15 12:23:25 AM UTC 24 | Oct 15 12:23:33 AM UTC 24 | 1169125071 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.105650119 | Oct 15 12:23:26 AM UTC 24 | Oct 15 12:23:35 AM UTC 24 | 170298278 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3851166000 | Oct 15 12:23:22 AM UTC 24 | Oct 15 12:23:36 AM UTC 24 | 294624663 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4096869435 | Oct 15 12:23:28 AM UTC 24 | Oct 15 12:23:37 AM UTC 24 | 123557345 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4110663234 | Oct 15 12:23:32 AM UTC 24 | Oct 15 12:23:40 AM UTC 24 | 209301886 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1005922038 | Oct 15 12:23:15 AM UTC 24 | Oct 15 12:23:40 AM UTC 24 | 2163078381 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2234743191 | Oct 15 12:23:33 AM UTC 24 | Oct 15 12:23:43 AM UTC 24 | 227821191 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1133948786 | Oct 15 12:23:41 AM UTC 24 | Oct 15 12:23:48 AM UTC 24 | 372590823 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.873873248 | Oct 15 12:23:04 AM UTC 24 | Oct 15 12:23:49 AM UTC 24 | 2256201325 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3152503534 | Oct 15 12:23:04 AM UTC 24 | Oct 15 12:23:50 AM UTC 24 | 358491159 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2527398 | Oct 15 12:23:44 AM UTC 24 | Oct 15 12:23:51 AM UTC 24 | 545519389 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.179878118 | Oct 15 12:23:37 AM UTC 24 | Oct 15 12:23:51 AM UTC 24 | 164847708 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3859602618 | Oct 15 12:23:41 AM UTC 24 | Oct 15 12:23:52 AM UTC 24 | 535187252 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3850844650 | Oct 15 12:23:15 AM UTC 24 | Oct 15 12:23:55 AM UTC 24 | 3702640499 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2523717382 | Oct 15 12:23:50 AM UTC 24 | Oct 15 12:23:59 AM UTC 24 | 440029420 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3479630692 | Oct 15 12:23:51 AM UTC 24 | Oct 15 12:23:59 AM UTC 24 | 326800316 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3149428985 | Oct 15 12:23:36 AM UTC 24 | Oct 15 12:23:59 AM UTC 24 | 587357309 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3523444634 | Oct 15 12:23:49 AM UTC 24 | Oct 15 12:23:59 AM UTC 24 | 168682664 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3867242714 | Oct 15 12:23:52 AM UTC 24 | Oct 15 12:23:59 AM UTC 24 | 301854811 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3786049091 | Oct 15 12:23:52 AM UTC 24 | Oct 15 12:24:05 AM UTC 24 | 326025446 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3515689204 | Oct 15 12:23:59 AM UTC 24 | Oct 15 12:24:07 AM UTC 24 | 292729689 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1090144610 | Oct 15 12:24:01 AM UTC 24 | Oct 15 12:24:07 AM UTC 24 | 1073579574 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2084434236 | Oct 15 12:24:00 AM UTC 24 | Oct 15 12:24:09 AM UTC 24 | 169343727 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4031870540 | Oct 15 12:23:56 AM UTC 24 | Oct 15 12:24:11 AM UTC 24 | 881648880 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3969556224 | Oct 15 12:24:01 AM UTC 24 | Oct 15 12:24:12 AM UTC 24 | 176050038 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3643632912 | Oct 15 12:24:09 AM UTC 24 | Oct 15 12:24:15 AM UTC 24 | 206583202 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3370164368 | Oct 15 12:24:09 AM UTC 24 | Oct 15 12:24:17 AM UTC 24 | 127846463 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4099811038 | Oct 15 12:24:09 AM UTC 24 | Oct 15 12:24:18 AM UTC 24 | 164278163 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3696868152 | Oct 15 12:23:53 AM UTC 24 | Oct 15 12:24:18 AM UTC 24 | 1352232868 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3928259094 | Oct 15 12:24:09 AM UTC 24 | Oct 15 12:24:18 AM UTC 24 | 309873645 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2008948799 | Oct 15 12:24:15 AM UTC 24 | Oct 15 12:24:23 AM UTC 24 | 169099393 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2988649682 | Oct 15 12:24:18 AM UTC 24 | Oct 15 12:24:25 AM UTC 24 | 439160358 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2888553373 | Oct 15 12:24:20 AM UTC 24 | Oct 15 12:24:27 AM UTC 24 | 1282760723 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2777654526 | Oct 15 12:24:19 AM UTC 24 | Oct 15 12:24:29 AM UTC 24 | 133158155 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3201413611 | Oct 15 12:24:12 AM UTC 24 | Oct 15 12:24:30 AM UTC 24 | 544227081 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.647583391 | Oct 15 12:24:20 AM UTC 24 | Oct 15 12:24:30 AM UTC 24 | 165649815 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.233478989 | Oct 15 12:24:25 AM UTC 24 | Oct 15 12:24:32 AM UTC 24 | 593265760 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1247667397 | Oct 15 12:24:25 AM UTC 24 | Oct 15 12:24:33 AM UTC 24 | 298147410 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2175224541 | Oct 15 12:24:27 AM UTC 24 | Oct 15 12:24:35 AM UTC 24 | 272883227 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4156609899 | Oct 15 12:24:30 AM UTC 24 | Oct 15 12:24:40 AM UTC 24 | 812795262 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3017101724 | Oct 15 12:24:31 AM UTC 24 | Oct 15 12:24:40 AM UTC 24 | 293389790 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1092345126 | Oct 15 12:24:33 AM UTC 24 | Oct 15 12:24:41 AM UTC 24 | 128035242 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.886683419 | Oct 15 12:24:33 AM UTC 24 | Oct 15 12:24:44 AM UTC 24 | 304358185 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1644808066 | Oct 15 12:24:10 AM UTC 24 | Oct 15 12:24:49 AM UTC 24 | 3744604649 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1366953258 | Oct 15 12:24:42 AM UTC 24 | Oct 15 12:24:50 AM UTC 24 | 385812043 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3976826874 | Oct 15 12:24:40 AM UTC 24 | Oct 15 12:24:51 AM UTC 24 | 336082074 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1006949856 | Oct 15 12:24:45 AM UTC 24 | Oct 15 12:24:54 AM UTC 24 | 168499101 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1767637766 | Oct 15 12:24:29 AM UTC 24 | Oct 15 12:24:54 AM UTC 24 | 2220628446 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2829598440 | Oct 15 12:23:37 AM UTC 24 | Oct 15 12:25:00 AM UTC 24 | 1115299239 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.905298020 | Oct 15 12:24:49 AM UTC 24 | Oct 15 12:25:00 AM UTC 24 | 173282531 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3755344445 | Oct 15 12:24:57 AM UTC 24 | Oct 15 12:25:04 AM UTC 24 | 171549720 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1568309268 | Oct 15 12:24:57 AM UTC 24 | Oct 15 12:25:08 AM UTC 24 | 449170508 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1437551234 | Oct 15 12:24:57 AM UTC 24 | Oct 15 12:25:08 AM UTC 24 | 290752872 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3873707770 | Oct 15 12:24:36 AM UTC 24 | Oct 15 12:25:09 AM UTC 24 | 1639724350 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2296759280 | Oct 15 12:24:57 AM UTC 24 | Oct 15 12:25:11 AM UTC 24 | 367033115 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2876144322 | Oct 15 12:25:01 AM UTC 24 | Oct 15 12:25:13 AM UTC 24 | 816307559 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.282490007 | Oct 15 12:24:50 AM UTC 24 | Oct 15 12:25:14 AM UTC 24 | 579447080 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.120098261 | Oct 15 12:25:10 AM UTC 24 | Oct 15 12:25:19 AM UTC 24 | 124478897 ps | ||
| T404 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2755793652 | Oct 15 12:25:10 AM UTC 24 | Oct 15 12:25:19 AM UTC 24 | 163705778 ps | ||
| T405 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.166695260 | Oct 15 12:25:10 AM UTC 24 | Oct 15 12:25:19 AM UTC 24 | 133306092 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4238114754 | Oct 15 12:23:59 AM UTC 24 | Oct 15 12:25:21 AM UTC 24 | 1031072190 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1639771345 | Oct 15 12:24:41 AM UTC 24 | Oct 15 12:25:22 AM UTC 24 | 307384418 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3316839773 | Oct 15 12:25:15 AM UTC 24 | Oct 15 12:25:23 AM UTC 24 | 371071198 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.491549586 | Oct 15 12:25:12 AM UTC 24 | Oct 15 12:25:24 AM UTC 24 | 557841529 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.887770733 | Oct 15 12:25:24 AM UTC 24 | Oct 15 12:25:32 AM UTC 24 | 416584050 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.39534013 | Oct 15 12:25:20 AM UTC 24 | Oct 15 12:25:29 AM UTC 24 | 2226636391 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2603614505 | Oct 15 12:25:20 AM UTC 24 | Oct 15 12:25:31 AM UTC 24 | 182509250 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1307722023 | Oct 15 12:25:24 AM UTC 24 | Oct 15 12:25:33 AM UTC 24 | 910733997 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3702164211 | Oct 15 12:25:22 AM UTC 24 | Oct 15 12:25:34 AM UTC 24 | 1068921179 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3611952227 | Oct 15 12:24:12 AM UTC 24 | Oct 15 12:25:35 AM UTC 24 | 539603064 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1639905203 | Oct 15 12:25:01 AM UTC 24 | Oct 15 12:25:37 AM UTC 24 | 576090169 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2669053790 | Oct 15 12:25:29 AM UTC 24 | Oct 15 12:25:37 AM UTC 24 | 410185234 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.650858757 | Oct 15 12:25:11 AM UTC 24 | Oct 15 12:25:40 AM UTC 24 | 2563023329 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.247169395 | Oct 15 12:25:35 AM UTC 24 | Oct 15 12:25:43 AM UTC 24 | 288658070 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.844013295 | Oct 15 12:25:36 AM UTC 24 | Oct 15 12:25:44 AM UTC 24 | 1006139340 ps | ||
| T416 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3376467534 | Oct 15 12:25:32 AM UTC 24 | Oct 15 12:25:44 AM UTC 24 | 540134351 ps | ||
| T417 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.379461711 | Oct 15 12:25:38 AM UTC 24 | Oct 15 12:25:47 AM UTC 24 | 426132444 ps | ||
| T418 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4161213395 | Oct 15 12:25:41 AM UTC 24 | Oct 15 12:25:53 AM UTC 24 | 2097057651 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3391908124 | Oct 15 12:24:31 AM UTC 24 | Oct 15 12:25:54 AM UTC 24 | 269731421 ps | ||
| T419 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2594279235 | Oct 15 12:25:45 AM UTC 24 | Oct 15 12:25:54 AM UTC 24 | 183803657 ps | ||
| T420 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1380299884 | Oct 15 12:25:45 AM UTC 24 | Oct 15 12:25:55 AM UTC 24 | 165932146 ps | ||
| T421 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2564728862 | Oct 15 12:25:48 AM UTC 24 | Oct 15 12:25:59 AM UTC 24 | 240418781 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.204527428 | Oct 15 12:25:05 AM UTC 24 | Oct 15 12:25:59 AM UTC 24 | 393707240 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.825157080 | Oct 15 12:25:55 AM UTC 24 | Oct 15 12:26:03 AM UTC 24 | 205839674 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2659835995 | Oct 15 12:25:20 AM UTC 24 | Oct 15 12:26:06 AM UTC 24 | 822318857 ps | ||
| T422 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1269574400 | Oct 15 12:26:00 AM UTC 24 | Oct 15 12:26:07 AM UTC 24 | 813057251 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2457239103 | Oct 15 12:24:57 AM UTC 24 | Oct 15 12:26:08 AM UTC 24 | 973587533 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1567903760 | Oct 15 12:26:00 AM UTC 24 | Oct 15 12:26:08 AM UTC 24 | 554383404 ps | ||
| T424 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1251639280 | Oct 15 12:25:54 AM UTC 24 | Oct 15 12:26:13 AM UTC 24 | 2078844394 ps | ||
| T425 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.603512805 | Oct 15 12:25:34 AM UTC 24 | Oct 15 12:26:13 AM UTC 24 | 386318785 ps | ||
| T426 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4202576819 | Oct 15 12:26:09 AM UTC 24 | Oct 15 12:26:16 AM UTC 24 | 169813997 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3655670438 | Oct 15 12:25:39 AM UTC 24 | Oct 15 12:26:16 AM UTC 24 | 2178801622 ps | ||
| T427 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3915315718 | Oct 15 12:26:09 AM UTC 24 | Oct 15 12:26:17 AM UTC 24 | 535756038 ps | ||
| T428 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.104371912 | Oct 15 12:26:07 AM UTC 24 | Oct 15 12:26:20 AM UTC 24 | 170426128 ps | ||
| T429 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3576583583 | Oct 15 12:25:32 AM UTC 24 | Oct 15 12:26:25 AM UTC 24 | 12530134671 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1855143009 | Oct 15 12:26:17 AM UTC 24 | Oct 15 12:26:26 AM UTC 24 | 304405106 ps | ||
| T430 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1312483356 | Oct 15 12:26:18 AM UTC 24 | Oct 15 12:26:26 AM UTC 24 | 961798947 ps | ||
| T431 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3796571703 | Oct 15 12:26:16 AM UTC 24 | Oct 15 12:26:27 AM UTC 24 | 194837341 ps | ||
| T432 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.25165027 | Oct 15 12:26:16 AM UTC 24 | Oct 15 12:26:31 AM UTC 24 | 594399717 ps | ||
| T433 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3278896185 | Oct 15 12:25:54 AM UTC 24 | Oct 15 12:26:31 AM UTC 24 | 1165128616 ps | ||
| T434 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3410957988 | Oct 15 12:26:20 AM UTC 24 | Oct 15 12:26:31 AM UTC 24 | 3844186916 ps | ||
| T435 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4090910421 | Oct 15 12:26:26 AM UTC 24 | Oct 15 12:26:33 AM UTC 24 | 958578767 ps | ||
| T436 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1971788887 | Oct 15 12:26:26 AM UTC 24 | Oct 15 12:26:35 AM UTC 24 | 417066947 ps | ||
| T437 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.320960974 | Oct 15 12:26:28 AM UTC 24 | Oct 15 12:26:39 AM UTC 24 | 195767331 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2172246530 | Oct 15 12:26:25 AM UTC 24 | Oct 15 12:26:39 AM UTC 24 | 164282878 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2226342017 | Oct 15 12:25:14 AM UTC 24 | Oct 15 12:26:41 AM UTC 24 | 890560795 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4253847710 | Oct 15 12:26:16 AM UTC 24 | Oct 15 12:26:42 AM UTC 24 | 1549739155 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3150596812 | Oct 15 12:26:32 AM UTC 24 | Oct 15 12:26:43 AM UTC 24 | 434692370 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2158661982 | Oct 15 12:26:35 AM UTC 24 | Oct 15 12:26:43 AM UTC 24 | 555389018 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.350376284 | Oct 15 12:26:34 AM UTC 24 | Oct 15 12:26:43 AM UTC 24 | 289180695 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3447635019 | Oct 15 12:26:04 AM UTC 24 | Oct 15 12:26:48 AM UTC 24 | 1623796753 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2618658219 | Oct 15 12:26:40 AM UTC 24 | Oct 15 12:26:50 AM UTC 24 | 886443341 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.126581167 | Oct 15 12:26:43 AM UTC 24 | Oct 15 12:26:51 AM UTC 24 | 386257398 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2843749881 | Oct 15 12:26:43 AM UTC 24 | Oct 15 12:26:55 AM UTC 24 | 547465670 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4183523424 | Oct 15 12:26:44 AM UTC 24 | Oct 15 12:26:55 AM UTC 24 | 187775860 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1714392168 | Oct 15 12:25:23 AM UTC 24 | Oct 15 12:26:56 AM UTC 24 | 539766349 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2394343635 | Oct 15 12:26:42 AM UTC 24 | Oct 15 12:26:57 AM UTC 24 | 372238022 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.60945890 | Oct 15 12:26:32 AM UTC 24 | Oct 15 12:26:59 AM UTC 24 | 407420803 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2614886967 | Oct 15 12:26:25 AM UTC 24 | Oct 15 12:27:00 AM UTC 24 | 593763303 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1117905330 | Oct 15 12:26:51 AM UTC 24 | Oct 15 12:27:03 AM UTC 24 | 961546709 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.151936252 | Oct 15 12:26:56 AM UTC 24 | Oct 15 12:27:04 AM UTC 24 | 299534775 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.236431376 | Oct 15 12:26:56 AM UTC 24 | Oct 15 12:27:04 AM UTC 24 | 558718435 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2049041072 | Oct 15 12:26:57 AM UTC 24 | Oct 15 12:27:05 AM UTC 24 | 380325841 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4168261283 | Oct 15 12:25:54 AM UTC 24 | Oct 15 12:27:09 AM UTC 24 | 1476040713 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3486881988 | Oct 15 12:26:17 AM UTC 24 | Oct 15 12:27:11 AM UTC 24 | 1321806062 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1044292340 | Oct 15 12:25:44 AM UTC 24 | Oct 15 12:27:14 AM UTC 24 | 1027411773 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.327289956 | Oct 15 12:26:50 AM UTC 24 | Oct 15 12:27:22 AM UTC 24 | 590012178 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.213964369 | Oct 15 12:26:40 AM UTC 24 | Oct 15 12:27:26 AM UTC 24 | 834127680 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3314713185 | Oct 15 12:26:43 AM UTC 24 | Oct 15 12:27:28 AM UTC 24 | 656723663 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.196053210 | Oct 15 12:26:08 AM UTC 24 | Oct 15 12:27:32 AM UTC 24 | 963962144 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3720014779 | Oct 15 12:26:52 AM UTC 24 | Oct 15 12:27:35 AM UTC 24 | 243903006 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.699697766 | Oct 15 12:26:26 AM UTC 24 | Oct 15 12:27:42 AM UTC 24 | 321421904 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3025339680 | Oct 15 12:26:33 AM UTC 24 | Oct 15 12:28:08 AM UTC 24 | 730891394 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1824586905 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1889094264 ps |
| CPU time | 7.26 seconds |
| Started | Oct 15 12:37:13 AM UTC 24 |
| Finished | Oct 15 12:37:21 AM UTC 24 |
| Peak memory | 223520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824586905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1824586905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1892577240 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3084055981 ps |
| CPU time | 115.59 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:39:02 AM UTC 24 |
| Peak memory | 232856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1892577240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.rom_ctrl_stress_all_with_rand_reset.1892577240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.99870090 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3175628067 ps |
| CPU time | 51.06 seconds |
| Started | Oct 15 12:37:23 AM UTC 24 |
| Finished | Oct 15 12:38:16 AM UTC 24 |
| Peak memory | 245900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99870090 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.99870090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.1900998303 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1072584470 ps |
| CPU time | 15.43 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:21 AM UTC 24 |
| Peak memory | 223452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900998303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1900998303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4225474595 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 7742917718 ps |
| CPU time | 126.4 seconds |
| Started | Oct 15 12:37:27 AM UTC 24 |
| Finished | Oct 15 12:39:36 AM UTC 24 |
| Peak memory | 259208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225474595 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.4225474595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.978631550 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 127083077 ps |
| CPU time | 5.14 seconds |
| Started | Oct 15 12:37:13 AM UTC 24 |
| Finished | Oct 15 12:37:19 AM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978631550 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.978631550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1231738443 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 579145419 ps |
| CPU time | 6.36 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:12 AM UTC 24 |
| Peak memory | 223836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231738443 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1231738443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.492661463 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 343583888 ps |
| CPU time | 20.67 seconds |
| Started | Oct 15 12:37:26 AM UTC 24 |
| Finished | Oct 15 12:37:48 AM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492661463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.492661463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4238114754 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1031072190 ps |
| CPU time | 79.96 seconds |
| Started | Oct 15 12:23:59 AM UTC 24 |
| Finished | Oct 15 12:25:21 AM UTC 24 |
| Peak memory | 227420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238114754 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.4238114754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.1876198876 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 580719113 ps |
| CPU time | 16.47 seconds |
| Started | Oct 15 12:37:20 AM UTC 24 |
| Finished | Oct 15 12:37:38 AM UTC 24 |
| Peak memory | 223452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876198876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1876198876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.661516563 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 182968169 ps |
| CPU time | 7.19 seconds |
| Started | Oct 15 12:37:38 AM UTC 24 |
| Finished | Oct 15 12:37:47 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661516563 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.661516563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.4034343187 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2495960640 ps |
| CPU time | 120.12 seconds |
| Started | Oct 15 12:37:21 AM UTC 24 |
| Finished | Oct 15 12:39:24 AM UTC 24 |
| Peak memory | 258848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034343187 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.4034343187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2163018750 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1274760752 ps |
| CPU time | 20.45 seconds |
| Started | Oct 15 12:37:07 AM UTC 24 |
| Finished | Oct 15 12:37:28 AM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216301875 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.2163018750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.873873248 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2256201325 ps |
| CPU time | 43.27 seconds |
| Started | Oct 15 12:23:04 AM UTC 24 |
| Finished | Oct 15 12:23:49 AM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873873248 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.873873248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1044292340 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1027411773 ps |
| CPU time | 88.31 seconds |
| Started | Oct 15 12:25:44 AM UTC 24 |
| Finished | Oct 15 12:27:14 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044292340 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.1044292340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2443951925 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 332696423 ps |
| CPU time | 19.01 seconds |
| Started | Oct 15 12:37:22 AM UTC 24 |
| Finished | Oct 15 12:37:43 AM UTC 24 |
| Peak memory | 224832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244395192 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.2443951925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3642310809 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11792002697 ps |
| CPU time | 89.79 seconds |
| Started | Oct 15 12:37:24 AM UTC 24 |
| Finished | Oct 15 12:38:55 AM UTC 24 |
| Peak memory | 243096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3642310809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3642310809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.150573678 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 731503522 ps |
| CPU time | 13.61 seconds |
| Started | Oct 15 12:40:00 AM UTC 24 |
| Finished | Oct 15 12:40:15 AM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150573678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.150573678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3025339680 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 730891394 ps |
| CPU time | 93.06 seconds |
| Started | Oct 15 12:26:33 AM UTC 24 |
| Finished | Oct 15 12:28:08 AM UTC 24 |
| Peak memory | 220148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025339680 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.3025339680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3020847022 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 4467788008 ps |
| CPU time | 85.69 seconds |
| Started | Oct 15 12:37:45 AM UTC 24 |
| Finished | Oct 15 12:39:13 AM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3020847022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3020847022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.962834359 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 126335957 ps |
| CPU time | 7.59 seconds |
| Started | Oct 15 12:23:05 AM UTC 24 |
| Finished | Oct 15 12:23:14 AM UTC 24 |
| Peak memory | 220084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962834359 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.962834359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.1355824862 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 472650014 ps |
| CPU time | 18.7 seconds |
| Started | Oct 15 12:37:34 AM UTC 24 |
| Finished | Oct 15 12:37:54 AM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135582486 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.1355824862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2397932194 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4179702232 ps |
| CPU time | 151.67 seconds |
| Started | Oct 15 12:40:38 AM UTC 24 |
| Finished | Oct 15 12:43:12 AM UTC 24 |
| Peak memory | 243104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2397932194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2397932194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.2729594561 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 245065898 ps |
| CPU time | 7.25 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:13 AM UTC 24 |
| Peak memory | 223536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729594561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2729594561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.3672336998 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 300125584 ps |
| CPU time | 14.74 seconds |
| Started | Oct 15 12:37:44 AM UTC 24 |
| Finished | Oct 15 12:38:00 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672336998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3672336998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3254643792 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 385497697 ps |
| CPU time | 7.34 seconds |
| Started | Oct 15 12:23:05 AM UTC 24 |
| Finished | Oct 15 12:23:14 AM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254643792 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.3254643792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1212086573 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 583369656 ps |
| CPU time | 12.84 seconds |
| Started | Oct 15 12:23:05 AM UTC 24 |
| Finished | Oct 15 12:23:19 AM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212086573 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.1212086573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3699341991 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 297468731 ps |
| CPU time | 7.79 seconds |
| Started | Oct 15 12:23:12 AM UTC 24 |
| Finished | Oct 15 12:23:21 AM UTC 24 |
| Peak memory | 224232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3699341991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r om_ctrl_csr_mem_rw_with_rand_reset.3699341991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3928935084 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 299093478 ps |
| CPU time | 7.06 seconds |
| Started | Oct 15 12:23:05 AM UTC 24 |
| Finished | Oct 15 12:23:13 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928935084 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3928935084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.768815192 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 292507480 ps |
| CPU time | 6.91 seconds |
| Started | Oct 15 12:23:04 AM UTC 24 |
| Finished | Oct 15 12:23:12 AM UTC 24 |
| Peak memory | 220020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768815192 -assert nopostpr oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.768815192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1852174236 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1692625062 ps |
| CPU time | 6.08 seconds |
| Started | Oct 15 12:23:04 AM UTC 24 |
| Finished | Oct 15 12:23:11 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852174236 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.1852174236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2994465272 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 173844087 ps |
| CPU time | 11.6 seconds |
| Started | Oct 15 12:23:12 AM UTC 24 |
| Finished | Oct 15 12:23:25 AM UTC 24 |
| Peak memory | 227452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994465272 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.2994465272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2592831161 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 206600367 ps |
| CPU time | 10.56 seconds |
| Started | Oct 15 12:23:04 AM UTC 24 |
| Finished | Oct 15 12:23:16 AM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592831161 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2592831161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3152503534 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 358491159 ps |
| CPU time | 44.27 seconds |
| Started | Oct 15 12:23:04 AM UTC 24 |
| Finished | Oct 15 12:23:50 AM UTC 24 |
| Peak memory | 222120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152503534 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.3152503534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4096869435 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 123557345 ps |
| CPU time | 7.28 seconds |
| Started | Oct 15 12:23:28 AM UTC 24 |
| Finished | Oct 15 12:23:37 AM UTC 24 |
| Peak memory | 227704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096869435 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.4096869435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.105650119 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 170298278 ps |
| CPU time | 8.29 seconds |
| Started | Oct 15 12:23:26 AM UTC 24 |
| Finished | Oct 15 12:23:35 AM UTC 24 |
| Peak memory | 220404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105650119 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.105650119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3851166000 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 294624663 ps |
| CPU time | 13.33 seconds |
| Started | Oct 15 12:23:22 AM UTC 24 |
| Finished | Oct 15 12:23:36 AM UTC 24 |
| Peak memory | 220004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851166000 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.3851166000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2234743191 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 227821191 ps |
| CPU time | 8.89 seconds |
| Started | Oct 15 12:23:33 AM UTC 24 |
| Finished | Oct 15 12:23:43 AM UTC 24 |
| Peak memory | 226536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2234743191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r om_ctrl_csr_mem_rw_with_rand_reset.2234743191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1929995364 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1169125071 ps |
| CPU time | 6.83 seconds |
| Started | Oct 15 12:23:25 AM UTC 24 |
| Finished | Oct 15 12:23:33 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929995364 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1929995364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.164089446 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 288232224 ps |
| CPU time | 6.03 seconds |
| Started | Oct 15 12:23:20 AM UTC 24 |
| Finished | Oct 15 12:23:27 AM UTC 24 |
| Peak memory | 220280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164089446 -assert nopostpr oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.164089446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2798617622 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1273829438 ps |
| CPU time | 5.91 seconds |
| Started | Oct 15 12:23:17 AM UTC 24 |
| Finished | Oct 15 12:23:24 AM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798617622 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.2798617622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1005922038 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 2163078381 ps |
| CPU time | 24.38 seconds |
| Started | Oct 15 12:23:15 AM UTC 24 |
| Finished | Oct 15 12:23:40 AM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005922038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.1005922038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4110663234 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 209301886 ps |
| CPU time | 6.63 seconds |
| Started | Oct 15 12:23:32 AM UTC 24 |
| Finished | Oct 15 12:23:40 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110663234 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.4110663234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1912471835 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 596109205 ps |
| CPU time | 15.18 seconds |
| Started | Oct 15 12:23:15 AM UTC 24 |
| Finished | Oct 15 12:23:31 AM UTC 24 |
| Peak memory | 224344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912471835 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1912471835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3850844650 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 3702640499 ps |
| CPU time | 39.33 seconds |
| Started | Oct 15 12:23:15 AM UTC 24 |
| Finished | Oct 15 12:23:55 AM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850844650 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.3850844650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2669053790 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 410185234 ps |
| CPU time | 7.07 seconds |
| Started | Oct 15 12:25:29 AM UTC 24 |
| Finished | Oct 15 12:25:37 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2669053790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. rom_ctrl_csr_mem_rw_with_rand_reset.2669053790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.887770733 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 416584050 ps |
| CPU time | 6.43 seconds |
| Started | Oct 15 12:25:24 AM UTC 24 |
| Finished | Oct 15 12:25:32 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887770733 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.887770733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2659835995 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 822318857 ps |
| CPU time | 44.26 seconds |
| Started | Oct 15 12:25:20 AM UTC 24 |
| Finished | Oct 15 12:26:06 AM UTC 24 |
| Peak memory | 220344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659835995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.2659835995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1307722023 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 910733997 ps |
| CPU time | 7.66 seconds |
| Started | Oct 15 12:25:24 AM UTC 24 |
| Finished | Oct 15 12:25:33 AM UTC 24 |
| Peak memory | 227712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307722023 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.1307722023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3702164211 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1068921179 ps |
| CPU time | 10.82 seconds |
| Started | Oct 15 12:25:22 AM UTC 24 |
| Finished | Oct 15 12:25:34 AM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702164211 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3702164211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1714392168 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 539766349 ps |
| CPU time | 90.46 seconds |
| Started | Oct 15 12:25:23 AM UTC 24 |
| Finished | Oct 15 12:26:56 AM UTC 24 |
| Peak memory | 222132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714392168 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.1714392168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.379461711 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 426132444 ps |
| CPU time | 8.11 seconds |
| Started | Oct 15 12:25:38 AM UTC 24 |
| Finished | Oct 15 12:25:47 AM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=379461711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.r om_ctrl_csr_mem_rw_with_rand_reset.379461711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.247169395 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 288658070 ps |
| CPU time | 7.59 seconds |
| Started | Oct 15 12:25:35 AM UTC 24 |
| Finished | Oct 15 12:25:43 AM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247169395 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.247169395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3576583583 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 12530134671 ps |
| CPU time | 50.64 seconds |
| Started | Oct 15 12:25:32 AM UTC 24 |
| Finished | Oct 15 12:26:25 AM UTC 24 |
| Peak memory | 220216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576583583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.3576583583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.844013295 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1006139340 ps |
| CPU time | 7.08 seconds |
| Started | Oct 15 12:25:36 AM UTC 24 |
| Finished | Oct 15 12:25:44 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844013295 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.844013295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3376467534 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 540134351 ps |
| CPU time | 10.46 seconds |
| Started | Oct 15 12:25:32 AM UTC 24 |
| Finished | Oct 15 12:25:44 AM UTC 24 |
| Peak memory | 226308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376467534 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3376467534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.603512805 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 386318785 ps |
| CPU time | 38.28 seconds |
| Started | Oct 15 12:25:34 AM UTC 24 |
| Finished | Oct 15 12:26:13 AM UTC 24 |
| Peak memory | 227452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603512805 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.603512805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2564728862 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 240418781 ps |
| CPU time | 9.32 seconds |
| Started | Oct 15 12:25:48 AM UTC 24 |
| Finished | Oct 15 12:25:59 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2564728862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. rom_ctrl_csr_mem_rw_with_rand_reset.2564728862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1380299884 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 165932146 ps |
| CPU time | 8.86 seconds |
| Started | Oct 15 12:25:45 AM UTC 24 |
| Finished | Oct 15 12:25:55 AM UTC 24 |
| Peak memory | 227488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380299884 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1380299884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3655670438 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2178801622 ps |
| CPU time | 35.73 seconds |
| Started | Oct 15 12:25:39 AM UTC 24 |
| Finished | Oct 15 12:26:16 AM UTC 24 |
| Peak memory | 220216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655670438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.3655670438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2594279235 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 183803657 ps |
| CPU time | 7.71 seconds |
| Started | Oct 15 12:25:45 AM UTC 24 |
| Finished | Oct 15 12:25:54 AM UTC 24 |
| Peak memory | 220016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594279235 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.2594279235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4161213395 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2097057651 ps |
| CPU time | 11.25 seconds |
| Started | Oct 15 12:25:41 AM UTC 24 |
| Finished | Oct 15 12:25:53 AM UTC 24 |
| Peak memory | 226308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161213395 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.4161213395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1567903760 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 554383404 ps |
| CPU time | 7.46 seconds |
| Started | Oct 15 12:26:00 AM UTC 24 |
| Finished | Oct 15 12:26:08 AM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1567903760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. rom_ctrl_csr_mem_rw_with_rand_reset.1567903760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.825157080 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 205839674 ps |
| CPU time | 6.1 seconds |
| Started | Oct 15 12:25:55 AM UTC 24 |
| Finished | Oct 15 12:26:03 AM UTC 24 |
| Peak memory | 227444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825157080 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.825157080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3278896185 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1165128616 ps |
| CPU time | 35.01 seconds |
| Started | Oct 15 12:25:54 AM UTC 24 |
| Finished | Oct 15 12:26:31 AM UTC 24 |
| Peak memory | 220300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278896185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.3278896185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1269574400 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 813057251 ps |
| CPU time | 6.81 seconds |
| Started | Oct 15 12:26:00 AM UTC 24 |
| Finished | Oct 15 12:26:07 AM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269574400 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.1269574400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1251639280 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2078844394 ps |
| CPU time | 17.14 seconds |
| Started | Oct 15 12:25:54 AM UTC 24 |
| Finished | Oct 15 12:26:13 AM UTC 24 |
| Peak memory | 227468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251639280 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1251639280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4168261283 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1476040713 ps |
| CPU time | 72.74 seconds |
| Started | Oct 15 12:25:54 AM UTC 24 |
| Finished | Oct 15 12:27:09 AM UTC 24 |
| Peak memory | 222196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168261283 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.4168261283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3796571703 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 194837341 ps |
| CPU time | 9.79 seconds |
| Started | Oct 15 12:26:16 AM UTC 24 |
| Finished | Oct 15 12:26:27 AM UTC 24 |
| Peak memory | 227512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3796571703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. rom_ctrl_csr_mem_rw_with_rand_reset.3796571703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4202576819 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 169813997 ps |
| CPU time | 6.26 seconds |
| Started | Oct 15 12:26:09 AM UTC 24 |
| Finished | Oct 15 12:26:16 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202576819 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4202576819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3447635019 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1623796753 ps |
| CPU time | 43.11 seconds |
| Started | Oct 15 12:26:04 AM UTC 24 |
| Finished | Oct 15 12:26:48 AM UTC 24 |
| Peak memory | 220344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447635019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.3447635019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3915315718 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 535756038 ps |
| CPU time | 6.92 seconds |
| Started | Oct 15 12:26:09 AM UTC 24 |
| Finished | Oct 15 12:26:17 AM UTC 24 |
| Peak memory | 227452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915315718 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.3915315718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.104371912 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 170426128 ps |
| CPU time | 12.06 seconds |
| Started | Oct 15 12:26:07 AM UTC 24 |
| Finished | Oct 15 12:26:20 AM UTC 24 |
| Peak memory | 226496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104371912 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.104371912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.196053210 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 963962144 ps |
| CPU time | 82.37 seconds |
| Started | Oct 15 12:26:08 AM UTC 24 |
| Finished | Oct 15 12:27:32 AM UTC 24 |
| Peak memory | 227772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196053210 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.196053210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3410957988 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3844186916 ps |
| CPU time | 10.02 seconds |
| Started | Oct 15 12:26:20 AM UTC 24 |
| Finished | Oct 15 12:26:31 AM UTC 24 |
| Peak memory | 222320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3410957988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. rom_ctrl_csr_mem_rw_with_rand_reset.3410957988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1855143009 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 304405106 ps |
| CPU time | 7.37 seconds |
| Started | Oct 15 12:26:17 AM UTC 24 |
| Finished | Oct 15 12:26:26 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855143009 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1855143009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4253847710 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1549739155 ps |
| CPU time | 25.35 seconds |
| Started | Oct 15 12:26:16 AM UTC 24 |
| Finished | Oct 15 12:26:42 AM UTC 24 |
| Peak memory | 220148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253847710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.4253847710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1312483356 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 961798947 ps |
| CPU time | 6.64 seconds |
| Started | Oct 15 12:26:18 AM UTC 24 |
| Finished | Oct 15 12:26:26 AM UTC 24 |
| Peak memory | 226664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312483356 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.1312483356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.25165027 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 594399717 ps |
| CPU time | 13.47 seconds |
| Started | Oct 15 12:26:16 AM UTC 24 |
| Finished | Oct 15 12:26:31 AM UTC 24 |
| Peak memory | 227776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25165027 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.25165027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3486881988 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1321806062 ps |
| CPU time | 52.26 seconds |
| Started | Oct 15 12:26:17 AM UTC 24 |
| Finished | Oct 15 12:27:11 AM UTC 24 |
| Peak memory | 220340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486881988 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.3486881988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.320960974 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 195767331 ps |
| CPU time | 10.57 seconds |
| Started | Oct 15 12:26:28 AM UTC 24 |
| Finished | Oct 15 12:26:39 AM UTC 24 |
| Peak memory | 227508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=320960974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.r om_ctrl_csr_mem_rw_with_rand_reset.320960974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4090910421 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 958578767 ps |
| CPU time | 5.29 seconds |
| Started | Oct 15 12:26:26 AM UTC 24 |
| Finished | Oct 15 12:26:33 AM UTC 24 |
| Peak memory | 227488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090910421 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4090910421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2614886967 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 593763303 ps |
| CPU time | 33.37 seconds |
| Started | Oct 15 12:26:25 AM UTC 24 |
| Finished | Oct 15 12:27:00 AM UTC 24 |
| Peak memory | 220344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614886967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.2614886967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1971788887 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 417066947 ps |
| CPU time | 7.01 seconds |
| Started | Oct 15 12:26:26 AM UTC 24 |
| Finished | Oct 15 12:26:35 AM UTC 24 |
| Peak memory | 226644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971788887 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.1971788887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2172246530 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 164282878 ps |
| CPU time | 13.06 seconds |
| Started | Oct 15 12:26:25 AM UTC 24 |
| Finished | Oct 15 12:26:39 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172246530 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2172246530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.699697766 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 321421904 ps |
| CPU time | 73.97 seconds |
| Started | Oct 15 12:26:26 AM UTC 24 |
| Finished | Oct 15 12:27:42 AM UTC 24 |
| Peak memory | 222128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699697766 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.699697766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2618658219 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 886443341 ps |
| CPU time | 8.45 seconds |
| Started | Oct 15 12:26:40 AM UTC 24 |
| Finished | Oct 15 12:26:50 AM UTC 24 |
| Peak memory | 227508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2618658219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. rom_ctrl_csr_mem_rw_with_rand_reset.2618658219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.350376284 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 289180695 ps |
| CPU time | 8.18 seconds |
| Started | Oct 15 12:26:34 AM UTC 24 |
| Finished | Oct 15 12:26:43 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350376284 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.350376284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.60945890 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 407420803 ps |
| CPU time | 25.93 seconds |
| Started | Oct 15 12:26:32 AM UTC 24 |
| Finished | Oct 15 12:26:59 AM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60945890 -assert nopostproc +U VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.60945890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2158661982 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 555389018 ps |
| CPU time | 6.95 seconds |
| Started | Oct 15 12:26:35 AM UTC 24 |
| Finished | Oct 15 12:26:43 AM UTC 24 |
| Peak memory | 227452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158661982 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.2158661982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3150596812 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 434692370 ps |
| CPU time | 9.97 seconds |
| Started | Oct 15 12:26:32 AM UTC 24 |
| Finished | Oct 15 12:26:43 AM UTC 24 |
| Peak memory | 226436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150596812 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3150596812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4183523424 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 187775860 ps |
| CPU time | 9.24 seconds |
| Started | Oct 15 12:26:44 AM UTC 24 |
| Finished | Oct 15 12:26:55 AM UTC 24 |
| Peak memory | 227772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4183523424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. rom_ctrl_csr_mem_rw_with_rand_reset.4183523424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.126581167 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 386257398 ps |
| CPU time | 6.84 seconds |
| Started | Oct 15 12:26:43 AM UTC 24 |
| Finished | Oct 15 12:26:51 AM UTC 24 |
| Peak memory | 227744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126581167 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.126581167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.213964369 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 834127680 ps |
| CPU time | 44.92 seconds |
| Started | Oct 15 12:26:40 AM UTC 24 |
| Finished | Oct 15 12:27:26 AM UTC 24 |
| Peak memory | 220352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213964369 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.213964369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2843749881 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 547465670 ps |
| CPU time | 10.25 seconds |
| Started | Oct 15 12:26:43 AM UTC 24 |
| Finished | Oct 15 12:26:55 AM UTC 24 |
| Peak memory | 227452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843749881 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.2843749881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2394343635 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 372238022 ps |
| CPU time | 13.32 seconds |
| Started | Oct 15 12:26:42 AM UTC 24 |
| Finished | Oct 15 12:26:57 AM UTC 24 |
| Peak memory | 226564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394343635 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2394343635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3314713185 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 656723663 ps |
| CPU time | 43.63 seconds |
| Started | Oct 15 12:26:43 AM UTC 24 |
| Finished | Oct 15 12:27:28 AM UTC 24 |
| Peak memory | 220404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314713185 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.3314713185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2049041072 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 380325841 ps |
| CPU time | 7.31 seconds |
| Started | Oct 15 12:26:57 AM UTC 24 |
| Finished | Oct 15 12:27:05 AM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2049041072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. rom_ctrl_csr_mem_rw_with_rand_reset.2049041072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.151936252 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 299534775 ps |
| CPU time | 6.93 seconds |
| Started | Oct 15 12:26:56 AM UTC 24 |
| Finished | Oct 15 12:27:04 AM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151936252 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.151936252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.327289956 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 590012178 ps |
| CPU time | 30.81 seconds |
| Started | Oct 15 12:26:50 AM UTC 24 |
| Finished | Oct 15 12:27:22 AM UTC 24 |
| Peak memory | 220096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327289956 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.327289956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.236431376 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 558718435 ps |
| CPU time | 7.4 seconds |
| Started | Oct 15 12:26:56 AM UTC 24 |
| Finished | Oct 15 12:27:04 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236431376 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.236431376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1117905330 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 961546709 ps |
| CPU time | 11.34 seconds |
| Started | Oct 15 12:26:51 AM UTC 24 |
| Finished | Oct 15 12:27:03 AM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117905330 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1117905330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3720014779 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 243903006 ps |
| CPU time | 41.47 seconds |
| Started | Oct 15 12:26:52 AM UTC 24 |
| Finished | Oct 15 12:27:35 AM UTC 24 |
| Peak memory | 220404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720014779 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.3720014779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3479630692 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 326800316 ps |
| CPU time | 6.7 seconds |
| Started | Oct 15 12:23:51 AM UTC 24 |
| Finished | Oct 15 12:23:59 AM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479630692 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.3479630692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2523717382 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 440029420 ps |
| CPU time | 7.57 seconds |
| Started | Oct 15 12:23:50 AM UTC 24 |
| Finished | Oct 15 12:23:59 AM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523717382 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.2523717382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2527398 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 545519389 ps |
| CPU time | 6.49 seconds |
| Started | Oct 15 12:23:44 AM UTC 24 |
| Finished | Oct 15 12:23:51 AM UTC 24 |
| Peak memory | 220404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527398 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.2527398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3867242714 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 301854811 ps |
| CPU time | 6.33 seconds |
| Started | Oct 15 12:23:52 AM UTC 24 |
| Finished | Oct 15 12:23:59 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3867242714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r om_ctrl_csr_mem_rw_with_rand_reset.3867242714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3523444634 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 168682664 ps |
| CPU time | 8.98 seconds |
| Started | Oct 15 12:23:49 AM UTC 24 |
| Finished | Oct 15 12:23:59 AM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523444634 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3523444634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3859602618 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 535187252 ps |
| CPU time | 10.08 seconds |
| Started | Oct 15 12:23:41 AM UTC 24 |
| Finished | Oct 15 12:23:52 AM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859602618 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.3859602618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1133948786 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 372590823 ps |
| CPU time | 6.81 seconds |
| Started | Oct 15 12:23:41 AM UTC 24 |
| Finished | Oct 15 12:23:48 AM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133948786 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.1133948786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3149428985 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 587357309 ps |
| CPU time | 21.32 seconds |
| Started | Oct 15 12:23:36 AM UTC 24 |
| Finished | Oct 15 12:23:59 AM UTC 24 |
| Peak memory | 220344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149428985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.3149428985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3786049091 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 326025446 ps |
| CPU time | 11.65 seconds |
| Started | Oct 15 12:23:52 AM UTC 24 |
| Finished | Oct 15 12:24:05 AM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786049091 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.3786049091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.179878118 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 164847708 ps |
| CPU time | 12.77 seconds |
| Started | Oct 15 12:23:37 AM UTC 24 |
| Finished | Oct 15 12:23:51 AM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179878118 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.179878118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2829598440 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1115299239 ps |
| CPU time | 80.53 seconds |
| Started | Oct 15 12:23:37 AM UTC 24 |
| Finished | Oct 15 12:25:00 AM UTC 24 |
| Peak memory | 222392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829598440 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.2829598440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4099811038 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 164278163 ps |
| CPU time | 8.13 seconds |
| Started | Oct 15 12:24:09 AM UTC 24 |
| Finished | Oct 15 12:24:18 AM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099811038 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.4099811038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3370164368 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 127846463 ps |
| CPU time | 7.08 seconds |
| Started | Oct 15 12:24:09 AM UTC 24 |
| Finished | Oct 15 12:24:17 AM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370164368 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.3370164368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3969556224 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 176050038 ps |
| CPU time | 9.99 seconds |
| Started | Oct 15 12:24:01 AM UTC 24 |
| Finished | Oct 15 12:24:12 AM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969556224 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.3969556224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3928259094 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 309873645 ps |
| CPU time | 8.18 seconds |
| Started | Oct 15 12:24:09 AM UTC 24 |
| Finished | Oct 15 12:24:18 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3928259094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r om_ctrl_csr_mem_rw_with_rand_reset.3928259094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1090144610 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1073579574 ps |
| CPU time | 5.64 seconds |
| Started | Oct 15 12:24:01 AM UTC 24 |
| Finished | Oct 15 12:24:07 AM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090144610 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1090144610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2084434236 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 169343727 ps |
| CPU time | 7.73 seconds |
| Started | Oct 15 12:24:00 AM UTC 24 |
| Finished | Oct 15 12:24:09 AM UTC 24 |
| Peak memory | 220256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084434236 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.2084434236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3515689204 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 292729689 ps |
| CPU time | 6.43 seconds |
| Started | Oct 15 12:23:59 AM UTC 24 |
| Finished | Oct 15 12:24:07 AM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515689204 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.3515689204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3696868152 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1352232868 ps |
| CPU time | 23.44 seconds |
| Started | Oct 15 12:23:53 AM UTC 24 |
| Finished | Oct 15 12:24:18 AM UTC 24 |
| Peak memory | 220088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696868152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.3696868152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3643632912 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 206583202 ps |
| CPU time | 4.76 seconds |
| Started | Oct 15 12:24:09 AM UTC 24 |
| Finished | Oct 15 12:24:15 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643632912 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.3643632912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4031870540 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 881648880 ps |
| CPU time | 13.5 seconds |
| Started | Oct 15 12:23:56 AM UTC 24 |
| Finished | Oct 15 12:24:11 AM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031870540 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4031870540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1247667397 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 298147410 ps |
| CPU time | 6.03 seconds |
| Started | Oct 15 12:24:25 AM UTC 24 |
| Finished | Oct 15 12:24:33 AM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247667397 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.1247667397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.647583391 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 165649815 ps |
| CPU time | 9.19 seconds |
| Started | Oct 15 12:24:20 AM UTC 24 |
| Finished | Oct 15 12:24:30 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647583391 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.647583391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2777654526 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 133158155 ps |
| CPU time | 8.56 seconds |
| Started | Oct 15 12:24:19 AM UTC 24 |
| Finished | Oct 15 12:24:29 AM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777654526 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.2777654526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2175224541 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 272883227 ps |
| CPU time | 7.59 seconds |
| Started | Oct 15 12:24:27 AM UTC 24 |
| Finished | Oct 15 12:24:35 AM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2175224541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r om_ctrl_csr_mem_rw_with_rand_reset.2175224541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2888553373 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1282760723 ps |
| CPU time | 6.8 seconds |
| Started | Oct 15 12:24:20 AM UTC 24 |
| Finished | Oct 15 12:24:27 AM UTC 24 |
| Peak memory | 220396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888553373 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2888553373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2988649682 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 439160358 ps |
| CPU time | 5.82 seconds |
| Started | Oct 15 12:24:18 AM UTC 24 |
| Finished | Oct 15 12:24:25 AM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988649682 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.2988649682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2008948799 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 169099393 ps |
| CPU time | 6.07 seconds |
| Started | Oct 15 12:24:15 AM UTC 24 |
| Finished | Oct 15 12:24:23 AM UTC 24 |
| Peak memory | 220268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008948799 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.2008948799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1644808066 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 3744604649 ps |
| CPU time | 36.77 seconds |
| Started | Oct 15 12:24:10 AM UTC 24 |
| Finished | Oct 15 12:24:49 AM UTC 24 |
| Peak memory | 222272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644808066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.1644808066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.233478989 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 593265760 ps |
| CPU time | 5.87 seconds |
| Started | Oct 15 12:24:25 AM UTC 24 |
| Finished | Oct 15 12:24:32 AM UTC 24 |
| Peak memory | 226692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233478989 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.233478989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3201413611 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 544227081 ps |
| CPU time | 15.95 seconds |
| Started | Oct 15 12:24:12 AM UTC 24 |
| Finished | Oct 15 12:24:30 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201413611 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3201413611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3611952227 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 539603064 ps |
| CPU time | 80.89 seconds |
| Started | Oct 15 12:24:12 AM UTC 24 |
| Finished | Oct 15 12:25:35 AM UTC 24 |
| Peak memory | 222120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611952227 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.3611952227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.886683419 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 304358185 ps |
| CPU time | 10.23 seconds |
| Started | Oct 15 12:24:33 AM UTC 24 |
| Finished | Oct 15 12:24:44 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=886683419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ro m_ctrl_csr_mem_rw_with_rand_reset.886683419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3017101724 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 293389790 ps |
| CPU time | 7.76 seconds |
| Started | Oct 15 12:24:31 AM UTC 24 |
| Finished | Oct 15 12:24:40 AM UTC 24 |
| Peak memory | 227448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017101724 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3017101724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1767637766 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2220628446 ps |
| CPU time | 24.29 seconds |
| Started | Oct 15 12:24:29 AM UTC 24 |
| Finished | Oct 15 12:24:54 AM UTC 24 |
| Peak memory | 220536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767637766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.1767637766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1092345126 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 128035242 ps |
| CPU time | 6.98 seconds |
| Started | Oct 15 12:24:33 AM UTC 24 |
| Finished | Oct 15 12:24:41 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092345126 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.1092345126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4156609899 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 812795262 ps |
| CPU time | 8.64 seconds |
| Started | Oct 15 12:24:30 AM UTC 24 |
| Finished | Oct 15 12:24:40 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156609899 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4156609899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3391908124 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 269731421 ps |
| CPU time | 80.96 seconds |
| Started | Oct 15 12:24:31 AM UTC 24 |
| Finished | Oct 15 12:25:54 AM UTC 24 |
| Peak memory | 227444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391908124 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.3391908124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.905298020 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 173282531 ps |
| CPU time | 9.67 seconds |
| Started | Oct 15 12:24:49 AM UTC 24 |
| Finished | Oct 15 12:25:00 AM UTC 24 |
| Peak memory | 222192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=905298020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.ro m_ctrl_csr_mem_rw_with_rand_reset.905298020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1366953258 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 385812043 ps |
| CPU time | 6.3 seconds |
| Started | Oct 15 12:24:42 AM UTC 24 |
| Finished | Oct 15 12:24:50 AM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366953258 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1366953258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3873707770 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1639724350 ps |
| CPU time | 31.52 seconds |
| Started | Oct 15 12:24:36 AM UTC 24 |
| Finished | Oct 15 12:25:09 AM UTC 24 |
| Peak memory | 220344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873707770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.3873707770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1006949856 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 168499101 ps |
| CPU time | 7.35 seconds |
| Started | Oct 15 12:24:45 AM UTC 24 |
| Finished | Oct 15 12:24:54 AM UTC 24 |
| Peak memory | 227452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006949856 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.1006949856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3976826874 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 336082074 ps |
| CPU time | 10.19 seconds |
| Started | Oct 15 12:24:40 AM UTC 24 |
| Finished | Oct 15 12:24:51 AM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976826874 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3976826874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1639771345 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 307384418 ps |
| CPU time | 39.47 seconds |
| Started | Oct 15 12:24:41 AM UTC 24 |
| Finished | Oct 15 12:25:22 AM UTC 24 |
| Peak memory | 222440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639771345 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.1639771345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1568309268 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 449170508 ps |
| CPU time | 9.74 seconds |
| Started | Oct 15 12:24:57 AM UTC 24 |
| Finished | Oct 15 12:25:08 AM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1568309268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r om_ctrl_csr_mem_rw_with_rand_reset.1568309268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3755344445 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 171549720 ps |
| CPU time | 6.45 seconds |
| Started | Oct 15 12:24:57 AM UTC 24 |
| Finished | Oct 15 12:25:04 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755344445 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3755344445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.282490007 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 579447080 ps |
| CPU time | 22.53 seconds |
| Started | Oct 15 12:24:50 AM UTC 24 |
| Finished | Oct 15 12:25:14 AM UTC 24 |
| Peak memory | 220288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282490007 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.282490007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1437551234 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 290752872 ps |
| CPU time | 10.32 seconds |
| Started | Oct 15 12:24:57 AM UTC 24 |
| Finished | Oct 15 12:25:08 AM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437551234 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.1437551234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2296759280 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 367033115 ps |
| CPU time | 13.13 seconds |
| Started | Oct 15 12:24:57 AM UTC 24 |
| Finished | Oct 15 12:25:11 AM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296759280 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2296759280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2457239103 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 973587533 ps |
| CPU time | 69.69 seconds |
| Started | Oct 15 12:24:57 AM UTC 24 |
| Finished | Oct 15 12:26:08 AM UTC 24 |
| Peak memory | 227524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457239103 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.2457239103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.166695260 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 133306092 ps |
| CPU time | 7.22 seconds |
| Started | Oct 15 12:25:10 AM UTC 24 |
| Finished | Oct 15 12:25:19 AM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=166695260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ro m_ctrl_csr_mem_rw_with_rand_reset.166695260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.120098261 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 124478897 ps |
| CPU time | 7.11 seconds |
| Started | Oct 15 12:25:10 AM UTC 24 |
| Finished | Oct 15 12:25:19 AM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120098261 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.120098261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1639905203 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 576090169 ps |
| CPU time | 34.22 seconds |
| Started | Oct 15 12:25:01 AM UTC 24 |
| Finished | Oct 15 12:25:37 AM UTC 24 |
| Peak memory | 220268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639905203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.1639905203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2755793652 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 163705778 ps |
| CPU time | 7.27 seconds |
| Started | Oct 15 12:25:10 AM UTC 24 |
| Finished | Oct 15 12:25:19 AM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755793652 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.2755793652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2876144322 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 816307559 ps |
| CPU time | 11.07 seconds |
| Started | Oct 15 12:25:01 AM UTC 24 |
| Finished | Oct 15 12:25:13 AM UTC 24 |
| Peak memory | 227712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876144322 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2876144322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.204527428 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 393707240 ps |
| CPU time | 52.24 seconds |
| Started | Oct 15 12:25:05 AM UTC 24 |
| Finished | Oct 15 12:25:59 AM UTC 24 |
| Peak memory | 227452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204527428 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.204527428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2603614505 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 182509250 ps |
| CPU time | 9.99 seconds |
| Started | Oct 15 12:25:20 AM UTC 24 |
| Finished | Oct 15 12:25:31 AM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2603614505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r om_ctrl_csr_mem_rw_with_rand_reset.2603614505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3316839773 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 371071198 ps |
| CPU time | 6.97 seconds |
| Started | Oct 15 12:25:15 AM UTC 24 |
| Finished | Oct 15 12:25:23 AM UTC 24 |
| Peak memory | 227744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316839773 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3316839773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.650858757 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 2563023329 ps |
| CPU time | 28 seconds |
| Started | Oct 15 12:25:11 AM UTC 24 |
| Finished | Oct 15 12:25:40 AM UTC 24 |
| Peak memory | 220224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650858757 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.650858757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.39534013 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2226636391 ps |
| CPU time | 7.81 seconds |
| Started | Oct 15 12:25:20 AM UTC 24 |
| Finished | Oct 15 12:25:29 AM UTC 24 |
| Peak memory | 220160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39534013 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.39534013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.491549586 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 557841529 ps |
| CPU time | 11.08 seconds |
| Started | Oct 15 12:25:12 AM UTC 24 |
| Finished | Oct 15 12:25:24 AM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491549586 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.491549586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2226342017 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 890560795 ps |
| CPU time | 85.73 seconds |
| Started | Oct 15 12:25:14 AM UTC 24 |
| Finished | Oct 15 12:26:41 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226342017 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.2226342017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.1711103639 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 165260546 ps |
| CPU time | 8.13 seconds |
| Started | Oct 15 12:37:05 AM UTC 24 |
| Finished | Oct 15 12:37:15 AM UTC 24 |
| Peak memory | 223596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711103639 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1711103639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3170815640 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2925521525 ps |
| CPU time | 139.33 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:39:26 AM UTC 24 |
| Peak memory | 246996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170815640 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.3170815640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.251407283 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 357209922 ps |
| CPU time | 119.04 seconds |
| Started | Oct 15 12:37:05 AM UTC 24 |
| Finished | Oct 15 12:39:07 AM UTC 24 |
| Peak memory | 258788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251407283 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.251407283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2847888844 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 199341811 ps |
| CPU time | 13.69 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:19 AM UTC 24 |
| Peak memory | 223628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284788884 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.2847888844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3556820224 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 126002940 ps |
| CPU time | 4.96 seconds |
| Started | Oct 15 12:37:08 AM UTC 24 |
| Finished | Oct 15 12:37:14 AM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556820224 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3556820224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1753956046 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3359889720 ps |
| CPU time | 169.23 seconds |
| Started | Oct 15 12:37:08 AM UTC 24 |
| Finished | Oct 15 12:40:00 AM UTC 24 |
| Peak memory | 259212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753956046 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.1753956046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2150143899 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 295452555 ps |
| CPU time | 14.31 seconds |
| Started | Oct 15 12:37:08 AM UTC 24 |
| Finished | Oct 15 12:37:23 AM UTC 24 |
| Peak memory | 223452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150143899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2150143899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.1491619242 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 428140219 ps |
| CPU time | 7.3 seconds |
| Started | Oct 15 12:37:08 AM UTC 24 |
| Finished | Oct 15 12:37:16 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491619242 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1491619242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1518418488 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 284453451 ps |
| CPU time | 55.79 seconds |
| Started | Oct 15 12:37:08 AM UTC 24 |
| Finished | Oct 15 12:38:05 AM UTC 24 |
| Peak memory | 258784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518418488 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1518418488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.506519131 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 171288691 ps |
| CPU time | 7.47 seconds |
| Started | Oct 15 12:37:05 AM UTC 24 |
| Finished | Oct 15 12:37:14 AM UTC 24 |
| Peak memory | 223440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506519131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32k B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.506519131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.2583707814 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 371208039 ps |
| CPU time | 6 seconds |
| Started | Oct 15 12:37:46 AM UTC 24 |
| Finished | Oct 15 12:37:54 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583707814 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2583707814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1899256504 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 7477536463 ps |
| CPU time | 144.89 seconds |
| Started | Oct 15 12:37:43 AM UTC 24 |
| Finished | Oct 15 12:40:10 AM UTC 24 |
| Peak memory | 259224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899256504 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.1899256504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3234327064 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 935096191 ps |
| CPU time | 6.37 seconds |
| Started | Oct 15 12:37:41 AM UTC 24 |
| Finished | Oct 15 12:37:48 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234327064 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3234327064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.3951487387 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 130115211 ps |
| CPU time | 11.26 seconds |
| Started | Oct 15 12:37:41 AM UTC 24 |
| Finished | Oct 15 12:37:53 AM UTC 24 |
| Peak memory | 223440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395148738 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.3951487387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.913083884 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 128988310 ps |
| CPU time | 6.28 seconds |
| Started | Oct 15 12:37:50 AM UTC 24 |
| Finished | Oct 15 12:37:57 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913083884 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.913083884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2813139909 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 6233532315 ps |
| CPU time | 106.86 seconds |
| Started | Oct 15 12:37:48 AM UTC 24 |
| Finished | Oct 15 12:39:37 AM UTC 24 |
| Peak memory | 246340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813139909 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.2813139909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1370674016 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 291094400 ps |
| CPU time | 17.05 seconds |
| Started | Oct 15 12:37:48 AM UTC 24 |
| Finished | Oct 15 12:38:07 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370674016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1370674016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.3031086336 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 587750024 ps |
| CPU time | 8.38 seconds |
| Started | Oct 15 12:37:47 AM UTC 24 |
| Finished | Oct 15 12:37:57 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031086336 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3031086336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.1748858009 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1734550039 ps |
| CPU time | 11.94 seconds |
| Started | Oct 15 12:37:46 AM UTC 24 |
| Finished | Oct 15 12:38:00 AM UTC 24 |
| Peak memory | 223636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174885800 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.1748858009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2124618144 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5069586159 ps |
| CPU time | 68.9 seconds |
| Started | Oct 15 12:37:49 AM UTC 24 |
| Finished | Oct 15 12:38:59 AM UTC 24 |
| Peak memory | 232848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2124618144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2124618144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3817502767 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 599727499 ps |
| CPU time | 6.27 seconds |
| Started | Oct 15 12:37:55 AM UTC 24 |
| Finished | Oct 15 12:38:03 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817502767 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3817502767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4227507326 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 8720344863 ps |
| CPU time | 115.31 seconds |
| Started | Oct 15 12:37:54 AM UTC 24 |
| Finished | Oct 15 12:39:52 AM UTC 24 |
| Peak memory | 256260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227507326 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.4227507326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.2746828604 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 545163638 ps |
| CPU time | 13.62 seconds |
| Started | Oct 15 12:37:55 AM UTC 24 |
| Finished | Oct 15 12:38:10 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746828604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2746828604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.3839814669 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 137795738 ps |
| CPU time | 9.85 seconds |
| Started | Oct 15 12:37:52 AM UTC 24 |
| Finished | Oct 15 12:38:04 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839814669 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3839814669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.3889954852 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 396967255 ps |
| CPU time | 12.55 seconds |
| Started | Oct 15 12:37:52 AM UTC 24 |
| Finished | Oct 15 12:38:06 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388995485 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.3889954852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.4087175169 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 12332675719 ps |
| CPU time | 275.5 seconds |
| Started | Oct 15 12:37:55 AM UTC 24 |
| Finished | Oct 15 12:42:35 AM UTC 24 |
| Peak memory | 235104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4087175169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.rom_ctrl_stress_all_with_rand_reset.4087175169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.3392413286 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 577531814 ps |
| CPU time | 5.27 seconds |
| Started | Oct 15 12:38:01 AM UTC 24 |
| Finished | Oct 15 12:38:07 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392413286 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3392413286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.515755237 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 8390841275 ps |
| CPU time | 132.27 seconds |
| Started | Oct 15 12:37:57 AM UTC 24 |
| Finished | Oct 15 12:40:12 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515755237 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.515755237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.3009271798 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 386622495 ps |
| CPU time | 11.92 seconds |
| Started | Oct 15 12:37:57 AM UTC 24 |
| Finished | Oct 15 12:38:11 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009271798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3009271798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.2381438798 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 316539019 ps |
| CPU time | 5.77 seconds |
| Started | Oct 15 12:37:56 AM UTC 24 |
| Finished | Oct 15 12:38:03 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381438798 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2381438798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.4225503132 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 165213312 ps |
| CPU time | 8.91 seconds |
| Started | Oct 15 12:37:56 AM UTC 24 |
| Finished | Oct 15 12:38:06 AM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422550313 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.4225503132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2618712424 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 6231681221 ps |
| CPU time | 121.54 seconds |
| Started | Oct 15 12:37:58 AM UTC 24 |
| Finished | Oct 15 12:40:02 AM UTC 24 |
| Peak memory | 234976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2618712424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.rom_ctrl_stress_all_with_rand_reset.2618712424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.3470891830 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 2610389369 ps |
| CPU time | 10.69 seconds |
| Started | Oct 15 12:38:07 AM UTC 24 |
| Finished | Oct 15 12:38:19 AM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470891830 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3470891830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4270092173 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 8962646555 ps |
| CPU time | 69.23 seconds |
| Started | Oct 15 12:38:04 AM UTC 24 |
| Finished | Oct 15 12:39:15 AM UTC 24 |
| Peak memory | 258792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270092173 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.4270092173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.1308452450 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 208776761 ps |
| CPU time | 14 seconds |
| Started | Oct 15 12:38:05 AM UTC 24 |
| Finished | Oct 15 12:38:20 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308452450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1308452450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1129460934 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1073280412 ps |
| CPU time | 11.81 seconds |
| Started | Oct 15 12:38:04 AM UTC 24 |
| Finished | Oct 15 12:38:17 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129460934 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1129460934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2274084463 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 456579693 ps |
| CPU time | 16.32 seconds |
| Started | Oct 15 12:38:01 AM UTC 24 |
| Finished | Oct 15 12:38:18 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227408446 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.2274084463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1498869081 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 14651619103 ps |
| CPU time | 114.51 seconds |
| Started | Oct 15 12:38:06 AM UTC 24 |
| Finished | Oct 15 12:40:03 AM UTC 24 |
| Peak memory | 243104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1498869081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1498869081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.1791514576 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 486129635 ps |
| CPU time | 5.72 seconds |
| Started | Oct 15 12:38:14 AM UTC 24 |
| Finished | Oct 15 12:38:21 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791514576 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1791514576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1006397893 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2222010526 ps |
| CPU time | 107.5 seconds |
| Started | Oct 15 12:38:08 AM UTC 24 |
| Finished | Oct 15 12:39:58 AM UTC 24 |
| Peak memory | 223680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006397893 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.1006397893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.15700078 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 296565854 ps |
| CPU time | 11.36 seconds |
| Started | Oct 15 12:38:10 AM UTC 24 |
| Finished | Oct 15 12:38:23 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15700078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_ TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.15700078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3587342042 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 137809404 ps |
| CPU time | 6.88 seconds |
| Started | Oct 15 12:38:08 AM UTC 24 |
| Finished | Oct 15 12:38:16 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587342042 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3587342042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3216365720 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1234286806 ps |
| CPU time | 19.84 seconds |
| Started | Oct 15 12:38:07 AM UTC 24 |
| Finished | Oct 15 12:38:29 AM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321636572 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.3216365720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1928751454 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 5159678390 ps |
| CPU time | 112.94 seconds |
| Started | Oct 15 12:38:11 AM UTC 24 |
| Finished | Oct 15 12:40:07 AM UTC 24 |
| Peak memory | 235168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1928751454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1928751454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.4272365019 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 165187541 ps |
| CPU time | 6.72 seconds |
| Started | Oct 15 12:38:20 AM UTC 24 |
| Finished | Oct 15 12:38:28 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272365019 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4272365019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2572035141 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 3434292994 ps |
| CPU time | 205.5 seconds |
| Started | Oct 15 12:38:18 AM UTC 24 |
| Finished | Oct 15 12:41:47 AM UTC 24 |
| Peak memory | 244000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572035141 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.2572035141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.309996226 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1075579939 ps |
| CPU time | 14.97 seconds |
| Started | Oct 15 12:38:19 AM UTC 24 |
| Finished | Oct 15 12:38:35 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309996226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.309996226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.3383976348 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 178872543 ps |
| CPU time | 6.91 seconds |
| Started | Oct 15 12:38:18 AM UTC 24 |
| Finished | Oct 15 12:38:26 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383976348 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3383976348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.3450503598 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 622934355 ps |
| CPU time | 21.89 seconds |
| Started | Oct 15 12:38:17 AM UTC 24 |
| Finished | Oct 15 12:38:40 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345050359 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.3450503598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.527227413 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1779541095 ps |
| CPU time | 60.07 seconds |
| Started | Oct 15 12:38:20 AM UTC 24 |
| Finished | Oct 15 12:39:22 AM UTC 24 |
| Peak memory | 232924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=527227413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 16.rom_ctrl_stress_all_with_rand_reset.527227413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.4004597133 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 372845326 ps |
| CPU time | 6.65 seconds |
| Started | Oct 15 12:38:28 AM UTC 24 |
| Finished | Oct 15 12:38:36 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004597133 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4004597133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2313546036 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 4219486721 ps |
| CPU time | 180.56 seconds |
| Started | Oct 15 12:38:24 AM UTC 24 |
| Finished | Oct 15 12:41:28 AM UTC 24 |
| Peak memory | 259412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313546036 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.2313546036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.3915965261 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 557491907 ps |
| CPU time | 13.43 seconds |
| Started | Oct 15 12:38:25 AM UTC 24 |
| Finished | Oct 15 12:38:40 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915965261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3915965261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.2102121828 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 177957414 ps |
| CPU time | 9.04 seconds |
| Started | Oct 15 12:38:22 AM UTC 24 |
| Finished | Oct 15 12:38:32 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102121828 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2102121828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3358582393 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 195913807 ps |
| CPU time | 14.36 seconds |
| Started | Oct 15 12:38:21 AM UTC 24 |
| Finished | Oct 15 12:38:37 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335858239 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.3358582393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2820410491 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 3995698217 ps |
| CPU time | 181.49 seconds |
| Started | Oct 15 12:38:26 AM UTC 24 |
| Finished | Oct 15 12:41:31 AM UTC 24 |
| Peak memory | 233056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2820410491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2820410491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.894568947 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 142002884 ps |
| CPU time | 6.96 seconds |
| Started | Oct 15 12:38:41 AM UTC 24 |
| Finished | Oct 15 12:38:49 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894568947 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.894568947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3595821467 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 7869918224 ps |
| CPU time | 108.15 seconds |
| Started | Oct 15 12:38:36 AM UTC 24 |
| Finished | Oct 15 12:40:26 AM UTC 24 |
| Peak memory | 259212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595821467 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.3595821467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2360802658 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1491575542 ps |
| CPU time | 14.23 seconds |
| Started | Oct 15 12:38:37 AM UTC 24 |
| Finished | Oct 15 12:38:52 AM UTC 24 |
| Peak memory | 223576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360802658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2360802658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.2731044612 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 134290055 ps |
| CPU time | 8.96 seconds |
| Started | Oct 15 12:38:34 AM UTC 24 |
| Finished | Oct 15 12:38:44 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731044612 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2731044612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3812638337 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 152780397 ps |
| CPU time | 9.47 seconds |
| Started | Oct 15 12:38:29 AM UTC 24 |
| Finished | Oct 15 12:38:40 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381263833 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.3812638337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3835524104 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1058256607 ps |
| CPU time | 47.12 seconds |
| Started | Oct 15 12:38:38 AM UTC 24 |
| Finished | Oct 15 12:39:26 AM UTC 24 |
| Peak memory | 230724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3835524104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3835524104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.1872133553 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 126150300 ps |
| CPU time | 7.44 seconds |
| Started | Oct 15 12:38:49 AM UTC 24 |
| Finished | Oct 15 12:38:58 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872133553 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1872133553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3836678813 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1709425020 ps |
| CPU time | 88.84 seconds |
| Started | Oct 15 12:38:42 AM UTC 24 |
| Finished | Oct 15 12:40:13 AM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836678813 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.3836678813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.3624666520 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 515360421 ps |
| CPU time | 11.96 seconds |
| Started | Oct 15 12:38:44 AM UTC 24 |
| Finished | Oct 15 12:38:57 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624666520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3624666520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.3879221748 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 548848730 ps |
| CPU time | 14.28 seconds |
| Started | Oct 15 12:38:41 AM UTC 24 |
| Finished | Oct 15 12:38:56 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879221748 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3879221748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2507399503 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 512081908 ps |
| CPU time | 26.82 seconds |
| Started | Oct 15 12:38:41 AM UTC 24 |
| Finished | Oct 15 12:39:09 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250739950 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.2507399503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.885480767 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 21386791266 ps |
| CPU time | 146.26 seconds |
| Started | Oct 15 12:38:45 AM UTC 24 |
| Finished | Oct 15 12:41:14 AM UTC 24 |
| Peak memory | 247324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=885480767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 19.rom_ctrl_stress_all_with_rand_reset.885480767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2255425334 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2505188900 ps |
| CPU time | 147.98 seconds |
| Started | Oct 15 12:37:13 AM UTC 24 |
| Finished | Oct 15 12:39:43 AM UTC 24 |
| Peak memory | 246296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255425334 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.2255425334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1608102214 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1028044905 ps |
| CPU time | 13.06 seconds |
| Started | Oct 15 12:37:13 AM UTC 24 |
| Finished | Oct 15 12:37:27 AM UTC 24 |
| Peak memory | 223452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608102214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1608102214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.973306733 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 427367777 ps |
| CPU time | 8.94 seconds |
| Started | Oct 15 12:37:13 AM UTC 24 |
| Finished | Oct 15 12:37:23 AM UTC 24 |
| Peak memory | 223768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973306733 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.973306733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.550606760 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 285901023 ps |
| CPU time | 111.64 seconds |
| Started | Oct 15 12:37:13 AM UTC 24 |
| Finished | Oct 15 12:39:07 AM UTC 24 |
| Peak memory | 258772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550606760 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.550606760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3551206352 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 592085693 ps |
| CPU time | 8.08 seconds |
| Started | Oct 15 12:37:13 AM UTC 24 |
| Finished | Oct 15 12:37:22 AM UTC 24 |
| Peak memory | 223520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551206352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3551206352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3940796017 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 329432765 ps |
| CPU time | 18.9 seconds |
| Started | Oct 15 12:37:13 AM UTC 24 |
| Finished | Oct 15 12:37:33 AM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394079601 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.3940796017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2759637775 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 7268200498 ps |
| CPU time | 153.46 seconds |
| Started | Oct 15 12:37:13 AM UTC 24 |
| Finished | Oct 15 12:39:49 AM UTC 24 |
| Peak memory | 241048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2759637775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2759637775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.1805346993 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 555638506 ps |
| CPU time | 6.29 seconds |
| Started | Oct 15 12:38:59 AM UTC 24 |
| Finished | Oct 15 12:39:06 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805346993 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1805346993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2453307180 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2519856804 ps |
| CPU time | 63.03 seconds |
| Started | Oct 15 12:38:57 AM UTC 24 |
| Finished | Oct 15 12:40:01 AM UTC 24 |
| Peak memory | 258924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453307180 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.2453307180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.1847356531 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 655100958 ps |
| CPU time | 9.81 seconds |
| Started | Oct 15 12:38:57 AM UTC 24 |
| Finished | Oct 15 12:39:08 AM UTC 24 |
| Peak memory | 223340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847356531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1847356531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.1658787384 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 740443764 ps |
| CPU time | 7.41 seconds |
| Started | Oct 15 12:38:56 AM UTC 24 |
| Finished | Oct 15 12:39:04 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658787384 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1658787384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2338191392 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 454803833 ps |
| CPU time | 18.82 seconds |
| Started | Oct 15 12:38:52 AM UTC 24 |
| Finished | Oct 15 12:39:13 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233819139 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.2338191392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2729291016 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 12809627110 ps |
| CPU time | 187.59 seconds |
| Started | Oct 15 12:38:59 AM UTC 24 |
| Finished | Oct 15 12:42:09 AM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2729291016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2729291016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.3925236256 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 224376246 ps |
| CPU time | 8.59 seconds |
| Started | Oct 15 12:39:13 AM UTC 24 |
| Finished | Oct 15 12:39:22 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925236256 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3925236256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3656289255 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2508043472 ps |
| CPU time | 127.28 seconds |
| Started | Oct 15 12:39:05 AM UTC 24 |
| Finished | Oct 15 12:41:15 AM UTC 24 |
| Peak memory | 259156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656289255 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.3656289255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.423093205 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 732179803 ps |
| CPU time | 15.5 seconds |
| Started | Oct 15 12:39:12 AM UTC 24 |
| Finished | Oct 15 12:39:29 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423093205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.423093205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.2051883149 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 305896261 ps |
| CPU time | 7.58 seconds |
| Started | Oct 15 12:39:03 AM UTC 24 |
| Finished | Oct 15 12:39:12 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051883149 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2051883149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.1276955901 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 163279159 ps |
| CPU time | 11.47 seconds |
| Started | Oct 15 12:39:01 AM UTC 24 |
| Finished | Oct 15 12:39:14 AM UTC 24 |
| Peak memory | 225828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127695590 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.1276955901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.336672761 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 10344697677 ps |
| CPU time | 67.24 seconds |
| Started | Oct 15 12:39:13 AM UTC 24 |
| Finished | Oct 15 12:40:22 AM UTC 24 |
| Peak memory | 241052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=336672761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 21.rom_ctrl_stress_all_with_rand_reset.336672761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.2491491735 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 371034155 ps |
| CPU time | 5.45 seconds |
| Started | Oct 15 12:39:17 AM UTC 24 |
| Finished | Oct 15 12:39:24 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491491735 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2491491735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.480405865 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 2935656666 ps |
| CPU time | 144.51 seconds |
| Started | Oct 15 12:39:13 AM UTC 24 |
| Finished | Oct 15 12:41:40 AM UTC 24 |
| Peak memory | 254536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480405865 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.480405865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.4131035476 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 804409651 ps |
| CPU time | 15.16 seconds |
| Started | Oct 15 12:39:13 AM UTC 24 |
| Finished | Oct 15 12:39:29 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131035476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4131035476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.3427305659 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 341309754 ps |
| CPU time | 7.96 seconds |
| Started | Oct 15 12:39:13 AM UTC 24 |
| Finished | Oct 15 12:39:22 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427305659 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3427305659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.1027189735 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 670668798 ps |
| CPU time | 14.63 seconds |
| Started | Oct 15 12:39:13 AM UTC 24 |
| Finished | Oct 15 12:39:29 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102718973 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.1027189735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3719688182 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 14956185425 ps |
| CPU time | 132.91 seconds |
| Started | Oct 15 12:39:13 AM UTC 24 |
| Finished | Oct 15 12:41:29 AM UTC 24 |
| Peak memory | 235040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3719688182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3719688182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3897266673 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 126031335 ps |
| CPU time | 5.69 seconds |
| Started | Oct 15 12:39:25 AM UTC 24 |
| Finished | Oct 15 12:39:32 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897266673 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3897266673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3539056519 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 17110803566 ps |
| CPU time | 131.31 seconds |
| Started | Oct 15 12:39:17 AM UTC 24 |
| Finished | Oct 15 12:41:31 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539056519 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.3539056519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1979368065 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1282970560 ps |
| CPU time | 16.84 seconds |
| Started | Oct 15 12:39:17 AM UTC 24 |
| Finished | Oct 15 12:39:35 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979368065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1979368065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3268313097 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1256893281 ps |
| CPU time | 9.25 seconds |
| Started | Oct 15 12:39:17 AM UTC 24 |
| Finished | Oct 15 12:39:27 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268313097 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3268313097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.3310186307 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1807012883 ps |
| CPU time | 19.69 seconds |
| Started | Oct 15 12:39:17 AM UTC 24 |
| Finished | Oct 15 12:39:38 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331018630 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.3310186307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3014241104 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1395517458 ps |
| CPU time | 71.55 seconds |
| Started | Oct 15 12:39:22 AM UTC 24 |
| Finished | Oct 15 12:40:36 AM UTC 24 |
| Peak memory | 232992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3014241104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3014241104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.642082254 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 539268174 ps |
| CPU time | 7.66 seconds |
| Started | Oct 15 12:39:28 AM UTC 24 |
| Finished | Oct 15 12:39:37 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642082254 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.642082254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.39078221 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3035782289 ps |
| CPU time | 159.59 seconds |
| Started | Oct 15 12:39:25 AM UTC 24 |
| Finished | Oct 15 12:42:07 AM UTC 24 |
| Peak memory | 243996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39078221 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.39078221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.644883496 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 225462229 ps |
| CPU time | 10.44 seconds |
| Started | Oct 15 12:39:28 AM UTC 24 |
| Finished | Oct 15 12:39:40 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644883496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_c trl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.644883496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.378247734 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1071802336 ps |
| CPU time | 8.21 seconds |
| Started | Oct 15 12:39:25 AM UTC 24 |
| Finished | Oct 15 12:39:34 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378247734 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.378247734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.1691872672 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 723921917 ps |
| CPU time | 14.83 seconds |
| Started | Oct 15 12:39:25 AM UTC 24 |
| Finished | Oct 15 12:39:41 AM UTC 24 |
| Peak memory | 227876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169187267 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.1691872672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1441032170 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4345667872 ps |
| CPU time | 198.22 seconds |
| Started | Oct 15 12:39:28 AM UTC 24 |
| Finished | Oct 15 12:42:50 AM UTC 24 |
| Peak memory | 235104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1441032170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1441032170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3008333062 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 213498305 ps |
| CPU time | 5.88 seconds |
| Started | Oct 15 12:39:32 AM UTC 24 |
| Finished | Oct 15 12:39:40 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008333062 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3008333062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3216797935 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 20088729141 ps |
| CPU time | 259.46 seconds |
| Started | Oct 15 12:39:30 AM UTC 24 |
| Finished | Oct 15 12:43:54 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216797935 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.3216797935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3575808560 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1492054915 ps |
| CPU time | 13.2 seconds |
| Started | Oct 15 12:39:30 AM UTC 24 |
| Finished | Oct 15 12:39:45 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575808560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3575808560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.2550774122 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 201379790 ps |
| CPU time | 7.41 seconds |
| Started | Oct 15 12:39:29 AM UTC 24 |
| Finished | Oct 15 12:39:38 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550774122 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2550774122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.4203293948 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1237156281 ps |
| CPU time | 19.18 seconds |
| Started | Oct 15 12:39:28 AM UTC 24 |
| Finished | Oct 15 12:39:49 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420329394 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.4203293948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1318728169 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 4055542724 ps |
| CPU time | 47.11 seconds |
| Started | Oct 15 12:39:31 AM UTC 24 |
| Finished | Oct 15 12:40:20 AM UTC 24 |
| Peak memory | 233044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1318728169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1318728169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.94351310 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 167196001 ps |
| CPU time | 6.5 seconds |
| Started | Oct 15 12:39:37 AM UTC 24 |
| Finished | Oct 15 12:39:45 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94351310 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.94351310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3297233495 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 7417998710 ps |
| CPU time | 103.01 seconds |
| Started | Oct 15 12:39:36 AM UTC 24 |
| Finished | Oct 15 12:41:21 AM UTC 24 |
| Peak memory | 230828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297233495 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.3297233495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.3826611750 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 299910381 ps |
| CPU time | 15.95 seconds |
| Started | Oct 15 12:39:36 AM UTC 24 |
| Finished | Oct 15 12:39:53 AM UTC 24 |
| Peak memory | 223640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826611750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3826611750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.3971815913 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 134022191 ps |
| CPU time | 9.84 seconds |
| Started | Oct 15 12:39:35 AM UTC 24 |
| Finished | Oct 15 12:39:46 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971815913 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3971815913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2564168181 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 798170341 ps |
| CPU time | 11.63 seconds |
| Started | Oct 15 12:39:33 AM UTC 24 |
| Finished | Oct 15 12:39:46 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256416818 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.2564168181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1852417180 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 25405286856 ps |
| CPU time | 157.34 seconds |
| Started | Oct 15 12:39:36 AM UTC 24 |
| Finished | Oct 15 12:42:16 AM UTC 24 |
| Peak memory | 245152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1852417180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1852417180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.2466447060 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 372559558 ps |
| CPU time | 6.16 seconds |
| Started | Oct 15 12:39:40 AM UTC 24 |
| Finished | Oct 15 12:39:48 AM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466447060 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2466447060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2912398239 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 2042763275 ps |
| CPU time | 166.11 seconds |
| Started | Oct 15 12:39:38 AM UTC 24 |
| Finished | Oct 15 12:42:27 AM UTC 24 |
| Peak memory | 246072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912398239 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.2912398239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.3844169480 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 304322736 ps |
| CPU time | 14.21 seconds |
| Started | Oct 15 12:39:39 AM UTC 24 |
| Finished | Oct 15 12:39:55 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844169480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3844169480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.2928921659 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 607033181 ps |
| CPU time | 9.07 seconds |
| Started | Oct 15 12:39:38 AM UTC 24 |
| Finished | Oct 15 12:39:48 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928921659 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2928921659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.93724599 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 340995035 ps |
| CPU time | 17.95 seconds |
| Started | Oct 15 12:39:38 AM UTC 24 |
| Finished | Oct 15 12:39:57 AM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93724599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.93724599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.440038090 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3696400657 ps |
| CPU time | 53.55 seconds |
| Started | Oct 15 12:39:40 AM UTC 24 |
| Finished | Oct 15 12:40:36 AM UTC 24 |
| Peak memory | 233052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=440038090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 27.rom_ctrl_stress_all_with_rand_reset.440038090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3758841557 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 171201732 ps |
| CPU time | 6.76 seconds |
| Started | Oct 15 12:39:47 AM UTC 24 |
| Finished | Oct 15 12:39:55 AM UTC 24 |
| Peak memory | 222752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758841557 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3758841557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2907329051 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 5013456101 ps |
| CPU time | 77.32 seconds |
| Started | Oct 15 12:39:45 AM UTC 24 |
| Finished | Oct 15 12:41:04 AM UTC 24 |
| Peak memory | 258468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907329051 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.2907329051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.1069409404 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 296661773 ps |
| CPU time | 12.02 seconds |
| Started | Oct 15 12:39:46 AM UTC 24 |
| Finished | Oct 15 12:39:59 AM UTC 24 |
| Peak memory | 223576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069409404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1069409404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2513163334 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 506880875 ps |
| CPU time | 9.31 seconds |
| Started | Oct 15 12:39:44 AM UTC 24 |
| Finished | Oct 15 12:39:54 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513163334 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2513163334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.342996622 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 790757007 ps |
| CPU time | 14.76 seconds |
| Started | Oct 15 12:39:41 AM UTC 24 |
| Finished | Oct 15 12:39:58 AM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342996622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.342996622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.2931948159 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 315801201 ps |
| CPU time | 5.36 seconds |
| Started | Oct 15 12:39:50 AM UTC 24 |
| Finished | Oct 15 12:39:57 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931948159 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2931948159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2638426411 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1784448444 ps |
| CPU time | 103.04 seconds |
| Started | Oct 15 12:39:49 AM UTC 24 |
| Finished | Oct 15 12:41:34 AM UTC 24 |
| Peak memory | 243656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638426411 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.2638426411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.1441562698 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 291654667 ps |
| CPU time | 12.59 seconds |
| Started | Oct 15 12:39:50 AM UTC 24 |
| Finished | Oct 15 12:40:04 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441562698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1441562698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.1009492741 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 592208568 ps |
| CPU time | 8.51 seconds |
| Started | Oct 15 12:39:49 AM UTC 24 |
| Finished | Oct 15 12:39:59 AM UTC 24 |
| Peak memory | 223156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009492741 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1009492741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.844301638 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 336559535 ps |
| CPU time | 19.05 seconds |
| Started | Oct 15 12:39:47 AM UTC 24 |
| Finished | Oct 15 12:40:07 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844301638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.844301638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2369257619 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1008001226 ps |
| CPU time | 36.06 seconds |
| Started | Oct 15 12:39:50 AM UTC 24 |
| Finished | Oct 15 12:40:28 AM UTC 24 |
| Peak memory | 230748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2369257619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2369257619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.289122298 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 127075862 ps |
| CPU time | 5.87 seconds |
| Started | Oct 15 12:37:16 AM UTC 24 |
| Finished | Oct 15 12:37:22 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289122298 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.289122298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.150852074 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 7795948743 ps |
| CPU time | 133.28 seconds |
| Started | Oct 15 12:37:14 AM UTC 24 |
| Finished | Oct 15 12:39:30 AM UTC 24 |
| Peak memory | 258832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150852074 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.150852074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.1087461956 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 359706392 ps |
| CPU time | 10.61 seconds |
| Started | Oct 15 12:37:15 AM UTC 24 |
| Finished | Oct 15 12:37:27 AM UTC 24 |
| Peak memory | 223640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087461956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1087461956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.497045305 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 592741526 ps |
| CPU time | 6.6 seconds |
| Started | Oct 15 12:37:14 AM UTC 24 |
| Finished | Oct 15 12:37:22 AM UTC 24 |
| Peak memory | 223260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497045305 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.497045305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.426784604 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 308011578 ps |
| CPU time | 111.15 seconds |
| Started | Oct 15 12:37:16 AM UTC 24 |
| Finished | Oct 15 12:39:09 AM UTC 24 |
| Peak memory | 258780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426784604 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.426784604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.2407556108 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 657749236 ps |
| CPU time | 9.85 seconds |
| Started | Oct 15 12:37:14 AM UTC 24 |
| Finished | Oct 15 12:37:25 AM UTC 24 |
| Peak memory | 223520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240755610 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.2407556108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2692657557 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 13136712655 ps |
| CPU time | 136.78 seconds |
| Started | Oct 15 12:37:15 AM UTC 24 |
| Finished | Oct 15 12:39:35 AM UTC 24 |
| Peak memory | 232840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2692657557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.rom_ctrl_stress_all_with_rand_reset.2692657557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.649021182 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2090630929 ps |
| CPU time | 7.07 seconds |
| Started | Oct 15 12:39:58 AM UTC 24 |
| Finished | Oct 15 12:40:06 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649021182 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.649021182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2069755804 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 9832520932 ps |
| CPU time | 136.24 seconds |
| Started | Oct 15 12:39:56 AM UTC 24 |
| Finished | Oct 15 12:42:14 AM UTC 24 |
| Peak memory | 258332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069755804 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.2069755804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.3989579954 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 288110762 ps |
| CPU time | 11.43 seconds |
| Started | Oct 15 12:39:56 AM UTC 24 |
| Finished | Oct 15 12:40:08 AM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989579954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3989579954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.1307929926 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 783987859 ps |
| CPU time | 9.62 seconds |
| Started | Oct 15 12:39:53 AM UTC 24 |
| Finished | Oct 15 12:40:04 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307929926 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1307929926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.1510715069 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 723379780 ps |
| CPU time | 31.39 seconds |
| Started | Oct 15 12:39:52 AM UTC 24 |
| Finished | Oct 15 12:40:25 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151071506 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.1510715069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.658818012 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 3374312008 ps |
| CPU time | 109.79 seconds |
| Started | Oct 15 12:39:56 AM UTC 24 |
| Finished | Oct 15 12:41:48 AM UTC 24 |
| Peak memory | 232860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=658818012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 30.rom_ctrl_stress_all_with_rand_reset.658818012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3310471677 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 164341063 ps |
| CPU time | 6.94 seconds |
| Started | Oct 15 12:40:01 AM UTC 24 |
| Finished | Oct 15 12:40:09 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310471677 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3310471677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1321944786 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 8163201024 ps |
| CPU time | 125.47 seconds |
| Started | Oct 15 12:39:59 AM UTC 24 |
| Finished | Oct 15 12:42:07 AM UTC 24 |
| Peak memory | 259208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321944786 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.1321944786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2067061281 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 136969824 ps |
| CPU time | 8.4 seconds |
| Started | Oct 15 12:39:59 AM UTC 24 |
| Finished | Oct 15 12:40:08 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067061281 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2067061281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2131568221 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 888276533 ps |
| CPU time | 18.99 seconds |
| Started | Oct 15 12:39:58 AM UTC 24 |
| Finished | Oct 15 12:40:18 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213156822 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.2131568221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1936384002 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 4770152094 ps |
| CPU time | 48.53 seconds |
| Started | Oct 15 12:40:00 AM UTC 24 |
| Finished | Oct 15 12:40:50 AM UTC 24 |
| Peak memory | 232964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1936384002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 31.rom_ctrl_stress_all_with_rand_reset.1936384002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.2656625539 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 528532527 ps |
| CPU time | 5.29 seconds |
| Started | Oct 15 12:40:07 AM UTC 24 |
| Finished | Oct 15 12:40:13 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656625539 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2656625539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2623856012 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1465020083 ps |
| CPU time | 63.9 seconds |
| Started | Oct 15 12:40:05 AM UTC 24 |
| Finished | Oct 15 12:41:10 AM UTC 24 |
| Peak memory | 223808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623856012 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.2623856012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.1758869279 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 294131511 ps |
| CPU time | 12.85 seconds |
| Started | Oct 15 12:40:05 AM UTC 24 |
| Finished | Oct 15 12:40:19 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758869279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1758869279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.123908335 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 174537768 ps |
| CPU time | 9.79 seconds |
| Started | Oct 15 12:40:03 AM UTC 24 |
| Finished | Oct 15 12:40:14 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123908335 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.123908335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.630989159 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 347392670 ps |
| CPU time | 17.62 seconds |
| Started | Oct 15 12:40:02 AM UTC 24 |
| Finished | Oct 15 12:40:21 AM UTC 24 |
| Peak memory | 225744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630989159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.630989159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2810731557 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1516732980 ps |
| CPU time | 37.88 seconds |
| Started | Oct 15 12:40:05 AM UTC 24 |
| Finished | Oct 15 12:40:44 AM UTC 24 |
| Peak memory | 230804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2810731557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2810731557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2519557579 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 216840836 ps |
| CPU time | 6.27 seconds |
| Started | Oct 15 12:40:12 AM UTC 24 |
| Finished | Oct 15 12:40:19 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519557579 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2519557579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2228232719 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2392114547 ps |
| CPU time | 76.73 seconds |
| Started | Oct 15 12:40:09 AM UTC 24 |
| Finished | Oct 15 12:41:28 AM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228232719 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.2228232719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.3277246483 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1410297886 ps |
| CPU time | 12.56 seconds |
| Started | Oct 15 12:40:09 AM UTC 24 |
| Finished | Oct 15 12:40:23 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277246483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3277246483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.2489741849 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 181105582 ps |
| CPU time | 9.13 seconds |
| Started | Oct 15 12:40:08 AM UTC 24 |
| Finished | Oct 15 12:40:18 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489741849 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2489741849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.2682749719 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1141963623 ps |
| CPU time | 22.41 seconds |
| Started | Oct 15 12:40:08 AM UTC 24 |
| Finished | Oct 15 12:40:32 AM UTC 24 |
| Peak memory | 225748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268274971 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.2682749719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2103290800 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3856507711 ps |
| CPU time | 149.65 seconds |
| Started | Oct 15 12:40:11 AM UTC 24 |
| Finished | Oct 15 12:42:43 AM UTC 24 |
| Peak memory | 234912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2103290800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2103290800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.586811723 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 168428405 ps |
| CPU time | 7.48 seconds |
| Started | Oct 15 12:40:19 AM UTC 24 |
| Finished | Oct 15 12:40:28 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586811723 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.586811723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2813002347 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 29857303569 ps |
| CPU time | 104.34 seconds |
| Started | Oct 15 12:40:14 AM UTC 24 |
| Finished | Oct 15 12:42:00 AM UTC 24 |
| Peak memory | 259308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813002347 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.2813002347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2226934484 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 294082488 ps |
| CPU time | 12.77 seconds |
| Started | Oct 15 12:40:15 AM UTC 24 |
| Finished | Oct 15 12:40:29 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226934484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2226934484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.3256091254 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 176717675 ps |
| CPU time | 9.04 seconds |
| Started | Oct 15 12:40:14 AM UTC 24 |
| Finished | Oct 15 12:40:24 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256091254 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3256091254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1841660319 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 852646672 ps |
| CPU time | 18.25 seconds |
| Started | Oct 15 12:40:13 AM UTC 24 |
| Finished | Oct 15 12:40:32 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184166031 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.1841660319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.6052643 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4624291889 ps |
| CPU time | 219.03 seconds |
| Started | Oct 15 12:40:16 AM UTC 24 |
| Finished | Oct 15 12:43:58 AM UTC 24 |
| Peak memory | 232860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=6052643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.6052643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.2476414464 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 553198751 ps |
| CPU time | 7.49 seconds |
| Started | Oct 15 12:40:23 AM UTC 24 |
| Finished | Oct 15 12:40:32 AM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476414464 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2476414464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2694860189 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 4299533654 ps |
| CPU time | 151.52 seconds |
| Started | Oct 15 12:40:20 AM UTC 24 |
| Finished | Oct 15 12:42:54 AM UTC 24 |
| Peak memory | 254520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694860189 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.2694860189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.1725666725 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 215613727 ps |
| CPU time | 13.4 seconds |
| Started | Oct 15 12:40:22 AM UTC 24 |
| Finished | Oct 15 12:40:36 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725666725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1725666725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.1566020087 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 177653901 ps |
| CPU time | 8.04 seconds |
| Started | Oct 15 12:40:20 AM UTC 24 |
| Finished | Oct 15 12:40:29 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566020087 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1566020087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1343963606 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 452976374 ps |
| CPU time | 9.51 seconds |
| Started | Oct 15 12:40:19 AM UTC 24 |
| Finished | Oct 15 12:40:30 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134396360 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.1343963606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3166997072 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 3406112927 ps |
| CPU time | 72.36 seconds |
| Started | Oct 15 12:40:22 AM UTC 24 |
| Finished | Oct 15 12:41:36 AM UTC 24 |
| Peak memory | 232860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3166997072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3166997072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1638613667 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 293042875 ps |
| CPU time | 6.91 seconds |
| Started | Oct 15 12:40:29 AM UTC 24 |
| Finished | Oct 15 12:40:37 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638613667 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1638613667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1398555202 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 5992027046 ps |
| CPU time | 113.91 seconds |
| Started | Oct 15 12:40:26 AM UTC 24 |
| Finished | Oct 15 12:42:23 AM UTC 24 |
| Peak memory | 246928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398555202 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.1398555202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1933206837 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 209132950 ps |
| CPU time | 14.54 seconds |
| Started | Oct 15 12:40:27 AM UTC 24 |
| Finished | Oct 15 12:40:43 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933206837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1933206837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.3640787677 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 174747891 ps |
| CPU time | 9.31 seconds |
| Started | Oct 15 12:40:25 AM UTC 24 |
| Finished | Oct 15 12:40:36 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640787677 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3640787677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.3136460936 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 168965965 ps |
| CPU time | 10.68 seconds |
| Started | Oct 15 12:40:24 AM UTC 24 |
| Finished | Oct 15 12:40:36 AM UTC 24 |
| Peak memory | 225828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313646093 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.3136460936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.4131710215 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 19842274560 ps |
| CPU time | 221.54 seconds |
| Started | Oct 15 12:40:29 AM UTC 24 |
| Finished | Oct 15 12:44:14 AM UTC 24 |
| Peak memory | 236960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4131710215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 36.rom_ctrl_stress_all_with_rand_reset.4131710215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3108548760 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 307290304 ps |
| CPU time | 5.76 seconds |
| Started | Oct 15 12:40:33 AM UTC 24 |
| Finished | Oct 15 12:40:40 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108548760 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3108548760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1636385964 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 3312651221 ps |
| CPU time | 124.91 seconds |
| Started | Oct 15 12:40:31 AM UTC 24 |
| Finished | Oct 15 12:42:39 AM UTC 24 |
| Peak memory | 260388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636385964 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.1636385964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2760550450 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 760683534 ps |
| CPU time | 15.46 seconds |
| Started | Oct 15 12:40:32 AM UTC 24 |
| Finished | Oct 15 12:40:49 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760550450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2760550450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.4293548611 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1059775464 ps |
| CPU time | 9.66 seconds |
| Started | Oct 15 12:40:30 AM UTC 24 |
| Finished | Oct 15 12:40:41 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293548611 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4293548611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.1963339783 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1160466979 ps |
| CPU time | 16.24 seconds |
| Started | Oct 15 12:40:30 AM UTC 24 |
| Finished | Oct 15 12:40:47 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196333978 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.1963339783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1513250280 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 15278725910 ps |
| CPU time | 104.46 seconds |
| Started | Oct 15 12:40:33 AM UTC 24 |
| Finished | Oct 15 12:42:20 AM UTC 24 |
| Peak memory | 234912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1513250280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1513250280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.970125737 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 958593570 ps |
| CPU time | 6.11 seconds |
| Started | Oct 15 12:40:38 AM UTC 24 |
| Finished | Oct 15 12:40:45 AM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970125737 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.970125737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3520272828 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 8502488514 ps |
| CPU time | 156.93 seconds |
| Started | Oct 15 12:40:37 AM UTC 24 |
| Finished | Oct 15 12:43:16 AM UTC 24 |
| Peak memory | 247028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520272828 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.3520272828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.3117812709 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1075112044 ps |
| CPU time | 15.02 seconds |
| Started | Oct 15 12:40:38 AM UTC 24 |
| Finished | Oct 15 12:40:54 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117812709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3117812709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2618833602 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 140089127 ps |
| CPU time | 7.06 seconds |
| Started | Oct 15 12:40:36 AM UTC 24 |
| Finished | Oct 15 12:40:45 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618833602 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2618833602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.3482400092 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 443417437 ps |
| CPU time | 27.67 seconds |
| Started | Oct 15 12:40:36 AM UTC 24 |
| Finished | Oct 15 12:41:05 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348240009 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.3482400092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.351678678 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 537947260 ps |
| CPU time | 5.15 seconds |
| Started | Oct 15 12:40:46 AM UTC 24 |
| Finished | Oct 15 12:40:52 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351678678 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.351678678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3743665737 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 13574657702 ps |
| CPU time | 154.9 seconds |
| Started | Oct 15 12:40:44 AM UTC 24 |
| Finished | Oct 15 12:43:22 AM UTC 24 |
| Peak memory | 246048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743665737 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.3743665737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2840351468 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 207194369 ps |
| CPU time | 10.49 seconds |
| Started | Oct 15 12:40:46 AM UTC 24 |
| Finished | Oct 15 12:40:57 AM UTC 24 |
| Peak memory | 223576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840351468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2840351468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.361506626 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 701457539 ps |
| CPU time | 8.83 seconds |
| Started | Oct 15 12:40:42 AM UTC 24 |
| Finished | Oct 15 12:40:52 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361506626 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.361506626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3144530565 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3951695858 ps |
| CPU time | 13.03 seconds |
| Started | Oct 15 12:40:41 AM UTC 24 |
| Finished | Oct 15 12:40:55 AM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314453056 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.3144530565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1991632005 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 4408002762 ps |
| CPU time | 161.42 seconds |
| Started | Oct 15 12:40:46 AM UTC 24 |
| Finished | Oct 15 12:43:30 AM UTC 24 |
| Peak memory | 235168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1991632005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1991632005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.789120063 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 163578198 ps |
| CPU time | 8.73 seconds |
| Started | Oct 15 12:37:22 AM UTC 24 |
| Finished | Oct 15 12:37:32 AM UTC 24 |
| Peak memory | 222536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789120063 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.789120063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2311425679 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5804001691 ps |
| CPU time | 80.68 seconds |
| Started | Oct 15 12:37:18 AM UTC 24 |
| Finished | Oct 15 12:38:41 AM UTC 24 |
| Peak memory | 255136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311425679 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.2311425679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.1272772568 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2423163649 ps |
| CPU time | 10.41 seconds |
| Started | Oct 15 12:37:18 AM UTC 24 |
| Finished | Oct 15 12:37:29 AM UTC 24 |
| Peak memory | 223508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272772568 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1272772568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3039693077 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 182033752 ps |
| CPU time | 8.84 seconds |
| Started | Oct 15 12:37:17 AM UTC 24 |
| Finished | Oct 15 12:37:27 AM UTC 24 |
| Peak memory | 223520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039693077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3039693077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3872601372 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1668168690 ps |
| CPU time | 18.82 seconds |
| Started | Oct 15 12:37:17 AM UTC 24 |
| Finished | Oct 15 12:37:37 AM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387260137 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.3872601372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.531723658 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 3100897055 ps |
| CPU time | 239.56 seconds |
| Started | Oct 15 12:37:20 AM UTC 24 |
| Finished | Oct 15 12:41:24 AM UTC 24 |
| Peak memory | 243100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=531723658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 4.rom_ctrl_stress_all_with_rand_reset.531723658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.382850385 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 123756303 ps |
| CPU time | 6.75 seconds |
| Started | Oct 15 12:40:53 AM UTC 24 |
| Finished | Oct 15 12:41:01 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382850385 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.382850385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2576473634 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2587457326 ps |
| CPU time | 133.84 seconds |
| Started | Oct 15 12:40:51 AM UTC 24 |
| Finished | Oct 15 12:43:07 AM UTC 24 |
| Peak memory | 259276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576473634 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.2576473634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2177350915 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1692785163 ps |
| CPU time | 11.46 seconds |
| Started | Oct 15 12:40:51 AM UTC 24 |
| Finished | Oct 15 12:41:04 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177350915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2177350915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3751695260 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 137461984 ps |
| CPU time | 7.07 seconds |
| Started | Oct 15 12:40:50 AM UTC 24 |
| Finished | Oct 15 12:40:58 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751695260 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3751695260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.887722369 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 329428730 ps |
| CPU time | 25.29 seconds |
| Started | Oct 15 12:40:48 AM UTC 24 |
| Finished | Oct 15 12:41:14 AM UTC 24 |
| Peak memory | 227808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887722369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.887722369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3776053489 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 6147989507 ps |
| CPU time | 111.71 seconds |
| Started | Oct 15 12:40:53 AM UTC 24 |
| Finished | Oct 15 12:42:47 AM UTC 24 |
| Peak memory | 241056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3776053489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3776053489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.950144078 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 170272883 ps |
| CPU time | 7.75 seconds |
| Started | Oct 15 12:41:09 AM UTC 24 |
| Finished | Oct 15 12:41:18 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950144078 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.950144078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1166323097 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 10465986634 ps |
| CPU time | 107.53 seconds |
| Started | Oct 15 12:41:08 AM UTC 24 |
| Finished | Oct 15 12:42:57 AM UTC 24 |
| Peak memory | 246876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166323097 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.1166323097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.1652984032 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 542578764 ps |
| CPU time | 13.31 seconds |
| Started | Oct 15 12:41:09 AM UTC 24 |
| Finished | Oct 15 12:41:23 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652984032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1652984032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.3137779492 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 140033970 ps |
| CPU time | 10.02 seconds |
| Started | Oct 15 12:41:07 AM UTC 24 |
| Finished | Oct 15 12:41:19 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137779492 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3137779492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3816197145 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1136279070 ps |
| CPU time | 12.1 seconds |
| Started | Oct 15 12:40:54 AM UTC 24 |
| Finished | Oct 15 12:41:08 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381619714 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.3816197145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1532628044 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4450048910 ps |
| CPU time | 166.55 seconds |
| Started | Oct 15 12:41:09 AM UTC 24 |
| Finished | Oct 15 12:43:58 AM UTC 24 |
| Peak memory | 235168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1532628044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1532628044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.2442479877 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 300148163 ps |
| CPU time | 7.88 seconds |
| Started | Oct 15 12:41:12 AM UTC 24 |
| Finished | Oct 15 12:41:21 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442479877 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2442479877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.928529991 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 6381682750 ps |
| CPU time | 98.98 seconds |
| Started | Oct 15 12:41:09 AM UTC 24 |
| Finished | Oct 15 12:42:50 AM UTC 24 |
| Peak memory | 223844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928529991 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.928529991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1517511056 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 208298255 ps |
| CPU time | 15.63 seconds |
| Started | Oct 15 12:41:09 AM UTC 24 |
| Finished | Oct 15 12:41:26 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517511056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1517511056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.3760656434 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 310205679 ps |
| CPU time | 9.62 seconds |
| Started | Oct 15 12:41:09 AM UTC 24 |
| Finished | Oct 15 12:41:20 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760656434 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3760656434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1981018498 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1221450250 ps |
| CPU time | 21.81 seconds |
| Started | Oct 15 12:41:09 AM UTC 24 |
| Finished | Oct 15 12:41:32 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198101849 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.1981018498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3935704358 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 3010660947 ps |
| CPU time | 197.3 seconds |
| Started | Oct 15 12:41:11 AM UTC 24 |
| Finished | Oct 15 12:44:32 AM UTC 24 |
| Peak memory | 241056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3935704358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3935704358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2568005715 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 6123399315 ps |
| CPU time | 12.03 seconds |
| Started | Oct 15 12:41:21 AM UTC 24 |
| Finished | Oct 15 12:41:35 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568005715 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2568005715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2008037338 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 5555498904 ps |
| CPU time | 142.86 seconds |
| Started | Oct 15 12:41:16 AM UTC 24 |
| Finished | Oct 15 12:43:41 AM UTC 24 |
| Peak memory | 252124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008037338 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.2008037338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.51194888 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1033838874 ps |
| CPU time | 11.72 seconds |
| Started | Oct 15 12:41:19 AM UTC 24 |
| Finished | Oct 15 12:41:32 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51194888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_ TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.51194888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1488257788 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 135904785 ps |
| CPU time | 6.12 seconds |
| Started | Oct 15 12:41:16 AM UTC 24 |
| Finished | Oct 15 12:41:23 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488257788 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1488257788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.1723310460 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 311232552 ps |
| CPU time | 14.27 seconds |
| Started | Oct 15 12:41:15 AM UTC 24 |
| Finished | Oct 15 12:41:30 AM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172331046 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.1723310460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2084476312 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 17238280002 ps |
| CPU time | 93.71 seconds |
| Started | Oct 15 12:41:20 AM UTC 24 |
| Finished | Oct 15 12:42:56 AM UTC 24 |
| Peak memory | 236960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2084476312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2084476312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.2896049972 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 556996377 ps |
| CPU time | 7.53 seconds |
| Started | Oct 15 12:41:27 AM UTC 24 |
| Finished | Oct 15 12:41:36 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896049972 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2896049972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1752679133 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1430925023 ps |
| CPU time | 82.87 seconds |
| Started | Oct 15 12:41:23 AM UTC 24 |
| Finished | Oct 15 12:42:48 AM UTC 24 |
| Peak memory | 246112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752679133 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.1752679133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.1483232020 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 548402621 ps |
| CPU time | 16.89 seconds |
| Started | Oct 15 12:41:25 AM UTC 24 |
| Finished | Oct 15 12:41:43 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483232020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1483232020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.41138649 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 757237124 ps |
| CPU time | 8.57 seconds |
| Started | Oct 15 12:41:22 AM UTC 24 |
| Finished | Oct 15 12:41:32 AM UTC 24 |
| Peak memory | 223712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41138649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.41138649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.2014623511 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 659368695 ps |
| CPU time | 9.38 seconds |
| Started | Oct 15 12:41:22 AM UTC 24 |
| Finished | Oct 15 12:41:33 AM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201462351 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.2014623511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.502727669 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1793969847 ps |
| CPU time | 69.85 seconds |
| Started | Oct 15 12:41:25 AM UTC 24 |
| Finished | Oct 15 12:42:36 AM UTC 24 |
| Peak memory | 230748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=502727669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 44.rom_ctrl_stress_all_with_rand_reset.502727669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.839574561 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 485647143 ps |
| CPU time | 7.71 seconds |
| Started | Oct 15 12:41:32 AM UTC 24 |
| Finished | Oct 15 12:41:40 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839574561 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.839574561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.304484947 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 20798119615 ps |
| CPU time | 165.25 seconds |
| Started | Oct 15 12:41:29 AM UTC 24 |
| Finished | Oct 15 12:44:17 AM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304484947 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.304484947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.4196902961 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 300753004 ps |
| CPU time | 15.98 seconds |
| Started | Oct 15 12:41:30 AM UTC 24 |
| Finished | Oct 15 12:41:48 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196902961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.4196902961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.920549577 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 618326379 ps |
| CPU time | 9.58 seconds |
| Started | Oct 15 12:41:29 AM UTC 24 |
| Finished | Oct 15 12:41:40 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920549577 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.920549577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2696488742 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 445727503 ps |
| CPU time | 6.86 seconds |
| Started | Oct 15 12:41:29 AM UTC 24 |
| Finished | Oct 15 12:41:37 AM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269648874 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.2696488742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.17250984 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 14250298112 ps |
| CPU time | 267.08 seconds |
| Started | Oct 15 12:41:32 AM UTC 24 |
| Finished | Oct 15 12:46:03 AM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=17250984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.17250984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.2148522913 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 123490109 ps |
| CPU time | 6.42 seconds |
| Started | Oct 15 12:41:36 AM UTC 24 |
| Finished | Oct 15 12:41:43 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148522913 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2148522913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3498566085 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1990177757 ps |
| CPU time | 130.89 seconds |
| Started | Oct 15 12:41:33 AM UTC 24 |
| Finished | Oct 15 12:43:46 AM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498566085 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.3498566085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.4263947355 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 372268137 ps |
| CPU time | 12.26 seconds |
| Started | Oct 15 12:41:34 AM UTC 24 |
| Finished | Oct 15 12:41:48 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263947355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4263947355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2752616584 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 411261435 ps |
| CPU time | 8.69 seconds |
| Started | Oct 15 12:41:33 AM UTC 24 |
| Finished | Oct 15 12:41:43 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752616584 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2752616584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.1634963681 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 416473396 ps |
| CPU time | 17.43 seconds |
| Started | Oct 15 12:41:33 AM UTC 24 |
| Finished | Oct 15 12:41:52 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163496368 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.1634963681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2615966575 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 5141822350 ps |
| CPU time | 188.52 seconds |
| Started | Oct 15 12:41:35 AM UTC 24 |
| Finished | Oct 15 12:44:47 AM UTC 24 |
| Peak memory | 243232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2615966575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2615966575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1661886276 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 128038340 ps |
| CPU time | 6.6 seconds |
| Started | Oct 15 12:41:41 AM UTC 24 |
| Finished | Oct 15 12:41:49 AM UTC 24 |
| Peak memory | 223304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661886276 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1661886276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1178811686 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 7958243383 ps |
| CPU time | 142.77 seconds |
| Started | Oct 15 12:41:38 AM UTC 24 |
| Finished | Oct 15 12:44:04 AM UTC 24 |
| Peak memory | 259328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178811686 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.1178811686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.1584394806 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1033175730 ps |
| CPU time | 12.14 seconds |
| Started | Oct 15 12:41:41 AM UTC 24 |
| Finished | Oct 15 12:41:55 AM UTC 24 |
| Peak memory | 223364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584394806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1584394806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.3304356417 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 577392769 ps |
| CPU time | 9.33 seconds |
| Started | Oct 15 12:41:37 AM UTC 24 |
| Finished | Oct 15 12:41:47 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304356417 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3304356417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.3407551691 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 207678099 ps |
| CPU time | 13.88 seconds |
| Started | Oct 15 12:41:37 AM UTC 24 |
| Finished | Oct 15 12:41:52 AM UTC 24 |
| Peak memory | 223764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340755169 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.3407551691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1774985802 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1948375288 ps |
| CPU time | 72.51 seconds |
| Started | Oct 15 12:41:41 AM UTC 24 |
| Finished | Oct 15 12:42:56 AM UTC 24 |
| Peak memory | 230728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1774985802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1774985802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.2737483467 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 2090785583 ps |
| CPU time | 8.53 seconds |
| Started | Oct 15 12:41:49 AM UTC 24 |
| Finished | Oct 15 12:41:59 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737483467 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2737483467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3119141866 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2358064076 ps |
| CPU time | 145.43 seconds |
| Started | Oct 15 12:41:44 AM UTC 24 |
| Finished | Oct 15 12:44:12 AM UTC 24 |
| Peak memory | 258892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119141866 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.3119141866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.2944703818 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 206504995 ps |
| CPU time | 15.52 seconds |
| Started | Oct 15 12:41:48 AM UTC 24 |
| Finished | Oct 15 12:42:05 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944703818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2944703818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.2684862688 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 181043060 ps |
| CPU time | 10.14 seconds |
| Started | Oct 15 12:41:44 AM UTC 24 |
| Finished | Oct 15 12:41:55 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684862688 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2684862688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1917271387 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 342534248 ps |
| CPU time | 26.04 seconds |
| Started | Oct 15 12:41:44 AM UTC 24 |
| Finished | Oct 15 12:42:11 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191727138 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.1917271387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.1412023872 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 357925459 ps |
| CPU time | 6.35 seconds |
| Started | Oct 15 12:41:56 AM UTC 24 |
| Finished | Oct 15 12:42:04 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412023872 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1412023872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.511639436 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3213688792 ps |
| CPU time | 111.19 seconds |
| Started | Oct 15 12:41:51 AM UTC 24 |
| Finished | Oct 15 12:43:44 AM UTC 24 |
| Peak memory | 244016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511639436 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.511639436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.2442662675 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 213734129 ps |
| CPU time | 12.94 seconds |
| Started | Oct 15 12:41:53 AM UTC 24 |
| Finished | Oct 15 12:42:07 AM UTC 24 |
| Peak memory | 223448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442662675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2442662675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2323258500 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 513796680 ps |
| CPU time | 7.38 seconds |
| Started | Oct 15 12:41:50 AM UTC 24 |
| Finished | Oct 15 12:41:58 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323258500 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2323258500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.1820227408 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1305292903 ps |
| CPU time | 27.57 seconds |
| Started | Oct 15 12:41:49 AM UTC 24 |
| Finished | Oct 15 12:42:18 AM UTC 24 |
| Peak memory | 227876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182022740 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.1820227408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3712108837 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3952229849 ps |
| CPU time | 138.84 seconds |
| Started | Oct 15 12:41:53 AM UTC 24 |
| Finished | Oct 15 12:44:14 AM UTC 24 |
| Peak memory | 243104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3712108837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3712108837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.1858969327 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1414709235 ps |
| CPU time | 4.91 seconds |
| Started | Oct 15 12:37:25 AM UTC 24 |
| Finished | Oct 15 12:37:31 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858969327 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1858969327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1360228274 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1314530681 ps |
| CPU time | 9.29 seconds |
| Started | Oct 15 12:37:23 AM UTC 24 |
| Finished | Oct 15 12:37:34 AM UTC 24 |
| Peak memory | 223452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360228274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1360228274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1146174700 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 177575229 ps |
| CPU time | 7.08 seconds |
| Started | Oct 15 12:37:23 AM UTC 24 |
| Finished | Oct 15 12:37:32 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146174700 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1146174700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3219068754 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 691536873 ps |
| CPU time | 9.18 seconds |
| Started | Oct 15 12:37:22 AM UTC 24 |
| Finished | Oct 15 12:37:33 AM UTC 24 |
| Peak memory | 223496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219068754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3219068754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.220121726 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 556412877 ps |
| CPU time | 6.37 seconds |
| Started | Oct 15 12:37:28 AM UTC 24 |
| Finished | Oct 15 12:37:36 AM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220121726 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.220121726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1504447758 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 378051443 ps |
| CPU time | 10.39 seconds |
| Started | Oct 15 12:37:27 AM UTC 24 |
| Finished | Oct 15 12:37:39 AM UTC 24 |
| Peak memory | 223452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504447758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1504447758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2946244858 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 221614946 ps |
| CPU time | 9.36 seconds |
| Started | Oct 15 12:37:26 AM UTC 24 |
| Finished | Oct 15 12:37:36 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946244858 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2946244858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.3949427242 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1145317951 ps |
| CPU time | 9.04 seconds |
| Started | Oct 15 12:37:25 AM UTC 24 |
| Finished | Oct 15 12:37:35 AM UTC 24 |
| Peak memory | 223520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949427242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3949427242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3669159745 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3072428660 ps |
| CPU time | 138.28 seconds |
| Started | Oct 15 12:37:28 AM UTC 24 |
| Finished | Oct 15 12:39:49 AM UTC 24 |
| Peak memory | 232920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3669159745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3669159745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.3683617230 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 372847485 ps |
| CPU time | 4.76 seconds |
| Started | Oct 15 12:37:34 AM UTC 24 |
| Finished | Oct 15 12:37:39 AM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683617230 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3683617230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.91652763 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5305800063 ps |
| CPU time | 80.05 seconds |
| Started | Oct 15 12:37:31 AM UTC 24 |
| Finished | Oct 15 12:38:53 AM UTC 24 |
| Peak memory | 259300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91652763 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.91652763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3247010323 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 293888237 ps |
| CPU time | 11.84 seconds |
| Started | Oct 15 12:37:33 AM UTC 24 |
| Finished | Oct 15 12:37:45 AM UTC 24 |
| Peak memory | 223452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247010323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3247010323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1639194839 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 871400496 ps |
| CPU time | 5.94 seconds |
| Started | Oct 15 12:37:30 AM UTC 24 |
| Finished | Oct 15 12:37:37 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639194839 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1639194839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.1725255265 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 264128385 ps |
| CPU time | 6.71 seconds |
| Started | Oct 15 12:37:29 AM UTC 24 |
| Finished | Oct 15 12:37:37 AM UTC 24 |
| Peak memory | 223520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725255265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1725255265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1710709292 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2003858814 ps |
| CPU time | 20.25 seconds |
| Started | Oct 15 12:37:29 AM UTC 24 |
| Finished | Oct 15 12:37:51 AM UTC 24 |
| Peak memory | 225616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171070929 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.1710709292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.1495626861 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 690340081 ps |
| CPU time | 6.14 seconds |
| Started | Oct 15 12:37:37 AM UTC 24 |
| Finished | Oct 15 12:37:44 AM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495626861 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1495626861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2183942040 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 13226601389 ps |
| CPU time | 213.06 seconds |
| Started | Oct 15 12:37:35 AM UTC 24 |
| Finished | Oct 15 12:41:11 AM UTC 24 |
| Peak memory | 259296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183942040 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.2183942040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2543830184 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 830443573 ps |
| CPU time | 9.95 seconds |
| Started | Oct 15 12:37:36 AM UTC 24 |
| Finished | Oct 15 12:37:47 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543830184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2543830184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3693227073 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 452911447 ps |
| CPU time | 9.36 seconds |
| Started | Oct 15 12:37:35 AM UTC 24 |
| Finished | Oct 15 12:37:45 AM UTC 24 |
| Peak memory | 223452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693227073 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3693227073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2997680235 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 308916652 ps |
| CPU time | 7.58 seconds |
| Started | Oct 15 12:37:34 AM UTC 24 |
| Finished | Oct 15 12:37:42 AM UTC 24 |
| Peak memory | 223520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997680235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2997680235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2168920187 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 8649408381 ps |
| CPU time | 116.04 seconds |
| Started | Oct 15 12:37:36 AM UTC 24 |
| Finished | Oct 15 12:39:34 AM UTC 24 |
| Peak memory | 235096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2168920187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2168920187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1638828539 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2025036651 ps |
| CPU time | 9.61 seconds |
| Started | Oct 15 12:37:40 AM UTC 24 |
| Finished | Oct 15 12:37:50 AM UTC 24 |
| Peak memory | 223596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638828539 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1638828539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.758127776 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1971239195 ps |
| CPU time | 121.87 seconds |
| Started | Oct 15 12:37:38 AM UTC 24 |
| Finished | Oct 15 12:39:43 AM UTC 24 |
| Peak memory | 258940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758127776 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.758127776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2249228439 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1033023171 ps |
| CPU time | 16.04 seconds |
| Started | Oct 15 12:37:39 AM UTC 24 |
| Finished | Oct 15 12:37:56 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249228439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2249228439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.776022292 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 179302332 ps |
| CPU time | 9.76 seconds |
| Started | Oct 15 12:37:37 AM UTC 24 |
| Finished | Oct 15 12:37:48 AM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776022292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32k B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.776022292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.2633005066 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1567996055 ps |
| CPU time | 15.6 seconds |
| Started | Oct 15 12:37:37 AM UTC 24 |
| Finished | Oct 15 12:37:54 AM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263300506 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.2633005066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.649459624 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2689440702 ps |
| CPU time | 110.28 seconds |
| Started | Oct 15 12:37:40 AM UTC 24 |
| Finished | Oct 15 12:39:32 AM UTC 24 |
| Peak memory | 232860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=649459624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 9.rom_ctrl_stress_all_with_rand_reset.649459624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest |
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