| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.83 | 99.36 | 92.28 | 97.67 | 100.00 | 98.55 | 97.91 | 99.06 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 63.04 | 63.04 | 94.78 | 94.78 | 69.52 | 69.52 | 41.12 | 41.12 | 40.00 | 40.00 | 89.49 | 89.49 | 93.73 | 93.73 | 12.65 | 12.65 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1824586905 |
| 72.46 | 9.41 | 95.16 | 0.38 | 76.26 | 6.74 | 44.73 | 3.60 | 40.00 | 0.00 | 90.94 | 1.45 | 95.22 | 1.49 | 64.87 | 52.22 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1892577240 |
| 79.21 | 6.76 | 95.16 | 0.00 | 79.07 | 2.81 | 75.90 | 31.18 | 53.33 | 13.33 | 90.94 | 0.00 | 95.22 | 0.00 | 64.87 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.99870090 |
| 84.29 | 5.07 | 95.80 | 0.64 | 80.76 | 1.69 | 83.15 | 7.25 | 73.33 | 20.00 | 93.84 | 2.90 | 95.67 | 0.45 | 67.45 | 2.58 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.1900998303 |
| 87.39 | 3.11 | 95.92 | 0.13 | 81.04 | 0.28 | 83.15 | 0.00 | 93.33 | 20.00 | 94.57 | 0.72 | 95.82 | 0.15 | 67.92 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4225474595 |
| 89.89 | 2.49 | 99.11 | 3.18 | 86.10 | 5.06 | 90.05 | 6.90 | 93.33 | 0.00 | 95.65 | 1.09 | 96.12 | 0.30 | 68.85 | 0.94 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.978631550 |
| 91.97 | 2.08 | 99.11 | 0.00 | 86.10 | 0.00 | 90.35 | 0.30 | 93.33 | 0.00 | 95.65 | 0.00 | 96.12 | 0.00 | 83.14 | 14.29 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1231738443 |
| 93.43 | 1.45 | 99.11 | 0.00 | 89.19 | 3.09 | 94.95 | 4.60 | 93.33 | 0.00 | 96.74 | 1.09 | 96.12 | 0.00 | 84.54 | 1.41 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.492661463 |
| 94.62 | 1.20 | 99.36 | 0.25 | 89.89 | 0.70 | 94.95 | 0.00 | 93.33 | 0.00 | 97.83 | 1.09 | 96.12 | 0.00 | 90.87 | 6.32 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4238114754 |
| 95.79 | 1.17 | 99.36 | 0.00 | 90.03 | 0.14 | 95.95 | 1.00 | 100.00 | 6.67 | 98.19 | 0.36 | 96.12 | 0.00 | 90.87 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.1876198876 |
| 96.36 | 0.57 | 99.36 | 0.00 | 90.03 | 0.00 | 95.95 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 96.12 | 0.00 | 94.85 | 3.98 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.661516563 |
| 96.69 | 0.33 | 99.36 | 0.00 | 90.73 | 0.70 | 96.10 | 0.15 | 100.00 | 0.00 | 98.19 | 0.00 | 96.42 | 0.30 | 96.02 | 1.17 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.4034343187 |
| 97.01 | 0.32 | 99.36 | 0.00 | 91.85 | 1.12 | 96.60 | 0.50 | 100.00 | 0.00 | 98.19 | 0.00 | 96.57 | 0.15 | 96.49 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2163018750 |
| 97.21 | 0.20 | 99.36 | 0.00 | 91.85 | 0.00 | 96.60 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 97.76 | 1.19 | 96.72 | 0.23 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.873873248 |
| 97.35 | 0.13 | 99.36 | 0.00 | 91.85 | 0.00 | 96.60 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 97.76 | 0.00 | 97.66 | 0.94 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1044292340 |
| 97.47 | 0.13 | 99.36 | 0.00 | 91.85 | 0.00 | 97.03 | 0.42 | 100.00 | 0.00 | 98.19 | 0.00 | 97.76 | 0.00 | 98.13 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2443951925 |
| 97.56 | 0.08 | 99.36 | 0.00 | 91.85 | 0.00 | 97.12 | 0.10 | 100.00 | 0.00 | 98.19 | 0.00 | 97.76 | 0.00 | 98.59 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3642310809 |
| 97.63 | 0.07 | 99.36 | 0.00 | 91.99 | 0.14 | 97.12 | 0.00 | 100.00 | 0.00 | 98.55 | 0.36 | 97.76 | 0.00 | 98.59 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.150573678 |
| 97.69 | 0.07 | 99.36 | 0.00 | 91.99 | 0.00 | 97.12 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.76 | 0.00 | 99.06 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3025339680 |
| 97.74 | 0.05 | 99.36 | 0.00 | 91.99 | 0.00 | 97.45 | 0.33 | 100.00 | 0.00 | 98.55 | 0.00 | 97.76 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3020847022 |
| 97.78 | 0.04 | 99.36 | 0.00 | 92.13 | 0.14 | 97.45 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.15 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.962834359 |
| 97.81 | 0.02 | 99.36 | 0.00 | 92.13 | 0.00 | 97.62 | 0.17 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.1355824862 |
| 97.83 | 0.02 | 99.36 | 0.00 | 92.28 | 0.14 | 97.62 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2397932194 |
| 97.83 | 0.01 | 99.36 | 0.00 | 92.28 | 0.00 | 97.65 | 0.03 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.2729594561 |
| 97.83 | 0.01 | 99.36 | 0.00 | 92.28 | 0.00 | 97.67 | 0.03 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.3672336998 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3254643792 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1212086573 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3699341991 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3928935084 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.768815192 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1852174236 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2994465272 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2592831161 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3152503534 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4096869435 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.105650119 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3851166000 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2234743191 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1929995364 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.164089446 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2798617622 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1005922038 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4110663234 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1912471835 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3850844650 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2669053790 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.887770733 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2659835995 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1307722023 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3702164211 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1714392168 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.379461711 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.247169395 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3576583583 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.844013295 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3376467534 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.603512805 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2564728862 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1380299884 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3655670438 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2594279235 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4161213395 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1567903760 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.825157080 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3278896185 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1269574400 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1251639280 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4168261283 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3796571703 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4202576819 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3447635019 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3915315718 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.104371912 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.196053210 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3410957988 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1855143009 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4253847710 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1312483356 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.25165027 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3486881988 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.320960974 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4090910421 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2614886967 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1971788887 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2172246530 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.699697766 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2618658219 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.350376284 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.60945890 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2158661982 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3150596812 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4183523424 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.126581167 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.213964369 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2843749881 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2394343635 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3314713185 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2049041072 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.151936252 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.327289956 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.236431376 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1117905330 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3720014779 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3479630692 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2523717382 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2527398 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3867242714 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3523444634 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3859602618 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1133948786 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3149428985 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3786049091 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.179878118 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2829598440 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4099811038 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3370164368 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3969556224 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3928259094 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1090144610 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2084434236 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3515689204 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3696868152 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3643632912 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4031870540 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1247667397 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.647583391 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2777654526 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2175224541 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2888553373 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2988649682 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2008948799 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1644808066 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.233478989 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3201413611 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3611952227 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.886683419 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3017101724 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1767637766 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1092345126 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4156609899 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3391908124 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.905298020 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1366953258 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3873707770 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1006949856 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3976826874 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1639771345 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1568309268 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3755344445 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.282490007 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1437551234 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2296759280 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2457239103 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.166695260 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.120098261 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1639905203 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2755793652 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2876144322 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.204527428 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2603614505 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3316839773 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.650858757 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.39534013 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.491549586 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2226342017 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.1711103639 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3170815640 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.251407283 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2847888844 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3556820224 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1753956046 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2150143899 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.1491619242 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1518418488 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.506519131 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.2583707814 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1899256504 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3234327064 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.3951487387 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.913083884 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2813139909 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1370674016 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.3031086336 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.1748858009 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2124618144 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3817502767 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4227507326 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.2746828604 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.3839814669 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.3889954852 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.4087175169 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.3392413286 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.515755237 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.3009271798 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.2381438798 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.4225503132 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2618712424 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.3470891830 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4270092173 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.1308452450 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1129460934 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2274084463 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1498869081 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.1791514576 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1006397893 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.15700078 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3587342042 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3216365720 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1928751454 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.4272365019 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2572035141 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.309996226 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.3383976348 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.3450503598 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.527227413 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.4004597133 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2313546036 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.3915965261 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.2102121828 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3358582393 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2820410491 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.894568947 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3595821467 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2360802658 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.2731044612 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3812638337 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3835524104 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.1872133553 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3836678813 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.3624666520 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.3879221748 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2507399503 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.885480767 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2255425334 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1608102214 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.973306733 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.550606760 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3551206352 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3940796017 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2759637775 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.1805346993 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2453307180 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.1847356531 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.1658787384 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2338191392 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2729291016 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.3925236256 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3656289255 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.423093205 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.2051883149 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.1276955901 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.336672761 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.2491491735 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.480405865 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.4131035476 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.3427305659 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.1027189735 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3719688182 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3897266673 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3539056519 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1979368065 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3268313097 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.3310186307 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3014241104 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.642082254 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.39078221 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.644883496 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.378247734 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.1691872672 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1441032170 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3008333062 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3216797935 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3575808560 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.2550774122 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.4203293948 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1318728169 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.94351310 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3297233495 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.3826611750 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.3971815913 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2564168181 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1852417180 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.2466447060 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2912398239 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.3844169480 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.2928921659 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.93724599 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.440038090 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3758841557 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2907329051 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.1069409404 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2513163334 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.342996622 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.2931948159 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2638426411 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.1441562698 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.1009492741 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.844301638 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2369257619 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.289122298 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.150852074 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.1087461956 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.497045305 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.426784604 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.2407556108 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2692657557 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.649021182 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2069755804 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.3989579954 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.1307929926 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.1510715069 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.658818012 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3310471677 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1321944786 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2067061281 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2131568221 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1936384002 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.2656625539 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2623856012 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.1758869279 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.123908335 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.630989159 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2810731557 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2519557579 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2228232719 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.3277246483 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.2489741849 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.2682749719 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2103290800 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.586811723 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2813002347 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2226934484 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.3256091254 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1841660319 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.6052643 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.2476414464 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2694860189 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.1725666725 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.1566020087 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1343963606 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3166997072 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1638613667 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1398555202 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1933206837 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.3640787677 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.3136460936 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.4131710215 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3108548760 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1636385964 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2760550450 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.4293548611 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.1963339783 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1513250280 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.970125737 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3520272828 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.3117812709 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2618833602 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.3482400092 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.351678678 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3743665737 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2840351468 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.361506626 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3144530565 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1991632005 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.789120063 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2311425679 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.1272772568 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3039693077 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3872601372 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.531723658 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.382850385 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2576473634 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2177350915 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3751695260 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.887722369 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3776053489 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.950144078 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1166323097 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.1652984032 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.3137779492 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3816197145 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1532628044 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.2442479877 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.928529991 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1517511056 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.3760656434 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1981018498 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3935704358 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2568005715 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2008037338 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.51194888 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1488257788 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.1723310460 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2084476312 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.2896049972 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1752679133 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.1483232020 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.41138649 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.2014623511 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.502727669 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.839574561 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.304484947 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.4196902961 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.920549577 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2696488742 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.17250984 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.2148522913 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3498566085 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.4263947355 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2752616584 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.1634963681 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2615966575 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1661886276 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1178811686 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.1584394806 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.3304356417 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.3407551691 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1774985802 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.2737483467 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3119141866 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.2944703818 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.2684862688 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1917271387 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.1412023872 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.511639436 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.2442662675 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2323258500 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.1820227408 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3712108837 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.1858969327 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1360228274 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1146174700 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3219068754 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.220121726 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1504447758 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2946244858 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.3949427242 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3669159745 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.3683617230 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.91652763 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3247010323 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1639194839 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.1725255265 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1710709292 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.1495626861 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2183942040 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2543830184 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3693227073 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2997680235 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2168920187 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1638828539 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.758127776 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2249228439 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.776022292 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.2633005066 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.649459624 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1231738443 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:12 AM UTC 24 | 579145419 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.2729594561 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:13 AM UTC 24 | 245065898 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.506519131 | Oct 15 12:37:05 AM UTC 24 | Oct 15 12:37:14 AM UTC 24 | 171288691 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3556820224 | Oct 15 12:37:08 AM UTC 24 | Oct 15 12:37:14 AM UTC 24 | 126002940 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.1711103639 | Oct 15 12:37:05 AM UTC 24 | Oct 15 12:37:15 AM UTC 24 | 165260546 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.1491619242 | Oct 15 12:37:08 AM UTC 24 | Oct 15 12:37:16 AM UTC 24 | 428140219 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2847888844 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:19 AM UTC 24 | 199341811 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.978631550 | Oct 15 12:37:13 AM UTC 24 | Oct 15 12:37:19 AM UTC 24 | 127083077 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.1900998303 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:21 AM UTC 24 | 1072584470 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1824586905 | Oct 15 12:37:13 AM UTC 24 | Oct 15 12:37:21 AM UTC 24 | 1889094264 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.4004597133 | Oct 15 12:38:28 AM UTC 24 | Oct 15 12:38:36 AM UTC 24 | 372845326 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3551206352 | Oct 15 12:37:13 AM UTC 24 | Oct 15 12:37:22 AM UTC 24 | 592085693 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.497045305 | Oct 15 12:37:14 AM UTC 24 | Oct 15 12:37:22 AM UTC 24 | 592741526 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.289122298 | Oct 15 12:37:16 AM UTC 24 | Oct 15 12:37:22 AM UTC 24 | 127075862 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.973306733 | Oct 15 12:37:13 AM UTC 24 | Oct 15 12:37:23 AM UTC 24 | 427367777 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.2150143899 | Oct 15 12:37:08 AM UTC 24 | Oct 15 12:37:23 AM UTC 24 | 295452555 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.2407556108 | Oct 15 12:37:14 AM UTC 24 | Oct 15 12:37:25 AM UTC 24 | 657749236 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3039693077 | Oct 15 12:37:17 AM UTC 24 | Oct 15 12:37:27 AM UTC 24 | 182033752 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1608102214 | Oct 15 12:37:13 AM UTC 24 | Oct 15 12:37:27 AM UTC 24 | 1028044905 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.1087461956 | Oct 15 12:37:15 AM UTC 24 | Oct 15 12:37:27 AM UTC 24 | 359706392 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.2163018750 | Oct 15 12:37:07 AM UTC 24 | Oct 15 12:37:28 AM UTC 24 | 1274760752 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.1272772568 | Oct 15 12:37:18 AM UTC 24 | Oct 15 12:37:29 AM UTC 24 | 2423163649 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.1858969327 | Oct 15 12:37:25 AM UTC 24 | Oct 15 12:37:31 AM UTC 24 | 1414709235 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1146174700 | Oct 15 12:37:23 AM UTC 24 | Oct 15 12:37:32 AM UTC 24 | 177575229 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.789120063 | Oct 15 12:37:22 AM UTC 24 | Oct 15 12:37:32 AM UTC 24 | 163578198 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.3219068754 | Oct 15 12:37:22 AM UTC 24 | Oct 15 12:37:33 AM UTC 24 | 691536873 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3940796017 | Oct 15 12:37:13 AM UTC 24 | Oct 15 12:37:33 AM UTC 24 | 329432765 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.1360228274 | Oct 15 12:37:23 AM UTC 24 | Oct 15 12:37:34 AM UTC 24 | 1314530681 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.3949427242 | Oct 15 12:37:25 AM UTC 24 | Oct 15 12:37:35 AM UTC 24 | 1145317951 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.220121726 | Oct 15 12:37:28 AM UTC 24 | Oct 15 12:37:36 AM UTC 24 | 556412877 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2946244858 | Oct 15 12:37:26 AM UTC 24 | Oct 15 12:37:36 AM UTC 24 | 221614946 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3872601372 | Oct 15 12:37:17 AM UTC 24 | Oct 15 12:37:37 AM UTC 24 | 1668168690 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.1725255265 | Oct 15 12:37:29 AM UTC 24 | Oct 15 12:37:37 AM UTC 24 | 264128385 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1639194839 | Oct 15 12:37:30 AM UTC 24 | Oct 15 12:37:37 AM UTC 24 | 871400496 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.1876198876 | Oct 15 12:37:20 AM UTC 24 | Oct 15 12:37:38 AM UTC 24 | 580719113 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1504447758 | Oct 15 12:37:27 AM UTC 24 | Oct 15 12:37:39 AM UTC 24 | 378051443 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.3683617230 | Oct 15 12:37:34 AM UTC 24 | Oct 15 12:37:39 AM UTC 24 | 372847485 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.2997680235 | Oct 15 12:37:34 AM UTC 24 | Oct 15 12:37:42 AM UTC 24 | 308916652 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2443951925 | Oct 15 12:37:22 AM UTC 24 | Oct 15 12:37:43 AM UTC 24 | 332696423 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.1495626861 | Oct 15 12:37:37 AM UTC 24 | Oct 15 12:37:44 AM UTC 24 | 690340081 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3693227073 | Oct 15 12:37:35 AM UTC 24 | Oct 15 12:37:45 AM UTC 24 | 452911447 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.3247010323 | Oct 15 12:37:33 AM UTC 24 | Oct 15 12:37:45 AM UTC 24 | 293888237 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.661516563 | Oct 15 12:37:38 AM UTC 24 | Oct 15 12:37:47 AM UTC 24 | 182968169 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.2543830184 | Oct 15 12:37:36 AM UTC 24 | Oct 15 12:37:47 AM UTC 24 | 830443573 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.492661463 | Oct 15 12:37:26 AM UTC 24 | Oct 15 12:37:48 AM UTC 24 | 343583888 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.776022292 | Oct 15 12:37:37 AM UTC 24 | Oct 15 12:37:48 AM UTC 24 | 179302332 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3234327064 | Oct 15 12:37:41 AM UTC 24 | Oct 15 12:37:48 AM UTC 24 | 935096191 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.1638828539 | Oct 15 12:37:40 AM UTC 24 | Oct 15 12:37:50 AM UTC 24 | 2025036651 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.1710709292 | Oct 15 12:37:29 AM UTC 24 | Oct 15 12:37:51 AM UTC 24 | 2003858814 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.3951487387 | Oct 15 12:37:41 AM UTC 24 | Oct 15 12:37:53 AM UTC 24 | 130115211 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.1355824862 | Oct 15 12:37:34 AM UTC 24 | Oct 15 12:37:54 AM UTC 24 | 472650014 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.2583707814 | Oct 15 12:37:46 AM UTC 24 | Oct 15 12:37:54 AM UTC 24 | 371208039 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.2633005066 | Oct 15 12:37:37 AM UTC 24 | Oct 15 12:37:54 AM UTC 24 | 1567996055 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3587342042 | Oct 15 12:38:08 AM UTC 24 | Oct 15 12:38:16 AM UTC 24 | 137809404 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.2249228439 | Oct 15 12:37:39 AM UTC 24 | Oct 15 12:37:56 AM UTC 24 | 1033023171 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.3031086336 | Oct 15 12:37:47 AM UTC 24 | Oct 15 12:37:57 AM UTC 24 | 587750024 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.913083884 | Oct 15 12:37:50 AM UTC 24 | Oct 15 12:37:57 AM UTC 24 | 128988310 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.1748858009 | Oct 15 12:37:46 AM UTC 24 | Oct 15 12:38:00 AM UTC 24 | 1734550039 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.3672336998 | Oct 15 12:37:44 AM UTC 24 | Oct 15 12:38:00 AM UTC 24 | 300125584 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3817502767 | Oct 15 12:37:55 AM UTC 24 | Oct 15 12:38:03 AM UTC 24 | 599727499 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.2381438798 | Oct 15 12:37:56 AM UTC 24 | Oct 15 12:38:03 AM UTC 24 | 316539019 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.3839814669 | Oct 15 12:37:52 AM UTC 24 | Oct 15 12:38:04 AM UTC 24 | 137795738 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1518418488 | Oct 15 12:37:08 AM UTC 24 | Oct 15 12:38:05 AM UTC 24 | 284453451 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.3889954852 | Oct 15 12:37:52 AM UTC 24 | Oct 15 12:38:06 AM UTC 24 | 396967255 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.4225503132 | Oct 15 12:37:56 AM UTC 24 | Oct 15 12:38:06 AM UTC 24 | 165213312 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.1370674016 | Oct 15 12:37:48 AM UTC 24 | Oct 15 12:38:07 AM UTC 24 | 291094400 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.3392413286 | Oct 15 12:38:01 AM UTC 24 | Oct 15 12:38:07 AM UTC 24 | 577531814 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.2746828604 | Oct 15 12:37:55 AM UTC 24 | Oct 15 12:38:10 AM UTC 24 | 545163638 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.3009271798 | Oct 15 12:37:57 AM UTC 24 | Oct 15 12:38:11 AM UTC 24 | 386622495 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.99870090 | Oct 15 12:37:23 AM UTC 24 | Oct 15 12:38:16 AM UTC 24 | 3175628067 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1129460934 | Oct 15 12:38:04 AM UTC 24 | Oct 15 12:38:17 AM UTC 24 | 1073280412 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.2274084463 | Oct 15 12:38:01 AM UTC 24 | Oct 15 12:38:18 AM UTC 24 | 456579693 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.3470891830 | Oct 15 12:38:07 AM UTC 24 | Oct 15 12:38:19 AM UTC 24 | 2610389369 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.1308452450 | Oct 15 12:38:05 AM UTC 24 | Oct 15 12:38:20 AM UTC 24 | 208776761 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.1791514576 | Oct 15 12:38:14 AM UTC 24 | Oct 15 12:38:21 AM UTC 24 | 486129635 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.15700078 | Oct 15 12:38:10 AM UTC 24 | Oct 15 12:38:23 AM UTC 24 | 296565854 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.3383976348 | Oct 15 12:38:18 AM UTC 24 | Oct 15 12:38:26 AM UTC 24 | 178872543 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.4272365019 | Oct 15 12:38:20 AM UTC 24 | Oct 15 12:38:28 AM UTC 24 | 165187541 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3216365720 | Oct 15 12:38:07 AM UTC 24 | Oct 15 12:38:29 AM UTC 24 | 1234286806 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.2102121828 | Oct 15 12:38:22 AM UTC 24 | Oct 15 12:38:32 AM UTC 24 | 177957414 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.309996226 | Oct 15 12:38:19 AM UTC 24 | Oct 15 12:38:35 AM UTC 24 | 1075579939 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.251407283 | Oct 15 12:37:05 AM UTC 24 | Oct 15 12:39:07 AM UTC 24 | 357209922 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.3358582393 | Oct 15 12:38:21 AM UTC 24 | Oct 15 12:38:37 AM UTC 24 | 195913807 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.3450503598 | Oct 15 12:38:17 AM UTC 24 | Oct 15 12:38:40 AM UTC 24 | 622934355 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.3915965261 | Oct 15 12:38:25 AM UTC 24 | Oct 15 12:38:40 AM UTC 24 | 557491907 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3812638337 | Oct 15 12:38:29 AM UTC 24 | Oct 15 12:38:40 AM UTC 24 | 152780397 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2311425679 | Oct 15 12:37:18 AM UTC 24 | Oct 15 12:38:41 AM UTC 24 | 5804001691 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.2731044612 | Oct 15 12:38:34 AM UTC 24 | Oct 15 12:38:44 AM UTC 24 | 134290055 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.894568947 | Oct 15 12:38:41 AM UTC 24 | Oct 15 12:38:49 AM UTC 24 | 142002884 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2360802658 | Oct 15 12:38:37 AM UTC 24 | Oct 15 12:38:52 AM UTC 24 | 1491575542 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.91652763 | Oct 15 12:37:31 AM UTC 24 | Oct 15 12:38:53 AM UTC 24 | 5305800063 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3642310809 | Oct 15 12:37:24 AM UTC 24 | Oct 15 12:38:55 AM UTC 24 | 11792002697 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.3879221748 | Oct 15 12:38:41 AM UTC 24 | Oct 15 12:38:56 AM UTC 24 | 548848730 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.3624666520 | Oct 15 12:38:44 AM UTC 24 | Oct 15 12:38:57 AM UTC 24 | 515360421 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.1872133553 | Oct 15 12:38:49 AM UTC 24 | Oct 15 12:38:58 AM UTC 24 | 126150300 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2124618144 | Oct 15 12:37:49 AM UTC 24 | Oct 15 12:38:59 AM UTC 24 | 5069586159 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1892577240 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:39:02 AM UTC 24 | 3084055981 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.1658787384 | Oct 15 12:38:56 AM UTC 24 | Oct 15 12:39:04 AM UTC 24 | 740443764 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.1805346993 | Oct 15 12:38:59 AM UTC 24 | Oct 15 12:39:06 AM UTC 24 | 555638506 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.550606760 | Oct 15 12:37:13 AM UTC 24 | Oct 15 12:39:07 AM UTC 24 | 285901023 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.1847356531 | Oct 15 12:38:57 AM UTC 24 | Oct 15 12:39:08 AM UTC 24 | 655100958 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.426784604 | Oct 15 12:37:16 AM UTC 24 | Oct 15 12:39:09 AM UTC 24 | 308011578 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2507399503 | Oct 15 12:38:41 AM UTC 24 | Oct 15 12:39:09 AM UTC 24 | 512081908 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.2051883149 | Oct 15 12:39:03 AM UTC 24 | Oct 15 12:39:12 AM UTC 24 | 305896261 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.2338191392 | Oct 15 12:38:52 AM UTC 24 | Oct 15 12:39:13 AM UTC 24 | 454803833 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3020847022 | Oct 15 12:37:45 AM UTC 24 | Oct 15 12:39:13 AM UTC 24 | 4467788008 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.1276955901 | Oct 15 12:39:01 AM UTC 24 | Oct 15 12:39:14 AM UTC 24 | 163279159 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4270092173 | Oct 15 12:38:04 AM UTC 24 | Oct 15 12:39:15 AM UTC 24 | 8962646555 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.527227413 | Oct 15 12:38:20 AM UTC 24 | Oct 15 12:39:22 AM UTC 24 | 1779541095 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.3427305659 | Oct 15 12:39:13 AM UTC 24 | Oct 15 12:39:22 AM UTC 24 | 341309754 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.3925236256 | Oct 15 12:39:13 AM UTC 24 | Oct 15 12:39:22 AM UTC 24 | 224376246 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.2491491735 | Oct 15 12:39:17 AM UTC 24 | Oct 15 12:39:24 AM UTC 24 | 371034155 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.4034343187 | Oct 15 12:37:21 AM UTC 24 | Oct 15 12:39:24 AM UTC 24 | 2495960640 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3835524104 | Oct 15 12:38:38 AM UTC 24 | Oct 15 12:39:26 AM UTC 24 | 1058256607 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3170815640 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:39:26 AM UTC 24 | 2925521525 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3268313097 | Oct 15 12:39:17 AM UTC 24 | Oct 15 12:39:27 AM UTC 24 | 1256893281 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.1027189735 | Oct 15 12:39:13 AM UTC 24 | Oct 15 12:39:29 AM UTC 24 | 670668798 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.4131035476 | Oct 15 12:39:13 AM UTC 24 | Oct 15 12:39:29 AM UTC 24 | 804409651 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.423093205 | Oct 15 12:39:12 AM UTC 24 | Oct 15 12:39:29 AM UTC 24 | 732179803 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.150852074 | Oct 15 12:37:14 AM UTC 24 | Oct 15 12:39:30 AM UTC 24 | 7795948743 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3897266673 | Oct 15 12:39:25 AM UTC 24 | Oct 15 12:39:32 AM UTC 24 | 126031335 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.649459624 | Oct 15 12:37:40 AM UTC 24 | Oct 15 12:39:32 AM UTC 24 | 2689440702 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.378247734 | Oct 15 12:39:25 AM UTC 24 | Oct 15 12:39:34 AM UTC 24 | 1071802336 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2168920187 | Oct 15 12:37:36 AM UTC 24 | Oct 15 12:39:34 AM UTC 24 | 8649408381 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2692657557 | Oct 15 12:37:15 AM UTC 24 | Oct 15 12:39:35 AM UTC 24 | 13136712655 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1979368065 | Oct 15 12:39:17 AM UTC 24 | Oct 15 12:39:35 AM UTC 24 | 1282970560 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4225474595 | Oct 15 12:37:27 AM UTC 24 | Oct 15 12:39:36 AM UTC 24 | 7742917718 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.642082254 | Oct 15 12:39:28 AM UTC 24 | Oct 15 12:39:37 AM UTC 24 | 539268174 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2453307180 | Oct 15 12:38:57 AM UTC 24 | Oct 15 12:40:01 AM UTC 24 | 2519856804 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2813139909 | Oct 15 12:37:48 AM UTC 24 | Oct 15 12:39:37 AM UTC 24 | 6233532315 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.2550774122 | Oct 15 12:39:29 AM UTC 24 | Oct 15 12:39:38 AM UTC 24 | 201379790 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.3310186307 | Oct 15 12:39:17 AM UTC 24 | Oct 15 12:39:38 AM UTC 24 | 1807012883 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3008333062 | Oct 15 12:39:32 AM UTC 24 | Oct 15 12:39:40 AM UTC 24 | 213498305 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.644883496 | Oct 15 12:39:28 AM UTC 24 | Oct 15 12:39:40 AM UTC 24 | 225462229 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.1691872672 | Oct 15 12:39:25 AM UTC 24 | Oct 15 12:39:41 AM UTC 24 | 723921917 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.758127776 | Oct 15 12:37:38 AM UTC 24 | Oct 15 12:39:43 AM UTC 24 | 1971239195 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2255425334 | Oct 15 12:37:13 AM UTC 24 | Oct 15 12:39:43 AM UTC 24 | 2505188900 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.94351310 | Oct 15 12:39:37 AM UTC 24 | Oct 15 12:39:45 AM UTC 24 | 167196001 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.3575808560 | Oct 15 12:39:30 AM UTC 24 | Oct 15 12:39:45 AM UTC 24 | 1492054915 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.3971815913 | Oct 15 12:39:35 AM UTC 24 | Oct 15 12:39:46 AM UTC 24 | 134022191 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.2564168181 | Oct 15 12:39:33 AM UTC 24 | Oct 15 12:39:46 AM UTC 24 | 798170341 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.2466447060 | Oct 15 12:39:40 AM UTC 24 | Oct 15 12:39:48 AM UTC 24 | 372559558 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.2928921659 | Oct 15 12:39:38 AM UTC 24 | Oct 15 12:39:48 AM UTC 24 | 607033181 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.4203293948 | Oct 15 12:39:28 AM UTC 24 | Oct 15 12:39:49 AM UTC 24 | 1237156281 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3669159745 | Oct 15 12:37:28 AM UTC 24 | Oct 15 12:39:49 AM UTC 24 | 3072428660 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2759637775 | Oct 15 12:37:13 AM UTC 24 | Oct 15 12:39:49 AM UTC 24 | 7268200498 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4227507326 | Oct 15 12:37:54 AM UTC 24 | Oct 15 12:39:52 AM UTC 24 | 8720344863 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.3826611750 | Oct 15 12:39:36 AM UTC 24 | Oct 15 12:39:53 AM UTC 24 | 299910381 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2513163334 | Oct 15 12:39:44 AM UTC 24 | Oct 15 12:39:54 AM UTC 24 | 506880875 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.3844169480 | Oct 15 12:39:39 AM UTC 24 | Oct 15 12:39:55 AM UTC 24 | 304322736 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3758841557 | Oct 15 12:39:47 AM UTC 24 | Oct 15 12:39:55 AM UTC 24 | 171201732 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.2931948159 | Oct 15 12:39:50 AM UTC 24 | Oct 15 12:39:57 AM UTC 24 | 315801201 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.93724599 | Oct 15 12:39:38 AM UTC 24 | Oct 15 12:39:57 AM UTC 24 | 340995035 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.342996622 | Oct 15 12:39:41 AM UTC 24 | Oct 15 12:39:58 AM UTC 24 | 790757007 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1006397893 | Oct 15 12:38:08 AM UTC 24 | Oct 15 12:39:58 AM UTC 24 | 2222010526 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.1009492741 | Oct 15 12:39:49 AM UTC 24 | Oct 15 12:39:59 AM UTC 24 | 592208568 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.1069409404 | Oct 15 12:39:46 AM UTC 24 | Oct 15 12:39:59 AM UTC 24 | 296661773 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1753956046 | Oct 15 12:37:08 AM UTC 24 | Oct 15 12:40:00 AM UTC 24 | 3359889720 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2618712424 | Oct 15 12:37:58 AM UTC 24 | Oct 15 12:40:02 AM UTC 24 | 6231681221 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1498869081 | Oct 15 12:38:06 AM UTC 24 | Oct 15 12:40:03 AM UTC 24 | 14651619103 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.1441562698 | Oct 15 12:39:50 AM UTC 24 | Oct 15 12:40:04 AM UTC 24 | 291654667 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.1307929926 | Oct 15 12:39:53 AM UTC 24 | Oct 15 12:40:04 AM UTC 24 | 783987859 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.649021182 | Oct 15 12:39:58 AM UTC 24 | Oct 15 12:40:06 AM UTC 24 | 2090630929 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1928751454 | Oct 15 12:38:11 AM UTC 24 | Oct 15 12:40:07 AM UTC 24 | 5159678390 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.844301638 | Oct 15 12:39:47 AM UTC 24 | Oct 15 12:40:07 AM UTC 24 | 336559535 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.3989579954 | Oct 15 12:39:56 AM UTC 24 | Oct 15 12:40:08 AM UTC 24 | 288110762 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.2067061281 | Oct 15 12:39:59 AM UTC 24 | Oct 15 12:40:08 AM UTC 24 | 136969824 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3310471677 | Oct 15 12:40:01 AM UTC 24 | Oct 15 12:40:09 AM UTC 24 | 164341063 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1899256504 | Oct 15 12:37:43 AM UTC 24 | Oct 15 12:40:10 AM UTC 24 | 7477536463 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.515755237 | Oct 15 12:37:57 AM UTC 24 | Oct 15 12:40:12 AM UTC 24 | 8390841275 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3836678813 | Oct 15 12:38:42 AM UTC 24 | Oct 15 12:40:13 AM UTC 24 | 1709425020 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.2656625539 | Oct 15 12:40:07 AM UTC 24 | Oct 15 12:40:13 AM UTC 24 | 528532527 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.123908335 | Oct 15 12:40:03 AM UTC 24 | Oct 15 12:40:14 AM UTC 24 | 174537768 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.150573678 | Oct 15 12:40:00 AM UTC 24 | Oct 15 12:40:15 AM UTC 24 | 731503522 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.2131568221 | Oct 15 12:39:58 AM UTC 24 | Oct 15 12:40:18 AM UTC 24 | 888276533 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.2489741849 | Oct 15 12:40:08 AM UTC 24 | Oct 15 12:40:18 AM UTC 24 | 181105582 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.1758869279 | Oct 15 12:40:05 AM UTC 24 | Oct 15 12:40:19 AM UTC 24 | 294131511 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2519557579 | Oct 15 12:40:12 AM UTC 24 | Oct 15 12:40:19 AM UTC 24 | 216840836 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1318728169 | Oct 15 12:39:31 AM UTC 24 | Oct 15 12:40:20 AM UTC 24 | 4055542724 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.630989159 | Oct 15 12:40:02 AM UTC 24 | Oct 15 12:40:21 AM UTC 24 | 347392670 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.336672761 | Oct 15 12:39:13 AM UTC 24 | Oct 15 12:40:22 AM UTC 24 | 10344697677 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.3277246483 | Oct 15 12:40:09 AM UTC 24 | Oct 15 12:40:23 AM UTC 24 | 1410297886 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.3256091254 | Oct 15 12:40:14 AM UTC 24 | Oct 15 12:40:24 AM UTC 24 | 176717675 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.1510715069 | Oct 15 12:39:52 AM UTC 24 | Oct 15 12:40:25 AM UTC 24 | 723379780 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3595821467 | Oct 15 12:38:36 AM UTC 24 | Oct 15 12:40:26 AM UTC 24 | 7869918224 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2369257619 | Oct 15 12:39:50 AM UTC 24 | Oct 15 12:40:28 AM UTC 24 | 1008001226 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.586811723 | Oct 15 12:40:19 AM UTC 24 | Oct 15 12:40:28 AM UTC 24 | 168428405 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.1566020087 | Oct 15 12:40:20 AM UTC 24 | Oct 15 12:40:29 AM UTC 24 | 177653901 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2226934484 | Oct 15 12:40:15 AM UTC 24 | Oct 15 12:40:29 AM UTC 24 | 294082488 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1343963606 | Oct 15 12:40:19 AM UTC 24 | Oct 15 12:40:30 AM UTC 24 | 452976374 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.2476414464 | Oct 15 12:40:23 AM UTC 24 | Oct 15 12:40:32 AM UTC 24 | 553198751 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.2682749719 | Oct 15 12:40:08 AM UTC 24 | Oct 15 12:40:32 AM UTC 24 | 1141963623 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.1841660319 | Oct 15 12:40:13 AM UTC 24 | Oct 15 12:40:32 AM UTC 24 | 852646672 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.3640787677 | Oct 15 12:40:25 AM UTC 24 | Oct 15 12:40:36 AM UTC 24 | 174747891 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.440038090 | Oct 15 12:39:40 AM UTC 24 | Oct 15 12:40:36 AM UTC 24 | 3696400657 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3014241104 | Oct 15 12:39:22 AM UTC 24 | Oct 15 12:40:36 AM UTC 24 | 1395517458 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.3136460936 | Oct 15 12:40:24 AM UTC 24 | Oct 15 12:40:36 AM UTC 24 | 168965965 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.1725666725 | Oct 15 12:40:22 AM UTC 24 | Oct 15 12:40:36 AM UTC 24 | 215613727 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1638613667 | Oct 15 12:40:29 AM UTC 24 | Oct 15 12:40:37 AM UTC 24 | 293042875 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.3108548760 | Oct 15 12:40:33 AM UTC 24 | Oct 15 12:40:40 AM UTC 24 | 307290304 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.4293548611 | Oct 15 12:40:30 AM UTC 24 | Oct 15 12:40:41 AM UTC 24 | 1059775464 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1933206837 | Oct 15 12:40:27 AM UTC 24 | Oct 15 12:40:43 AM UTC 24 | 209132950 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2810731557 | Oct 15 12:40:05 AM UTC 24 | Oct 15 12:40:44 AM UTC 24 | 1516732980 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2618833602 | Oct 15 12:40:36 AM UTC 24 | Oct 15 12:40:45 AM UTC 24 | 140089127 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.970125737 | Oct 15 12:40:38 AM UTC 24 | Oct 15 12:40:45 AM UTC 24 | 958593570 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1517511056 | Oct 15 12:41:09 AM UTC 24 | Oct 15 12:41:26 AM UTC 24 | 208298255 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.1963339783 | Oct 15 12:40:30 AM UTC 24 | Oct 15 12:40:47 AM UTC 24 | 1160466979 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2760550450 | Oct 15 12:40:32 AM UTC 24 | Oct 15 12:40:49 AM UTC 24 | 760683534 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1936384002 | Oct 15 12:40:00 AM UTC 24 | Oct 15 12:40:50 AM UTC 24 | 4770152094 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.351678678 | Oct 15 12:40:46 AM UTC 24 | Oct 15 12:40:52 AM UTC 24 | 537947260 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.361506626 | Oct 15 12:40:42 AM UTC 24 | Oct 15 12:40:52 AM UTC 24 | 701457539 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.3117812709 | Oct 15 12:40:38 AM UTC 24 | Oct 15 12:40:54 AM UTC 24 | 1075112044 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3144530565 | Oct 15 12:40:41 AM UTC 24 | Oct 15 12:40:55 AM UTC 24 | 3951695858 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.2840351468 | Oct 15 12:40:46 AM UTC 24 | Oct 15 12:40:57 AM UTC 24 | 207194369 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3751695260 | Oct 15 12:40:50 AM UTC 24 | Oct 15 12:40:58 AM UTC 24 | 137461984 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.382850385 | Oct 15 12:40:53 AM UTC 24 | Oct 15 12:41:01 AM UTC 24 | 123756303 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2177350915 | Oct 15 12:40:51 AM UTC 24 | Oct 15 12:41:04 AM UTC 24 | 1692785163 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2907329051 | Oct 15 12:39:45 AM UTC 24 | Oct 15 12:41:04 AM UTC 24 | 5013456101 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.3482400092 | Oct 15 12:40:36 AM UTC 24 | Oct 15 12:41:05 AM UTC 24 | 443417437 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.3816197145 | Oct 15 12:40:54 AM UTC 24 | Oct 15 12:41:08 AM UTC 24 | 1136279070 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2623856012 | Oct 15 12:40:05 AM UTC 24 | Oct 15 12:41:10 AM UTC 24 | 1465020083 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2183942040 | Oct 15 12:37:35 AM UTC 24 | Oct 15 12:41:11 AM UTC 24 | 13226601389 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.885480767 | Oct 15 12:38:45 AM UTC 24 | Oct 15 12:41:14 AM UTC 24 | 21386791266 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.887722369 | Oct 15 12:40:48 AM UTC 24 | Oct 15 12:41:14 AM UTC 24 | 329428730 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3656289255 | Oct 15 12:39:05 AM UTC 24 | Oct 15 12:41:15 AM UTC 24 | 2508043472 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.950144078 | Oct 15 12:41:09 AM UTC 24 | Oct 15 12:41:18 AM UTC 24 | 170272883 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.3137779492 | Oct 15 12:41:07 AM UTC 24 | Oct 15 12:41:19 AM UTC 24 | 140033970 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.3760656434 | Oct 15 12:41:09 AM UTC 24 | Oct 15 12:41:20 AM UTC 24 | 310205679 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3297233495 | Oct 15 12:39:36 AM UTC 24 | Oct 15 12:41:21 AM UTC 24 | 7417998710 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.2442479877 | Oct 15 12:41:12 AM UTC 24 | Oct 15 12:41:21 AM UTC 24 | 300148163 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1488257788 | Oct 15 12:41:16 AM UTC 24 | Oct 15 12:41:23 AM UTC 24 | 135904785 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.1652984032 | Oct 15 12:41:09 AM UTC 24 | Oct 15 12:41:23 AM UTC 24 | 542578764 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.531723658 | Oct 15 12:37:20 AM UTC 24 | Oct 15 12:41:24 AM UTC 24 | 3100897055 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2228232719 | Oct 15 12:40:09 AM UTC 24 | Oct 15 12:41:28 AM UTC 24 | 2392114547 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2313546036 | Oct 15 12:38:24 AM UTC 24 | Oct 15 12:41:28 AM UTC 24 | 4219486721 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3719688182 | Oct 15 12:39:13 AM UTC 24 | Oct 15 12:41:29 AM UTC 24 | 14956185425 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.1723310460 | Oct 15 12:41:15 AM UTC 24 | Oct 15 12:41:30 AM UTC 24 | 311232552 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2820410491 | Oct 15 12:38:26 AM UTC 24 | Oct 15 12:41:31 AM UTC 24 | 3995698217 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3539056519 | Oct 15 12:39:17 AM UTC 24 | Oct 15 12:41:31 AM UTC 24 | 17110803566 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.51194888 | Oct 15 12:41:19 AM UTC 24 | Oct 15 12:41:32 AM UTC 24 | 1033838874 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.41138649 | Oct 15 12:41:22 AM UTC 24 | Oct 15 12:41:32 AM UTC 24 | 757237124 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1981018498 | Oct 15 12:41:09 AM UTC 24 | Oct 15 12:41:32 AM UTC 24 | 1221450250 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.2014623511 | Oct 15 12:41:22 AM UTC 24 | Oct 15 12:41:33 AM UTC 24 | 659368695 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2638426411 | Oct 15 12:39:49 AM UTC 24 | Oct 15 12:41:34 AM UTC 24 | 1784448444 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2568005715 | Oct 15 12:41:21 AM UTC 24 | Oct 15 12:41:35 AM UTC 24 | 6123399315 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3166997072 | Oct 15 12:40:22 AM UTC 24 | Oct 15 12:41:36 AM UTC 24 | 3406112927 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.2896049972 | Oct 15 12:41:27 AM UTC 24 | Oct 15 12:41:36 AM UTC 24 | 556996377 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.2696488742 | Oct 15 12:41:29 AM UTC 24 | Oct 15 12:41:37 AM UTC 24 | 445727503 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.920549577 | Oct 15 12:41:29 AM UTC 24 | Oct 15 12:41:40 AM UTC 24 | 618326379 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.480405865 | Oct 15 12:39:13 AM UTC 24 | Oct 15 12:41:40 AM UTC 24 | 2935656666 ps |
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