| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.22 | 96.89 | 91.85 | 97.67 | 100.00 | 98.28 | 97.45 | 98.37 |
| T313 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.1678795444 | Feb 08 02:35:13 PM UTC 25 | Feb 08 02:35:20 PM UTC 25 | 129166233 ps | ||
| T314 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1038051045 | Feb 08 02:35:24 PM UTC 25 | Feb 08 02:35:32 PM UTC 25 | 97738410 ps | ||
| T315 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.3082421910 | Feb 08 02:35:22 PM UTC 25 | Feb 08 02:35:48 PM UTC 25 | 1436951810 ps | ||
| T316 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.199999776 | Feb 08 02:33:53 PM UTC 25 | Feb 08 02:35:51 PM UTC 25 | 1666084264 ps | ||
| T317 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.784530357 | Feb 08 02:35:49 PM UTC 25 | Feb 08 02:36:07 PM UTC 25 | 253597241 ps | ||
| T318 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.185605182 | Feb 08 02:36:08 PM UTC 25 | Feb 08 02:36:15 PM UTC 25 | 269292750 ps | ||
| T319 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.199588042 | Feb 08 02:36:16 PM UTC 25 | Feb 08 02:36:29 PM UTC 25 | 642898029 ps | ||
| T320 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.1664833719 | Feb 08 02:36:30 PM UTC 25 | Feb 08 02:36:41 PM UTC 25 | 397543318 ps | ||
| T321 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.678759715 | Feb 08 02:36:41 PM UTC 25 | Feb 08 02:36:55 PM UTC 25 | 2251701704 ps | ||
| T322 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1209186642 | Feb 08 02:34:48 PM UTC 25 | Feb 08 02:37:00 PM UTC 25 | 7812022555 ps | ||
| T323 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.567583786 | Feb 08 02:37:00 PM UTC 25 | Feb 08 02:37:07 PM UTC 25 | 89188139 ps | ||
| T49 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.59998850 | Feb 08 02:06:01 PM UTC 25 | Feb 08 02:37:27 PM UTC 25 | 45541361293 ps | ||
| T324 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.2212736955 | Feb 08 02:37:07 PM UTC 25 | Feb 08 02:37:30 PM UTC 25 | 286778890 ps | ||
| T325 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.3682610414 | Feb 08 02:37:27 PM UTC 25 | Feb 08 02:37:36 PM UTC 25 | 190728481 ps | ||
| T326 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.2915664509 | Feb 08 02:37:31 PM UTC 25 | Feb 08 02:37:44 PM UTC 25 | 170242487 ps | ||
| T327 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.960089007 | Feb 08 02:37:45 PM UTC 25 | Feb 08 02:37:55 PM UTC 25 | 733478617 ps | ||
| T328 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2440390272 | Feb 08 02:35:33 PM UTC 25 | Feb 08 02:38:36 PM UTC 25 | 9933769826 ps | ||
| T329 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2587989129 | Feb 08 02:36:35 PM UTC 25 | Feb 08 02:38:41 PM UTC 25 | 4852021315 ps | ||
| T50 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3678550578 | Feb 08 02:15:14 PM UTC 25 | Feb 08 02:40:15 PM UTC 25 | 173936054083 ps | ||
| T330 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3762714170 | Feb 08 02:37:29 PM UTC 25 | Feb 08 02:40:33 PM UTC 25 | 13136331793 ps | ||
| T51 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1838442379 | Feb 08 02:08:33 PM UTC 25 | Feb 08 02:42:05 PM UTC 25 | 179864112126 ps | ||
| T52 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1938701445 | Feb 08 02:27:46 PM UTC 25 | Feb 08 02:42:15 PM UTC 25 | 16802359646 ps | ||
| T53 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3541567770 | Feb 08 02:31:27 PM UTC 25 | Feb 08 02:44:48 PM UTC 25 | 36774231333 ps | ||
| T54 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2244348122 | Feb 08 02:17:26 PM UTC 25 | Feb 08 02:48:09 PM UTC 25 | 164904621383 ps | ||
| T331 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2629457101 | Feb 08 02:09:40 PM UTC 25 | Feb 08 02:57:33 PM UTC 25 | 529037456152 ps | ||
| T332 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3014554236 | Feb 08 02:13:37 PM UTC 25 | Feb 08 03:00:03 PM UTC 25 | 110430967178 ps | ||
| T128 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.648737190 | Feb 08 02:19:13 PM UTC 25 | Feb 08 03:00:10 PM UTC 25 | 95766328450 ps | ||
| T333 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.4195571657 | Feb 08 02:10:00 PM UTC 25 | Feb 08 03:07:59 PM UTC 25 | 73755368267 ps | ||
| T334 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1357813243 | Feb 08 02:05:41 PM UTC 25 | Feb 08 04:00:05 PM UTC 25 | 14385296618 ps | ||
| T126 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2839069363 | Feb 08 02:10:31 PM UTC 25 | Feb 08 04:08:21 PM UTC 25 | 13156579533 ps | ||
| T335 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.4146840023 | Feb 08 02:16:02 PM UTC 25 | Feb 08 04:20:38 PM UTC 25 | 50459039759 ps | ||
| T336 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3446191773 | Feb 08 02:22:57 PM UTC 25 | Feb 08 04:36:44 PM UTC 25 | 38038889730 ps | ||
| T69 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.182671497 | Feb 08 02:37:56 PM UTC 25 | Feb 08 02:38:29 PM UTC 25 | 1994952308 ps | ||
| T337 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2983930885 | Feb 08 02:38:30 PM UTC 25 | Feb 08 02:38:43 PM UTC 25 | 127262274 ps | ||
| T338 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3940490560 | Feb 08 02:38:42 PM UTC 25 | Feb 08 02:38:50 PM UTC 25 | 334263086 ps | ||
| T339 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2204689021 | Feb 08 02:38:44 PM UTC 25 | Feb 08 02:38:52 PM UTC 25 | 86687763 ps | ||
| T70 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2056937061 | Feb 08 02:38:52 PM UTC 25 | Feb 08 02:39:02 PM UTC 25 | 168001827 ps | ||
| T71 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3538910744 | Feb 08 02:38:51 PM UTC 25 | Feb 08 02:39:03 PM UTC 25 | 508385399 ps | ||
| T122 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1533466096 | Feb 08 02:38:59 PM UTC 25 | Feb 08 02:39:09 PM UTC 25 | 263351895 ps | ||
| T76 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2434586561 | Feb 08 02:39:03 PM UTC 25 | Feb 08 02:39:12 PM UTC 25 | 249723473 ps | ||
| T77 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3399011519 | Feb 08 02:39:02 PM UTC 25 | Feb 08 02:39:15 PM UTC 25 | 492886442 ps | ||
| T340 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2220365458 | Feb 08 02:39:10 PM UTC 25 | Feb 08 02:39:18 PM UTC 25 | 110046189 ps | ||
| T341 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3075096449 | Feb 08 02:39:16 PM UTC 25 | Feb 08 02:39:30 PM UTC 25 | 149148477 ps | ||
| T342 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4062934428 | Feb 08 02:39:31 PM UTC 25 | Feb 08 02:39:39 PM UTC 25 | 145790084 ps | ||
| T343 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2269183012 | Feb 08 02:39:41 PM UTC 25 | Feb 08 02:39:48 PM UTC 25 | 489985971 ps | ||
| T78 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1281795482 | Feb 08 02:39:14 PM UTC 25 | Feb 08 02:39:53 PM UTC 25 | 798189546 ps | ||
| T123 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2817794940 | Feb 08 02:39:49 PM UTC 25 | Feb 08 02:40:02 PM UTC 25 | 1052453193 ps | ||
| T344 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.21049709 | Feb 08 02:39:54 PM UTC 25 | Feb 08 02:40:03 PM UTC 25 | 172095560 ps | ||
| T345 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2076348216 | Feb 08 02:40:03 PM UTC 25 | Feb 08 02:40:11 PM UTC 25 | 440388596 ps | ||
| T79 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3849868943 | Feb 08 02:40:04 PM UTC 25 | Feb 08 02:40:11 PM UTC 25 | 333074033 ps | ||
| T63 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.982430956 | Feb 08 02:38:37 PM UTC 25 | Feb 08 02:40:13 PM UTC 25 | 2407271698 ps | ||
| T64 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2115107450 | Feb 08 02:39:19 PM UTC 25 | Feb 08 02:40:14 PM UTC 25 | 960455139 ps | ||
| T115 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.358065233 | Feb 08 02:40:11 PM UTC 25 | Feb 08 02:40:19 PM UTC 25 | 415594544 ps | ||
| T346 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.175532098 | Feb 08 02:40:12 PM UTC 25 | Feb 08 02:40:23 PM UTC 25 | 829020203 ps | ||
| T347 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1319755182 | Feb 08 02:40:14 PM UTC 25 | Feb 08 02:40:26 PM UTC 25 | 499781691 ps | ||
| T348 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3845285355 | Feb 08 02:40:20 PM UTC 25 | Feb 08 02:40:29 PM UTC 25 | 598259654 ps | ||
| T349 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1250748904 | Feb 08 02:40:24 PM UTC 25 | Feb 08 02:40:32 PM UTC 25 | 256587425 ps | ||
| T80 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1917821515 | Feb 08 02:40:30 PM UTC 25 | Feb 08 02:40:39 PM UTC 25 | 1045175343 ps | ||
| T350 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.754150649 | Feb 08 02:40:33 PM UTC 25 | Feb 08 02:40:41 PM UTC 25 | 175570035 ps | ||
| T351 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2171958466 | Feb 08 02:40:28 PM UTC 25 | Feb 08 02:40:41 PM UTC 25 | 282165933 ps | ||
| T81 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.67644686 | Feb 08 02:40:13 PM UTC 25 | Feb 08 02:40:41 PM UTC 25 | 2170549569 ps | ||
| T82 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.831907680 | Feb 08 02:40:34 PM UTC 25 | Feb 08 02:40:42 PM UTC 25 | 516492336 ps | ||
| T116 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2452610337 | Feb 08 02:40:40 PM UTC 25 | Feb 08 02:40:48 PM UTC 25 | 334039760 ps | ||
| T352 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2519295223 | Feb 08 02:40:42 PM UTC 25 | Feb 08 02:40:53 PM UTC 25 | 508539133 ps | ||
| T353 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4174084442 | Feb 08 02:40:42 PM UTC 25 | Feb 08 02:40:54 PM UTC 25 | 133336992 ps | ||
| T354 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3123306246 | Feb 08 02:40:49 PM UTC 25 | Feb 08 02:40:57 PM UTC 25 | 129181640 ps | ||
| T355 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3379090864 | Feb 08 02:40:54 PM UTC 25 | Feb 08 02:41:00 PM UTC 25 | 85822209 ps | ||
| T356 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.313117685 | Feb 08 02:40:55 PM UTC 25 | Feb 08 02:41:05 PM UTC 25 | 341217167 ps | ||
| T357 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1465631305 | Feb 08 02:40:58 PM UTC 25 | Feb 08 02:41:05 PM UTC 25 | 351578311 ps | ||
| T358 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3465350418 | Feb 08 02:41:01 PM UTC 25 | Feb 08 02:41:10 PM UTC 25 | 256219638 ps | ||
| T65 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3501247363 | Feb 08 02:40:16 PM UTC 25 | Feb 08 02:41:15 PM UTC 25 | 2108114049 ps | ||
| T88 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2772635186 | Feb 08 02:41:06 PM UTC 25 | Feb 08 02:41:15 PM UTC 25 | 251245618 ps | ||
| T359 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1371521879 | Feb 08 02:41:11 PM UTC 25 | Feb 08 02:41:19 PM UTC 25 | 265866968 ps | ||
| T117 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1120223460 | Feb 08 02:41:06 PM UTC 25 | Feb 08 02:41:21 PM UTC 25 | 508076471 ps | ||
| T360 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1355272947 | Feb 08 02:41:23 PM UTC 25 | Feb 08 02:41:30 PM UTC 25 | 86626235 ps | ||
| T361 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3199809883 | Feb 08 02:41:17 PM UTC 25 | Feb 08 02:41:33 PM UTC 25 | 498303729 ps | ||
| T362 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1340870170 | Feb 08 02:41:31 PM UTC 25 | Feb 08 02:41:39 PM UTC 25 | 335877472 ps | ||
| T89 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4181210234 | Feb 08 02:40:42 PM UTC 25 | Feb 08 02:41:45 PM UTC 25 | 3071102811 ps | ||
| T90 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.266916247 | Feb 08 02:41:34 PM UTC 25 | Feb 08 02:41:46 PM UTC 25 | 507757080 ps | ||
| T363 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.993983286 | Feb 08 02:41:40 PM UTC 25 | Feb 08 02:41:48 PM UTC 25 | 449557906 ps | ||
| T364 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3479515043 | Feb 08 02:41:45 PM UTC 25 | Feb 08 02:41:52 PM UTC 25 | 415566672 ps | ||
| T127 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3690649411 | Feb 08 02:41:15 PM UTC 25 | Feb 08 02:41:53 PM UTC 25 | 1569259581 ps | ||
| T91 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1574995346 | Feb 08 02:41:47 PM UTC 25 | Feb 08 02:41:55 PM UTC 25 | 479156200 ps | ||
| T118 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1159756536 | Feb 08 02:41:49 PM UTC 25 | Feb 08 02:41:59 PM UTC 25 | 498225883 ps | ||
| T365 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.319896213 | Feb 08 02:41:53 PM UTC 25 | Feb 08 02:42:02 PM UTC 25 | 145798440 ps | ||
| T366 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.712011272 | Feb 08 02:42:02 PM UTC 25 | Feb 08 02:42:10 PM UTC 25 | 89040364 ps | ||
| T367 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.727960653 | Feb 08 02:41:56 PM UTC 25 | Feb 08 02:42:11 PM UTC 25 | 662559932 ps | ||
| T119 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1064834189 | Feb 08 02:42:05 PM UTC 25 | Feb 08 02:42:14 PM UTC 25 | 499657865 ps | ||
| T133 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.441670377 | Feb 08 02:41:21 PM UTC 25 | Feb 08 02:42:18 PM UTC 25 | 262812291 ps | ||
| T368 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2875698111 | Feb 08 02:42:10 PM UTC 25 | Feb 08 02:42:22 PM UTC 25 | 670142037 ps | ||
| T369 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3656842061 | Feb 08 02:42:19 PM UTC 25 | Feb 08 02:42:27 PM UTC 25 | 171731941 ps | ||
| T370 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3615505647 | Feb 08 02:42:14 PM UTC 25 | Feb 08 02:42:31 PM UTC 25 | 133116549 ps | ||
| T120 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1033110412 | Feb 08 02:42:23 PM UTC 25 | Feb 08 02:42:32 PM UTC 25 | 594565493 ps | ||
| T371 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3960721835 | Feb 08 02:41:54 PM UTC 25 | Feb 08 02:42:35 PM UTC 25 | 2276896003 ps | ||
| T136 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2358098773 | Feb 08 02:40:43 PM UTC 25 | Feb 08 02:42:35 PM UTC 25 | 507562135 ps | ||
| T372 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1404786883 | Feb 08 02:42:28 PM UTC 25 | Feb 08 02:42:40 PM UTC 25 | 144529565 ps | ||
| T121 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2779345118 | Feb 08 02:42:36 PM UTC 25 | Feb 08 02:42:43 PM UTC 25 | 126911277 ps | ||
| T373 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2116082976 | Feb 08 02:42:33 PM UTC 25 | Feb 08 02:42:44 PM UTC 25 | 126442043 ps | ||
| T374 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3960767704 | Feb 08 02:42:41 PM UTC 25 | Feb 08 02:42:47 PM UTC 25 | 174674305 ps | ||
| T97 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2043108391 | Feb 08 02:42:11 PM UTC 25 | Feb 08 02:42:50 PM UTC 25 | 2230162287 ps | ||
| T375 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1418533119 | Feb 08 02:42:44 PM UTC 25 | Feb 08 02:42:52 PM UTC 25 | 131660527 ps | ||
| T376 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3839671501 | Feb 08 02:42:48 PM UTC 25 | Feb 08 02:43:02 PM UTC 25 | 287777627 ps | ||
| T92 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3342148022 | Feb 08 02:42:53 PM UTC 25 | Feb 08 02:43:02 PM UTC 25 | 279428421 ps | ||
| T377 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3207197923 | Feb 08 02:43:02 PM UTC 25 | Feb 08 02:43:12 PM UTC 25 | 501051361 ps | ||
| T93 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1630121588 | Feb 08 02:42:32 PM UTC 25 | Feb 08 02:43:12 PM UTC 25 | 544514547 ps | ||
| T378 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2374727217 | Feb 08 02:43:03 PM UTC 25 | Feb 08 02:43:14 PM UTC 25 | 716374457 ps | ||
| T379 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1202911825 | Feb 08 02:42:45 PM UTC 25 | Feb 08 02:43:16 PM UTC 25 | 566204317 ps | ||
| T380 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2282224206 | Feb 08 02:43:17 PM UTC 25 | Feb 08 02:43:25 PM UTC 25 | 251890229 ps | ||
| T94 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.118294482 | Feb 08 02:43:38 PM UTC 25 | Feb 08 02:43:48 PM UTC 25 | 520796024 ps | ||
| T381 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.976305681 | Feb 08 02:43:12 PM UTC 25 | Feb 08 02:43:27 PM UTC 25 | 499842826 ps | ||
| T382 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1424787414 | Feb 08 02:43:27 PM UTC 25 | Feb 08 02:43:34 PM UTC 25 | 348826643 ps | ||
| T137 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3795427643 | Feb 08 02:42:36 PM UTC 25 | Feb 08 02:43:35 PM UTC 25 | 277554286 ps | ||
| T129 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3600238302 | Feb 08 02:41:59 PM UTC 25 | Feb 08 02:43:36 PM UTC 25 | 926893251 ps | ||
| T383 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.271598032 | Feb 08 02:43:28 PM UTC 25 | Feb 08 02:43:37 PM UTC 25 | 294830797 ps | ||
| T384 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1477223417 | Feb 08 02:43:12 PM UTC 25 | Feb 08 02:43:40 PM UTC 25 | 7393170479 ps | ||
| T385 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3024168723 | Feb 08 02:43:36 PM UTC 25 | Feb 08 02:43:46 PM UTC 25 | 176309394 ps | ||
| T386 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.29390879 | Feb 08 02:43:41 PM UTC 25 | Feb 08 02:43:49 PM UTC 25 | 334849909 ps | ||
| T130 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.223849576 | Feb 08 02:42:51 PM UTC 25 | Feb 08 02:43:52 PM UTC 25 | 208290609 ps | ||
| T131 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.130522374 | Feb 08 02:43:14 PM UTC 25 | Feb 08 02:43:56 PM UTC 25 | 384032916 ps | ||
| T100 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1516608924 | Feb 08 02:43:35 PM UTC 25 | Feb 08 02:43:57 PM UTC 25 | 380566414 ps | ||
| T387 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2294939574 | Feb 08 02:43:47 PM UTC 25 | Feb 08 02:44:00 PM UTC 25 | 1054161699 ps | ||
| T101 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3215250853 | Feb 08 02:43:57 PM UTC 25 | Feb 08 02:44:04 PM UTC 25 | 88715407 ps | ||
| T388 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2583065840 | Feb 08 02:43:50 PM UTC 25 | Feb 08 02:44:07 PM UTC 25 | 584792856 ps | ||
| T389 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1881595014 | Feb 08 02:43:58 PM UTC 25 | Feb 08 02:44:09 PM UTC 25 | 517861958 ps | ||
| T390 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.234664354 | Feb 08 02:44:01 PM UTC 25 | Feb 08 02:44:11 PM UTC 25 | 494283567 ps | ||
| T138 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2153083419 | Feb 08 02:42:17 PM UTC 25 | Feb 08 02:44:12 PM UTC 25 | 856801730 ps | ||
| T391 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.131060966 | Feb 08 02:44:07 PM UTC 25 | Feb 08 02:44:19 PM UTC 25 | 128035233 ps | ||
| T392 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2252120657 | Feb 08 02:44:14 PM UTC 25 | Feb 08 02:44:21 PM UTC 25 | 332735052 ps | ||
| T393 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2194113603 | Feb 08 02:43:48 PM UTC 25 | Feb 08 02:44:24 PM UTC 25 | 2164776619 ps | ||
| T394 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1815413878 | Feb 08 02:44:12 PM UTC 25 | Feb 08 02:44:24 PM UTC 25 | 2057313497 ps | ||
| T395 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3674207978 | Feb 08 02:44:21 PM UTC 25 | Feb 08 02:44:29 PM UTC 25 | 373417874 ps | ||
| T98 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.458904090 | Feb 08 02:44:05 PM UTC 25 | Feb 08 02:44:34 PM UTC 25 | 1499044809 ps | ||
| T396 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3879151690 | Feb 08 02:44:25 PM UTC 25 | Feb 08 02:44:35 PM UTC 25 | 127011403 ps | ||
| T95 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1887042228 | Feb 08 02:44:29 PM UTC 25 | Feb 08 02:44:38 PM UTC 25 | 438384309 ps | ||
| T132 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1782282485 | Feb 08 02:43:52 PM UTC 25 | Feb 08 02:44:43 PM UTC 25 | 1289234512 ps | ||
| T397 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3320305830 | Feb 08 02:44:36 PM UTC 25 | Feb 08 02:44:45 PM UTC 25 | 94447216 ps | ||
| T398 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1964131856 | Feb 08 02:44:35 PM UTC 25 | Feb 08 02:44:45 PM UTC 25 | 138154836 ps | ||
| T399 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3835663519 | Feb 08 02:44:46 PM UTC 25 | Feb 08 02:44:53 PM UTC 25 | 347203877 ps | ||
| T96 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2062187641 | Feb 08 02:44:22 PM UTC 25 | Feb 08 02:44:57 PM UTC 25 | 1113270398 ps | ||
| T400 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3014994949 | Feb 08 02:44:49 PM UTC 25 | Feb 08 02:44:58 PM UTC 25 | 517979188 ps | ||
| T401 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3024072017 | Feb 08 02:44:44 PM UTC 25 | Feb 08 02:44:58 PM UTC 25 | 2063990610 ps | ||
| T142 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.644499447 | Feb 08 02:43:37 PM UTC 25 | Feb 08 02:45:00 PM UTC 25 | 276687976 ps | ||
| T402 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2915212514 | Feb 08 02:44:54 PM UTC 25 | Feb 08 02:45:03 PM UTC 25 | 443853233 ps | ||
| T403 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2113434742 | Feb 08 02:45:02 PM UTC 25 | Feb 08 02:45:10 PM UTC 25 | 127555975 ps | ||
| T102 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2323177061 | Feb 08 02:44:39 PM UTC 25 | Feb 08 02:45:11 PM UTC 25 | 8790562683 ps | ||
| T404 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1468642560 | Feb 08 02:45:04 PM UTC 25 | Feb 08 02:45:12 PM UTC 25 | 291836849 ps | ||
| T405 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1129418520 | Feb 08 02:44:58 PM UTC 25 | Feb 08 02:45:15 PM UTC 25 | 140140888 ps | ||
| T406 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2898893148 | Feb 08 02:44:11 PM UTC 25 | Feb 08 02:45:17 PM UTC 25 | 293735759 ps | ||
| T134 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2327832327 | Feb 08 02:44:25 PM UTC 25 | Feb 08 02:45:20 PM UTC 25 | 681975278 ps | ||
| T407 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.537087976 | Feb 08 02:45:11 PM UTC 25 | Feb 08 02:45:20 PM UTC 25 | 1474855469 ps | ||
| T408 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4047517173 | Feb 08 02:45:13 PM UTC 25 | Feb 08 02:45:26 PM UTC 25 | 333567246 ps | ||
| T409 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3359691739 | Feb 08 02:45:18 PM UTC 25 | Feb 08 02:45:26 PM UTC 25 | 492489780 ps | ||
| T410 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.859567024 | Feb 08 02:44:58 PM UTC 25 | Feb 08 02:45:27 PM UTC 25 | 1437557246 ps | ||
| T411 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2460754746 | Feb 08 02:45:21 PM UTC 25 | Feb 08 02:45:32 PM UTC 25 | 494417560 ps | ||
| T412 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.434593441 | Feb 08 02:45:21 PM UTC 25 | Feb 08 02:45:34 PM UTC 25 | 137881828 ps | ||
| T103 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.506317168 | Feb 08 02:45:12 PM UTC 25 | Feb 08 02:45:37 PM UTC 25 | 917995818 ps | ||
| T104 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2204642663 | Feb 08 02:45:32 PM UTC 25 | Feb 08 02:45:39 PM UTC 25 | 86514226 ps | ||
| T413 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2629979893 | Feb 08 02:45:27 PM UTC 25 | Feb 08 02:45:42 PM UTC 25 | 131300124 ps | ||
| T414 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3909370478 | Feb 08 02:45:34 PM UTC 25 | Feb 08 02:45:45 PM UTC 25 | 131485007 ps | ||
| T415 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2653183321 | Feb 08 02:45:38 PM UTC 25 | Feb 08 02:45:48 PM UTC 25 | 516704189 ps | ||
| T135 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1525288958 | Feb 08 02:44:59 PM UTC 25 | Feb 08 02:45:49 PM UTC 25 | 592881549 ps | ||
| T139 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4055186526 | Feb 08 02:45:16 PM UTC 25 | Feb 08 02:45:57 PM UTC 25 | 1334963652 ps | ||
| T99 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3346591342 | Feb 08 02:45:49 PM UTC 25 | Feb 08 02:45:58 PM UTC 25 | 757792023 ps | ||
| T416 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3785601138 | Feb 08 02:45:44 PM UTC 25 | Feb 08 02:45:58 PM UTC 25 | 1956620220 ps | ||
| T417 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1242207360 | Feb 08 02:45:51 PM UTC 25 | Feb 08 02:46:00 PM UTC 25 | 126919218 ps | ||
| T418 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4243696734 | Feb 08 02:45:26 PM UTC 25 | Feb 08 02:46:08 PM UTC 25 | 594703384 ps | ||
| T419 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1544627286 | Feb 08 02:45:59 PM UTC 25 | Feb 08 02:46:10 PM UTC 25 | 528867803 ps | ||
| T420 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3833757222 | Feb 08 02:46:00 PM UTC 25 | Feb 08 02:46:12 PM UTC 25 | 1193623448 ps | ||
| T421 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2813706038 | Feb 08 02:45:40 PM UTC 25 | Feb 08 02:46:17 PM UTC 25 | 2559935149 ps | ||
| T422 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.618676605 | Feb 08 02:46:09 PM UTC 25 | Feb 08 02:46:18 PM UTC 25 | 250915860 ps | ||
| T423 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.666992082 | Feb 08 02:46:11 PM UTC 25 | Feb 08 02:46:25 PM UTC 25 | 516327975 ps | ||
| T424 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.863622778 | Feb 08 02:46:12 PM UTC 25 | Feb 08 02:46:27 PM UTC 25 | 152289122 ps | ||
| T425 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3767388301 | Feb 08 02:45:59 PM UTC 25 | Feb 08 02:46:34 PM UTC 25 | 1104897265 ps | ||
| T426 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4112337986 | Feb 08 02:44:45 PM UTC 25 | Feb 08 02:46:39 PM UTC 25 | 330550978 ps | ||
| T427 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.295874766 | Feb 08 02:45:46 PM UTC 25 | Feb 08 02:46:41 PM UTC 25 | 302951391 ps | ||
| T140 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3799989248 | Feb 08 02:45:27 PM UTC 25 | Feb 08 02:47:20 PM UTC 25 | 349993892 ps | ||
| T141 | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1798246458 | Feb 08 02:46:01 PM UTC 25 | Feb 08 02:47:42 PM UTC 25 | 301421188 ps |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.3311905353 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 261657211 ps |
| CPU time | 13.51 seconds |
| Started | Feb 08 02:04:29 PM UTC 25 |
| Finished | Feb 08 02:04:44 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311905353 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.3311905353 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1495020021 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10050429788 ps |
| CPU time | 127.39 seconds |
| Started | Feb 08 02:04:50 PM UTC 25 |
| Finished | Feb 08 02:07:00 PM UTC 25 |
| Peak memory | 244080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495020021 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.1495020021 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1385254275 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 96787275098 ps |
| CPU time | 1071.37 seconds |
| Started | Feb 08 02:05:16 PM UTC 25 |
| Finished | Feb 08 02:23:20 PM UTC 25 |
| Peak memory | 246180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1385254275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl _stress_all_with_rand_reset.1385254275 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3472943142 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 89262169 ps |
| CPU time | 6.29 seconds |
| Started | Feb 08 02:04:57 PM UTC 25 |
| Finished | Feb 08 02:05:05 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472943142 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3472943142 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3040035426 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 142336371 ps |
| CPU time | 8.49 seconds |
| Started | Feb 08 02:06:44 PM UTC 25 |
| Finished | Feb 08 02:06:54 PM UTC 25 |
| Peak memory | 221268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040035426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3040035426 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3802827253 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 20553639407 ps |
| CPU time | 210.22 seconds |
| Started | Feb 08 02:05:01 PM UTC 25 |
| Finished | Feb 08 02:08:34 PM UTC 25 |
| Peak memory | 256356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802827253 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.3802827253 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3501247363 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2108114049 ps |
| CPU time | 55.09 seconds |
| Started | Feb 08 02:40:16 PM UTC 25 |
| Finished | Feb 08 02:41:15 PM UTC 25 |
| Peak memory | 222836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501247363 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.3501247363 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.785116412 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3466332855 ps |
| CPU time | 30.97 seconds |
| Started | Feb 08 02:05:08 PM UTC 25 |
| Finished | Feb 08 02:05:40 PM UTC 25 |
| Peak memory | 227484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785116412 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.785116412 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.3315584974 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 952982853 ps |
| CPU time | 6.74 seconds |
| Started | Feb 08 02:05:12 PM UTC 25 |
| Finished | Feb 08 02:05:20 PM UTC 25 |
| Peak memory | 221204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315584974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3315584974 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.4029870248 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 297265088 ps |
| CPU time | 82.61 seconds |
| Started | Feb 08 02:04:43 PM UTC 25 |
| Finished | Feb 08 02:06:08 PM UTC 25 |
| Peak memory | 257356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029870248 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4029870248 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.3383595241 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 136917145 ps |
| CPU time | 10.02 seconds |
| Started | Feb 08 02:07:31 PM UTC 25 |
| Finished | Feb 08 02:07:42 PM UTC 25 |
| Peak memory | 221212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383595241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3383595241 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3600238302 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 926893251 ps |
| CPU time | 93.95 seconds |
| Started | Feb 08 02:41:59 PM UTC 25 |
| Finished | Feb 08 02:43:36 PM UTC 25 |
| Peak memory | 222912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600238302 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.3600238302 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3538910744 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 508385399 ps |
| CPU time | 9.09 seconds |
| Started | Feb 08 02:38:51 PM UTC 25 |
| Finished | Feb 08 02:39:03 PM UTC 25 |
| Peak memory | 221060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538910744 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.3538910744 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.858374471 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2390074825 ps |
| CPU time | 13.73 seconds |
| Started | Feb 08 02:04:38 PM UTC 25 |
| Finished | Feb 08 02:04:53 PM UTC 25 |
| Peak memory | 223328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858374471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.858374471 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.849222881 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 348414014 ps |
| CPU time | 11.02 seconds |
| Started | Feb 08 02:04:51 PM UTC 25 |
| Finished | Feb 08 02:05:03 PM UTC 25 |
| Peak memory | 223392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849222881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.849222881 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1782282485 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1289234512 ps |
| CPU time | 49.25 seconds |
| Started | Feb 08 02:43:52 PM UTC 25 |
| Finished | Feb 08 02:44:43 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782282485 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.1782282485 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1798246458 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 301421188 ps |
| CPU time | 96.97 seconds |
| Started | Feb 08 02:46:01 PM UTC 25 |
| Finished | Feb 08 02:47:42 PM UTC 25 |
| Peak memory | 223108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798246458 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.1798246458 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1630121588 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 544514547 ps |
| CPU time | 37.8 seconds |
| Started | Feb 08 02:42:32 PM UTC 25 |
| Finished | Feb 08 02:43:12 PM UTC 25 |
| Peak memory | 220876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630121588 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.1630121588 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.2942321007 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 153900638 ps |
| CPU time | 8.04 seconds |
| Started | Feb 08 02:07:09 PM UTC 25 |
| Finished | Feb 08 02:07:19 PM UTC 25 |
| Peak memory | 221140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942321007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2942321007 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2131565277 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2050947387 ps |
| CPU time | 19.25 seconds |
| Started | Feb 08 02:09:50 PM UTC 25 |
| Finished | Feb 08 02:10:11 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131565277 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.2131565277 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2153083419 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 856801730 ps |
| CPU time | 111.46 seconds |
| Started | Feb 08 02:42:17 PM UTC 25 |
| Finished | Feb 08 02:44:12 PM UTC 25 |
| Peak memory | 222836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153083419 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.2153083419 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.4023781243 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 136498769 ps |
| CPU time | 6.55 seconds |
| Started | Feb 08 02:04:27 PM UTC 25 |
| Finished | Feb 08 02:04:35 PM UTC 25 |
| Peak memory | 221292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023781243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4023781243 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2056937061 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 168001827 ps |
| CPU time | 6.92 seconds |
| Started | Feb 08 02:38:52 PM UTC 25 |
| Finished | Feb 08 02:39:02 PM UTC 25 |
| Peak memory | 221048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056937061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2056937061 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.1360276403 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3989897898 ps |
| CPU time | 20.28 seconds |
| Started | Feb 08 02:13:46 PM UTC 25 |
| Finished | Feb 08 02:14:09 PM UTC 25 |
| Peak memory | 225324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360276403 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.1360276403 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.3284561173 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 166053975 ps |
| CPU time | 10.35 seconds |
| Started | Feb 08 02:07:43 PM UTC 25 |
| Finished | Feb 08 02:07:55 PM UTC 25 |
| Peak memory | 221148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284561173 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.3284561173 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3399011519 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 492886442 ps |
| CPU time | 10.27 seconds |
| Started | Feb 08 02:39:02 PM UTC 25 |
| Finished | Feb 08 02:39:15 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399011519 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.3399011519 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1533466096 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 263351895 ps |
| CPU time | 7.2 seconds |
| Started | Feb 08 02:38:59 PM UTC 25 |
| Finished | Feb 08 02:39:09 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533466096 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.1533466096 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2220365458 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 110046189 ps |
| CPU time | 6.65 seconds |
| Started | Feb 08 02:39:10 PM UTC 25 |
| Finished | Feb 08 02:39:18 PM UTC 25 |
| Peak memory | 225220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2220365458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_wit h_rand_reset.2220365458 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2204689021 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 86687763 ps |
| CPU time | 5.65 seconds |
| Started | Feb 08 02:38:44 PM UTC 25 |
| Finished | Feb 08 02:38:52 PM UTC 25 |
| Peak memory | 220796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204689021 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.2204689021 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3940490560 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 334263086 ps |
| CPU time | 5.7 seconds |
| Started | Feb 08 02:38:42 PM UTC 25 |
| Finished | Feb 08 02:38:50 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940490560 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.3940490560 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.182671497 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1994952308 ps |
| CPU time | 30.23 seconds |
| Started | Feb 08 02:37:56 PM UTC 25 |
| Finished | Feb 08 02:38:29 PM UTC 25 |
| Peak memory | 220936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182671497 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.182671497 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2434586561 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 249723473 ps |
| CPU time | 6.62 seconds |
| Started | Feb 08 02:39:03 PM UTC 25 |
| Finished | Feb 08 02:39:12 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434586561 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.2434586561 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2983930885 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 127262274 ps |
| CPU time | 9.8 seconds |
| Started | Feb 08 02:38:30 PM UTC 25 |
| Finished | Feb 08 02:38:43 PM UTC 25 |
| Peak memory | 224972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983930885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2983930885 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.982430956 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2407271698 ps |
| CPU time | 92.45 seconds |
| Started | Feb 08 02:38:37 PM UTC 25 |
| Finished | Feb 08 02:40:13 PM UTC 25 |
| Peak memory | 223228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982430956 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.982430956 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3849868943 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 333074033 ps |
| CPU time | 5.71 seconds |
| Started | Feb 08 02:40:04 PM UTC 25 |
| Finished | Feb 08 02:40:11 PM UTC 25 |
| Peak memory | 220796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849868943 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.3849868943 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2076348216 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 440388596 ps |
| CPU time | 6.07 seconds |
| Started | Feb 08 02:40:03 PM UTC 25 |
| Finished | Feb 08 02:40:11 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076348216 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.2076348216 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2817794940 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1052453193 ps |
| CPU time | 11 seconds |
| Started | Feb 08 02:39:49 PM UTC 25 |
| Finished | Feb 08 02:40:02 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817794940 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.2817794940 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.175532098 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 829020203 ps |
| CPU time | 8.96 seconds |
| Started | Feb 08 02:40:12 PM UTC 25 |
| Finished | Feb 08 02:40:23 PM UTC 25 |
| Peak memory | 225044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 175532098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with _rand_reset.175532098 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.21049709 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 172095560 ps |
| CPU time | 5.72 seconds |
| Started | Feb 08 02:39:54 PM UTC 25 |
| Finished | Feb 08 02:40:03 PM UTC 25 |
| Peak memory | 220872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21049709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ba se_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_3 2kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.21049709 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2269183012 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 489985971 ps |
| CPU time | 5.64 seconds |
| Started | Feb 08 02:39:41 PM UTC 25 |
| Finished | Feb 08 02:39:48 PM UTC 25 |
| Peak memory | 221060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269183012 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.2269183012 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4062934428 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 145790084 ps |
| CPU time | 6.77 seconds |
| Started | Feb 08 02:39:31 PM UTC 25 |
| Finished | Feb 08 02:39:39 PM UTC 25 |
| Peak memory | 220788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062934428 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.4062934428 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1281795482 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 798189546 ps |
| CPU time | 37.29 seconds |
| Started | Feb 08 02:39:14 PM UTC 25 |
| Finished | Feb 08 02:39:53 PM UTC 25 |
| Peak memory | 221068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281795482 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.1281795482 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.358065233 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 415594544 ps |
| CPU time | 6.39 seconds |
| Started | Feb 08 02:40:11 PM UTC 25 |
| Finished | Feb 08 02:40:19 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358065233 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.358065233 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3075096449 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 149148477 ps |
| CPU time | 13.17 seconds |
| Started | Feb 08 02:39:16 PM UTC 25 |
| Finished | Feb 08 02:39:30 PM UTC 25 |
| Peak memory | 227156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075096449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3075096449 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2115107450 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 960455139 ps |
| CPU time | 53.09 seconds |
| Started | Feb 08 02:39:19 PM UTC 25 |
| Finished | Feb 08 02:40:14 PM UTC 25 |
| Peak memory | 220860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115107450 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.2115107450 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2294939574 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1054161699 ps |
| CPU time | 11.4 seconds |
| Started | Feb 08 02:43:47 PM UTC 25 |
| Finished | Feb 08 02:44:00 PM UTC 25 |
| Peak memory | 224968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2294939574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_wi th_rand_reset.2294939574 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.118294482 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 520796024 ps |
| CPU time | 8.21 seconds |
| Started | Feb 08 02:43:38 PM UTC 25 |
| Finished | Feb 08 02:43:48 PM UTC 25 |
| Peak memory | 221116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118294482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b ase_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_ 32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.118294482 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1516608924 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 380566414 ps |
| CPU time | 20.84 seconds |
| Started | Feb 08 02:43:35 PM UTC 25 |
| Finished | Feb 08 02:43:57 PM UTC 25 |
| Peak memory | 220952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516608924 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.1516608924 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.29390879 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 334849909 ps |
| CPU time | 6.82 seconds |
| Started | Feb 08 02:43:41 PM UTC 25 |
| Finished | Feb 08 02:43:49 PM UTC 25 |
| Peak memory | 220860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29390879 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.29390879 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3024168723 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 176309394 ps |
| CPU time | 8.82 seconds |
| Started | Feb 08 02:43:36 PM UTC 25 |
| Finished | Feb 08 02:43:46 PM UTC 25 |
| Peak memory | 225044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024168723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3024168723 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.644499447 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 276687976 ps |
| CPU time | 81.34 seconds |
| Started | Feb 08 02:43:37 PM UTC 25 |
| Finished | Feb 08 02:45:00 PM UTC 25 |
| Peak memory | 222912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644499447 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.644499447 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.234664354 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 494283567 ps |
| CPU time | 7.87 seconds |
| Started | Feb 08 02:44:01 PM UTC 25 |
| Finished | Feb 08 02:44:11 PM UTC 25 |
| Peak memory | 225108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 234664354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_wit h_rand_reset.234664354 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3215250853 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 88715407 ps |
| CPU time | 5.65 seconds |
| Started | Feb 08 02:43:57 PM UTC 25 |
| Finished | Feb 08 02:44:04 PM UTC 25 |
| Peak memory | 220856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215250853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3215250853 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2194113603 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2164776619 ps |
| CPU time | 33.88 seconds |
| Started | Feb 08 02:43:48 PM UTC 25 |
| Finished | Feb 08 02:44:24 PM UTC 25 |
| Peak memory | 221208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194113603 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.2194113603 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1881595014 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 517861958 ps |
| CPU time | 9.67 seconds |
| Started | Feb 08 02:43:58 PM UTC 25 |
| Finished | Feb 08 02:44:09 PM UTC 25 |
| Peak memory | 220796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881595014 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.1881595014 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2583065840 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 584792856 ps |
| CPU time | 15.09 seconds |
| Started | Feb 08 02:43:50 PM UTC 25 |
| Finished | Feb 08 02:44:07 PM UTC 25 |
| Peak memory | 227092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583065840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2583065840 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3674207978 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 373417874 ps |
| CPU time | 6.24 seconds |
| Started | Feb 08 02:44:21 PM UTC 25 |
| Finished | Feb 08 02:44:29 PM UTC 25 |
| Peak memory | 228296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3674207978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_wi th_rand_reset.3674207978 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1815413878 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 2057313497 ps |
| CPU time | 10.35 seconds |
| Started | Feb 08 02:44:12 PM UTC 25 |
| Finished | Feb 08 02:44:24 PM UTC 25 |
| Peak memory | 220784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815413878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1815413878 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.458904090 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1499044809 ps |
| CPU time | 26.1 seconds |
| Started | Feb 08 02:44:05 PM UTC 25 |
| Finished | Feb 08 02:44:34 PM UTC 25 |
| Peak memory | 221076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458904090 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.458904090 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2252120657 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 332735052 ps |
| CPU time | 5.72 seconds |
| Started | Feb 08 02:44:14 PM UTC 25 |
| Finished | Feb 08 02:44:21 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252120657 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.2252120657 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.131060966 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 128035233 ps |
| CPU time | 10.1 seconds |
| Started | Feb 08 02:44:07 PM UTC 25 |
| Finished | Feb 08 02:44:19 PM UTC 25 |
| Peak memory | 227020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131060966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base _test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32k B-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.131060966 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2898893148 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 293735759 ps |
| CPU time | 63.7 seconds |
| Started | Feb 08 02:44:11 PM UTC 25 |
| Finished | Feb 08 02:45:17 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898893148 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.2898893148 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3320305830 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 94447216 ps |
| CPU time | 5.99 seconds |
| Started | Feb 08 02:44:36 PM UTC 25 |
| Finished | Feb 08 02:44:45 PM UTC 25 |
| Peak memory | 222980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3320305830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_wi th_rand_reset.3320305830 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1887042228 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 438384309 ps |
| CPU time | 4.56 seconds |
| Started | Feb 08 02:44:29 PM UTC 25 |
| Finished | Feb 08 02:44:38 PM UTC 25 |
| Peak memory | 220792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887042228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1887042228 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2062187641 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1113270398 ps |
| CPU time | 33.33 seconds |
| Started | Feb 08 02:44:22 PM UTC 25 |
| Finished | Feb 08 02:44:57 PM UTC 25 |
| Peak memory | 220824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062187641 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.2062187641 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1964131856 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 138154836 ps |
| CPU time | 6.77 seconds |
| Started | Feb 08 02:44:35 PM UTC 25 |
| Finished | Feb 08 02:44:45 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964131856 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.1964131856 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3879151690 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 127011403 ps |
| CPU time | 7.04 seconds |
| Started | Feb 08 02:44:25 PM UTC 25 |
| Finished | Feb 08 02:44:35 PM UTC 25 |
| Peak memory | 225172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879151690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3879151690 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2327832327 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 681975278 ps |
| CPU time | 51.06 seconds |
| Started | Feb 08 02:44:25 PM UTC 25 |
| Finished | Feb 08 02:45:20 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327832327 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.2327832327 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2915212514 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 443853233 ps |
| CPU time | 6.88 seconds |
| Started | Feb 08 02:44:54 PM UTC 25 |
| Finished | Feb 08 02:45:03 PM UTC 25 |
| Peak memory | 227276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2915212514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_wi th_rand_reset.2915212514 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3835663519 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 347203877 ps |
| CPU time | 5.56 seconds |
| Started | Feb 08 02:44:46 PM UTC 25 |
| Finished | Feb 08 02:44:53 PM UTC 25 |
| Peak memory | 220784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835663519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3835663519 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2323177061 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 8790562683 ps |
| CPU time | 29.79 seconds |
| Started | Feb 08 02:44:39 PM UTC 25 |
| Finished | Feb 08 02:45:11 PM UTC 25 |
| Peak memory | 220944 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323177061 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.2323177061 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3014994949 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 517979188 ps |
| CPU time | 6.8 seconds |
| Started | Feb 08 02:44:49 PM UTC 25 |
| Finished | Feb 08 02:44:58 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014994949 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.3014994949 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3024072017 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2063990610 ps |
| CPU time | 12.11 seconds |
| Started | Feb 08 02:44:44 PM UTC 25 |
| Finished | Feb 08 02:44:58 PM UTC 25 |
| Peak memory | 228304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024072017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3024072017 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4112337986 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 330550978 ps |
| CPU time | 111.1 seconds |
| Started | Feb 08 02:44:45 PM UTC 25 |
| Finished | Feb 08 02:46:39 PM UTC 25 |
| Peak memory | 222844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112337986 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.4112337986 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.537087976 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1474855469 ps |
| CPU time | 7.32 seconds |
| Started | Feb 08 02:45:11 PM UTC 25 |
| Finished | Feb 08 02:45:20 PM UTC 25 |
| Peak memory | 222920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 537087976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_wit h_rand_reset.537087976 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2113434742 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 127555975 ps |
| CPU time | 6.56 seconds |
| Started | Feb 08 02:45:02 PM UTC 25 |
| Finished | Feb 08 02:45:10 PM UTC 25 |
| Peak memory | 220784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113434742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2113434742 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.859567024 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1437557246 ps |
| CPU time | 26.46 seconds |
| Started | Feb 08 02:44:58 PM UTC 25 |
| Finished | Feb 08 02:45:27 PM UTC 25 |
| Peak memory | 221140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859567024 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.859567024 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1468642560 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 291836849 ps |
| CPU time | 6.59 seconds |
| Started | Feb 08 02:45:04 PM UTC 25 |
| Finished | Feb 08 02:45:12 PM UTC 25 |
| Peak memory | 220796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468642560 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.1468642560 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1129418520 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 140140888 ps |
| CPU time | 14.98 seconds |
| Started | Feb 08 02:44:58 PM UTC 25 |
| Finished | Feb 08 02:45:15 PM UTC 25 |
| Peak memory | 228368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129418520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1129418520 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1525288958 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 592881549 ps |
| CPU time | 48.88 seconds |
| Started | Feb 08 02:44:59 PM UTC 25 |
| Finished | Feb 08 02:45:49 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525288958 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.1525288958 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2460754746 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 494417560 ps |
| CPU time | 8.07 seconds |
| Started | Feb 08 02:45:21 PM UTC 25 |
| Finished | Feb 08 02:45:32 PM UTC 25 |
| Peak memory | 225036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2460754746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_wi th_rand_reset.2460754746 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3359691739 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 492489780 ps |
| CPU time | 5.73 seconds |
| Started | Feb 08 02:45:18 PM UTC 25 |
| Finished | Feb 08 02:45:26 PM UTC 25 |
| Peak memory | 221048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359691739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3359691739 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.506317168 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 917995818 ps |
| CPU time | 23.42 seconds |
| Started | Feb 08 02:45:12 PM UTC 25 |
| Finished | Feb 08 02:45:37 PM UTC 25 |
| Peak memory | 221076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506317168 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.506317168 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.434593441 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 137881828 ps |
| CPU time | 10.07 seconds |
| Started | Feb 08 02:45:21 PM UTC 25 |
| Finished | Feb 08 02:45:34 PM UTC 25 |
| Peak memory | 220876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434593441 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.434593441 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4047517173 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 333567246 ps |
| CPU time | 10.88 seconds |
| Started | Feb 08 02:45:13 PM UTC 25 |
| Finished | Feb 08 02:45:26 PM UTC 25 |
| Peak memory | 227284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047517173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.4047517173 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4055186526 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1334963652 ps |
| CPU time | 39.65 seconds |
| Started | Feb 08 02:45:16 PM UTC 25 |
| Finished | Feb 08 02:45:57 PM UTC 25 |
| Peak memory | 222916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055186526 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.4055186526 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2653183321 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 516704189 ps |
| CPU time | 8.28 seconds |
| Started | Feb 08 02:45:38 PM UTC 25 |
| Finished | Feb 08 02:45:48 PM UTC 25 |
| Peak memory | 222916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2653183321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_wi th_rand_reset.2653183321 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2204642663 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 86514226 ps |
| CPU time | 5.48 seconds |
| Started | Feb 08 02:45:32 PM UTC 25 |
| Finished | Feb 08 02:45:39 PM UTC 25 |
| Peak memory | 220856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204642663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2204642663 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4243696734 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 594703384 ps |
| CPU time | 37.35 seconds |
| Started | Feb 08 02:45:26 PM UTC 25 |
| Finished | Feb 08 02:46:08 PM UTC 25 |
| Peak memory | 220816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243696734 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.4243696734 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3909370478 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 131485007 ps |
| CPU time | 8.66 seconds |
| Started | Feb 08 02:45:34 PM UTC 25 |
| Finished | Feb 08 02:45:45 PM UTC 25 |
| Peak memory | 220796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909370478 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.3909370478 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2629979893 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 131300124 ps |
| CPU time | 11.35 seconds |
| Started | Feb 08 02:45:27 PM UTC 25 |
| Finished | Feb 08 02:45:42 PM UTC 25 |
| Peak memory | 228420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629979893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2629979893 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3799989248 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 349993892 ps |
| CPU time | 108.19 seconds |
| Started | Feb 08 02:45:27 PM UTC 25 |
| Finished | Feb 08 02:47:20 PM UTC 25 |
| Peak memory | 222916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799989248 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.3799989248 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1544627286 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 528867803 ps |
| CPU time | 7.52 seconds |
| Started | Feb 08 02:45:59 PM UTC 25 |
| Finished | Feb 08 02:46:10 PM UTC 25 |
| Peak memory | 228360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1544627286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_wi th_rand_reset.1544627286 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3346591342 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 757792023 ps |
| CPU time | 7 seconds |
| Started | Feb 08 02:45:49 PM UTC 25 |
| Finished | Feb 08 02:45:58 PM UTC 25 |
| Peak memory | 220856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346591342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3346591342 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2813706038 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2559935149 ps |
| CPU time | 34.33 seconds |
| Started | Feb 08 02:45:40 PM UTC 25 |
| Finished | Feb 08 02:46:17 PM UTC 25 |
| Peak memory | 221016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813706038 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.2813706038 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1242207360 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 126919218 ps |
| CPU time | 6.63 seconds |
| Started | Feb 08 02:45:51 PM UTC 25 |
| Finished | Feb 08 02:46:00 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242207360 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.1242207360 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3785601138 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1956620220 ps |
| CPU time | 13.01 seconds |
| Started | Feb 08 02:45:44 PM UTC 25 |
| Finished | Feb 08 02:45:58 PM UTC 25 |
| Peak memory | 224972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785601138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3785601138 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.295874766 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 302951391 ps |
| CPU time | 53.26 seconds |
| Started | Feb 08 02:45:46 PM UTC 25 |
| Finished | Feb 08 02:46:41 PM UTC 25 |
| Peak memory | 222912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295874766 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.295874766 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.863622778 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 152289122 ps |
| CPU time | 10.75 seconds |
| Started | Feb 08 02:46:12 PM UTC 25 |
| Finished | Feb 08 02:46:27 PM UTC 25 |
| Peak memory | 228300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 863622778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_wit h_rand_reset.863622778 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.618676605 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 250915860 ps |
| CPU time | 6.75 seconds |
| Started | Feb 08 02:46:09 PM UTC 25 |
| Finished | Feb 08 02:46:18 PM UTC 25 |
| Peak memory | 220924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618676605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b ase_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_ 32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.618676605 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3767388301 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1104897265 ps |
| CPU time | 31.4 seconds |
| Started | Feb 08 02:45:59 PM UTC 25 |
| Finished | Feb 08 02:46:34 PM UTC 25 |
| Peak memory | 220888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767388301 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.3767388301 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.666992082 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 516327975 ps |
| CPU time | 10.64 seconds |
| Started | Feb 08 02:46:11 PM UTC 25 |
| Finished | Feb 08 02:46:25 PM UTC 25 |
| Peak memory | 220940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666992082 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.666992082 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3833757222 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1193623448 ps |
| CPU time | 8.52 seconds |
| Started | Feb 08 02:46:00 PM UTC 25 |
| Finished | Feb 08 02:46:12 PM UTC 25 |
| Peak memory | 228232 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833757222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3833757222 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.831907680 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 516492336 ps |
| CPU time | 6.36 seconds |
| Started | Feb 08 02:40:34 PM UTC 25 |
| Finished | Feb 08 02:40:42 PM UTC 25 |
| Peak memory | 220792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831907680 -assert nopostproc +UVM_TESTNAME=rom_ ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom _ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.831907680 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.754150649 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 175570035 ps |
| CPU time | 6.24 seconds |
| Started | Feb 08 02:40:33 PM UTC 25 |
| Finished | Feb 08 02:40:41 PM UTC 25 |
| Peak memory | 220796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754150649 -assert nopostproc +UVM_TESTNAME=rom_ ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom _ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.754150649 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2171958466 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 282165933 ps |
| CPU time | 10.82 seconds |
| Started | Feb 08 02:40:28 PM UTC 25 |
| Finished | Feb 08 02:40:41 PM UTC 25 |
| Peak memory | 220796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171958466 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.2171958466 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2519295223 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 508539133 ps |
| CPU time | 8.99 seconds |
| Started | Feb 08 02:40:42 PM UTC 25 |
| Finished | Feb 08 02:40:53 PM UTC 25 |
| Peak memory | 225028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2519295223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_wit h_rand_reset.2519295223 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1917821515 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1045175343 ps |
| CPU time | 6.72 seconds |
| Started | Feb 08 02:40:30 PM UTC 25 |
| Finished | Feb 08 02:40:39 PM UTC 25 |
| Peak memory | 220920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917821515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1917821515 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1250748904 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 256587425 ps |
| CPU time | 6.57 seconds |
| Started | Feb 08 02:40:24 PM UTC 25 |
| Finished | Feb 08 02:40:32 PM UTC 25 |
| Peak memory | 220996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250748904 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.1250748904 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3845285355 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 598259654 ps |
| CPU time | 6.37 seconds |
| Started | Feb 08 02:40:20 PM UTC 25 |
| Finished | Feb 08 02:40:29 PM UTC 25 |
| Peak memory | 221060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845285355 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.3845285355 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.67644686 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2170549569 ps |
| CPU time | 25.46 seconds |
| Started | Feb 08 02:40:13 PM UTC 25 |
| Finished | Feb 08 02:40:41 PM UTC 25 |
| Peak memory | 221192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67644686 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.67644686 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2452610337 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 334039760 ps |
| CPU time | 6.14 seconds |
| Started | Feb 08 02:40:40 PM UTC 25 |
| Finished | Feb 08 02:40:48 PM UTC 25 |
| Peak memory | 221124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452610337 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.2452610337 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1319755182 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 499781691 ps |
| CPU time | 10.29 seconds |
| Started | Feb 08 02:40:14 PM UTC 25 |
| Finished | Feb 08 02:40:26 PM UTC 25 |
| Peak memory | 227284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319755182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1319755182 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2772635186 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 251245618 ps |
| CPU time | 6.69 seconds |
| Started | Feb 08 02:41:06 PM UTC 25 |
| Finished | Feb 08 02:41:15 PM UTC 25 |
| Peak memory | 220932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772635186 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.2772635186 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3465350418 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 256219638 ps |
| CPU time | 7.05 seconds |
| Started | Feb 08 02:41:01 PM UTC 25 |
| Finished | Feb 08 02:41:10 PM UTC 25 |
| Peak memory | 220796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465350418 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.3465350418 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.313117685 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 341217167 ps |
| CPU time | 8.3 seconds |
| Started | Feb 08 02:40:55 PM UTC 25 |
| Finished | Feb 08 02:41:05 PM UTC 25 |
| Peak memory | 220864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313117685 -assert nopostproc +UVM_TESTNAME=rom_ ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom _ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.313117685 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1371521879 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 265866968 ps |
| CPU time | 6.06 seconds |
| Started | Feb 08 02:41:11 PM UTC 25 |
| Finished | Feb 08 02:41:19 PM UTC 25 |
| Peak memory | 225092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1371521879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_wit h_rand_reset.1371521879 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1465631305 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 351578311 ps |
| CPU time | 5.6 seconds |
| Started | Feb 08 02:40:58 PM UTC 25 |
| Finished | Feb 08 02:41:05 PM UTC 25 |
| Peak memory | 221052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465631305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1465631305 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3379090864 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 85822209 ps |
| CPU time | 4.64 seconds |
| Started | Feb 08 02:40:54 PM UTC 25 |
| Finished | Feb 08 02:41:00 PM UTC 25 |
| Peak memory | 221060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379090864 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.3379090864 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3123306246 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 129181640 ps |
| CPU time | 6.61 seconds |
| Started | Feb 08 02:40:49 PM UTC 25 |
| Finished | Feb 08 02:40:57 PM UTC 25 |
| Peak memory | 220932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123306246 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.3123306246 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4181210234 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3071102811 ps |
| CPU time | 59.44 seconds |
| Started | Feb 08 02:40:42 PM UTC 25 |
| Finished | Feb 08 02:41:45 PM UTC 25 |
| Peak memory | 220984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181210234 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.4181210234 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1120223460 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 508076471 ps |
| CPU time | 12.87 seconds |
| Started | Feb 08 02:41:06 PM UTC 25 |
| Finished | Feb 08 02:41:21 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120223460 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.1120223460 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4174084442 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 133336992 ps |
| CPU time | 9.66 seconds |
| Started | Feb 08 02:40:42 PM UTC 25 |
| Finished | Feb 08 02:40:54 PM UTC 25 |
| Peak memory | 228208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174084442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4174084442 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2358098773 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 507562135 ps |
| CPU time | 108.84 seconds |
| Started | Feb 08 02:40:43 PM UTC 25 |
| Finished | Feb 08 02:42:35 PM UTC 25 |
| Peak memory | 223104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358098773 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.2358098773 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1574995346 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 479156200 ps |
| CPU time | 6.53 seconds |
| Started | Feb 08 02:41:47 PM UTC 25 |
| Finished | Feb 08 02:41:55 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574995346 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.1574995346 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3479515043 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 415566672 ps |
| CPU time | 5.91 seconds |
| Started | Feb 08 02:41:45 PM UTC 25 |
| Finished | Feb 08 02:41:52 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479515043 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.3479515043 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.266916247 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 507757080 ps |
| CPU time | 10.91 seconds |
| Started | Feb 08 02:41:34 PM UTC 25 |
| Finished | Feb 08 02:41:46 PM UTC 25 |
| Peak memory | 220992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266916247 -assert nopostproc +UVM_TESTNAME=rom_ ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom _ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.266916247 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.319896213 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 145798440 ps |
| CPU time | 7.41 seconds |
| Started | Feb 08 02:41:53 PM UTC 25 |
| Finished | Feb 08 02:42:02 PM UTC 25 |
| Peak memory | 228392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 319896213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with _rand_reset.319896213 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.993983286 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 449557906 ps |
| CPU time | 6.58 seconds |
| Started | Feb 08 02:41:40 PM UTC 25 |
| Finished | Feb 08 02:41:48 PM UTC 25 |
| Peak memory | 220792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993983286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b ase_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_ 32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.993983286 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1340870170 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 335877472 ps |
| CPU time | 6.89 seconds |
| Started | Feb 08 02:41:31 PM UTC 25 |
| Finished | Feb 08 02:41:39 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340870170 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.1340870170 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1355272947 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 86626235 ps |
| CPU time | 5.64 seconds |
| Started | Feb 08 02:41:23 PM UTC 25 |
| Finished | Feb 08 02:41:30 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355272947 -assert nopostproc +UVM_TESTNAME=rom _ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ro m_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.1355272947 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3690649411 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1569259581 ps |
| CPU time | 34.16 seconds |
| Started | Feb 08 02:41:15 PM UTC 25 |
| Finished | Feb 08 02:41:53 PM UTC 25 |
| Peak memory | 220804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690649411 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.3690649411 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1159756536 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 498225883 ps |
| CPU time | 8.15 seconds |
| Started | Feb 08 02:41:49 PM UTC 25 |
| Finished | Feb 08 02:41:59 PM UTC 25 |
| Peak memory | 220932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159756536 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.1159756536 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3199809883 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 498303729 ps |
| CPU time | 13.71 seconds |
| Started | Feb 08 02:41:17 PM UTC 25 |
| Finished | Feb 08 02:41:33 PM UTC 25 |
| Peak memory | 227020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199809883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3199809883 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.441670377 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 262812291 ps |
| CPU time | 54.7 seconds |
| Started | Feb 08 02:41:21 PM UTC 25 |
| Finished | Feb 08 02:42:18 PM UTC 25 |
| Peak memory | 222908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441670377 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.441670377 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2875698111 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 670142037 ps |
| CPU time | 9.29 seconds |
| Started | Feb 08 02:42:10 PM UTC 25 |
| Finished | Feb 08 02:42:22 PM UTC 25 |
| Peak memory | 227004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2875698111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_wit h_rand_reset.2875698111 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.712011272 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 89040364 ps |
| CPU time | 5.63 seconds |
| Started | Feb 08 02:42:02 PM UTC 25 |
| Finished | Feb 08 02:42:10 PM UTC 25 |
| Peak memory | 220792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712011272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b ase_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_ 32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.712011272 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3960721835 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2276896003 ps |
| CPU time | 38.56 seconds |
| Started | Feb 08 02:41:54 PM UTC 25 |
| Finished | Feb 08 02:42:35 PM UTC 25 |
| Peak memory | 221004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960721835 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.3960721835 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1064834189 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 499657865 ps |
| CPU time | 6.63 seconds |
| Started | Feb 08 02:42:05 PM UTC 25 |
| Finished | Feb 08 02:42:14 PM UTC 25 |
| Peak memory | 220872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064834189 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.1064834189 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.727960653 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 662559932 ps |
| CPU time | 13.12 seconds |
| Started | Feb 08 02:41:56 PM UTC 25 |
| Finished | Feb 08 02:42:11 PM UTC 25 |
| Peak memory | 228300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727960653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base _test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32k B-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.727960653 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1404786883 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 144529565 ps |
| CPU time | 8.95 seconds |
| Started | Feb 08 02:42:28 PM UTC 25 |
| Finished | Feb 08 02:42:40 PM UTC 25 |
| Peak memory | 228312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1404786883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_wit h_rand_reset.1404786883 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3656842061 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 171731941 ps |
| CPU time | 5.68 seconds |
| Started | Feb 08 02:42:19 PM UTC 25 |
| Finished | Feb 08 02:42:27 PM UTC 25 |
| Peak memory | 220856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656842061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3656842061 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2043108391 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2230162287 ps |
| CPU time | 36.29 seconds |
| Started | Feb 08 02:42:11 PM UTC 25 |
| Finished | Feb 08 02:42:50 PM UTC 25 |
| Peak memory | 221068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043108391 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.2043108391 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1033110412 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 594565493 ps |
| CPU time | 6.64 seconds |
| Started | Feb 08 02:42:23 PM UTC 25 |
| Finished | Feb 08 02:42:32 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033110412 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.1033110412 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3615505647 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 133116549 ps |
| CPU time | 12.29 seconds |
| Started | Feb 08 02:42:14 PM UTC 25 |
| Finished | Feb 08 02:42:31 PM UTC 25 |
| Peak memory | 225108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615505647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3615505647 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1418533119 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 131660527 ps |
| CPU time | 6.81 seconds |
| Started | Feb 08 02:42:44 PM UTC 25 |
| Finished | Feb 08 02:42:52 PM UTC 25 |
| Peak memory | 222980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1418533119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_wit h_rand_reset.1418533119 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2779345118 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 126911277 ps |
| CPU time | 5.41 seconds |
| Started | Feb 08 02:42:36 PM UTC 25 |
| Finished | Feb 08 02:42:43 PM UTC 25 |
| Peak memory | 220792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779345118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2779345118 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3960767704 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 174674305 ps |
| CPU time | 4.47 seconds |
| Started | Feb 08 02:42:41 PM UTC 25 |
| Finished | Feb 08 02:42:47 PM UTC 25 |
| Peak memory | 221060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960767704 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.3960767704 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2116082976 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 126442043 ps |
| CPU time | 9.38 seconds |
| Started | Feb 08 02:42:33 PM UTC 25 |
| Finished | Feb 08 02:42:44 PM UTC 25 |
| Peak memory | 227024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116082976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2116082976 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3795427643 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 277554286 ps |
| CPU time | 56.24 seconds |
| Started | Feb 08 02:42:36 PM UTC 25 |
| Finished | Feb 08 02:43:35 PM UTC 25 |
| Peak memory | 223100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795427643 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.3795427643 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2374727217 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 716374457 ps |
| CPU time | 7.97 seconds |
| Started | Feb 08 02:43:03 PM UTC 25 |
| Finished | Feb 08 02:43:14 PM UTC 25 |
| Peak memory | 227076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2374727217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_wit h_rand_reset.2374727217 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3342148022 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 279428421 ps |
| CPU time | 6.65 seconds |
| Started | Feb 08 02:42:53 PM UTC 25 |
| Finished | Feb 08 02:43:02 PM UTC 25 |
| Peak memory | 221048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342148022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3342148022 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1202911825 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 566204317 ps |
| CPU time | 28.68 seconds |
| Started | Feb 08 02:42:45 PM UTC 25 |
| Finished | Feb 08 02:43:16 PM UTC 25 |
| Peak memory | 220804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202911825 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.1202911825 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3207197923 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 501051361 ps |
| CPU time | 6.68 seconds |
| Started | Feb 08 02:43:02 PM UTC 25 |
| Finished | Feb 08 02:43:12 PM UTC 25 |
| Peak memory | 220932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207197923 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.3207197923 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3839671501 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 287777627 ps |
| CPU time | 11.85 seconds |
| Started | Feb 08 02:42:48 PM UTC 25 |
| Finished | Feb 08 02:43:02 PM UTC 25 |
| Peak memory | 227020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839671501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_bas e_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32 kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3839671501 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.223849576 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 208290609 ps |
| CPU time | 58.21 seconds |
| Started | Feb 08 02:42:51 PM UTC 25 |
| Finished | Feb 08 02:43:52 PM UTC 25 |
| Peak memory | 220860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223849576 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.223849576 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.271598032 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 294830797 ps |
| CPU time | 7.18 seconds |
| Started | Feb 08 02:43:28 PM UTC 25 |
| Finished | Feb 08 02:43:37 PM UTC 25 |
| Peak memory | 228300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 271598032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with _rand_reset.271598032 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2282224206 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 251890229 ps |
| CPU time | 6.63 seconds |
| Started | Feb 08 02:43:17 PM UTC 25 |
| Finished | Feb 08 02:43:25 PM UTC 25 |
| Peak memory | 220856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282224206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2282224206 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1477223417 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 7393170479 ps |
| CPU time | 25.52 seconds |
| Started | Feb 08 02:43:12 PM UTC 25 |
| Finished | Feb 08 02:43:40 PM UTC 25 |
| Peak memory | 221004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477223417 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.1477223417 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1424787414 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 348826643 ps |
| CPU time | 5.74 seconds |
| Started | Feb 08 02:43:27 PM UTC 25 |
| Finished | Feb 08 02:43:34 PM UTC 25 |
| Peak memory | 220868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424787414 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.1424787414 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.976305681 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 499842826 ps |
| CPU time | 12.51 seconds |
| Started | Feb 08 02:43:12 PM UTC 25 |
| Finished | Feb 08 02:43:27 PM UTC 25 |
| Peak memory | 227152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976305681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base _test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32k B-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.976305681 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.130522374 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 384032916 ps |
| CPU time | 39.81 seconds |
| Started | Feb 08 02:43:14 PM UTC 25 |
| Finished | Feb 08 02:43:56 PM UTC 25 |
| Peak memory | 220788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130522374 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.130522374 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.407497226 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 349897141 ps |
| CPU time | 5.55 seconds |
| Started | Feb 08 02:04:44 PM UTC 25 |
| Finished | Feb 08 02:04:51 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407497226 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.407497226 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2380134053 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3193067484 ps |
| CPU time | 151.13 seconds |
| Started | Feb 08 02:04:37 PM UTC 25 |
| Finished | Feb 08 02:07:11 PM UTC 25 |
| Peak memory | 223680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380134053 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.2380134053 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.3311132336 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 97337838 ps |
| CPU time | 6.48 seconds |
| Started | Feb 08 02:04:35 PM UTC 25 |
| Finished | Feb 08 02:04:43 PM UTC 25 |
| Peak memory | 221204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311132336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3311132336 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.1875605557 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 193504057 ps |
| CPU time | 8.83 seconds |
| Started | Feb 08 02:04:50 PM UTC 25 |
| Finished | Feb 08 02:05:00 PM UTC 25 |
| Peak memory | 221132 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875605557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1875605557 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1866211115 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 260928269 ps |
| CPU time | 77.26 seconds |
| Started | Feb 08 02:04:56 PM UTC 25 |
| Finished | Feb 08 02:06:16 PM UTC 25 |
| Peak memory | 257364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866211115 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1866211115 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.467037163 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 144112493 ps |
| CPU time | 9.04 seconds |
| Started | Feb 08 02:04:45 PM UTC 25 |
| Finished | Feb 08 02:04:55 PM UTC 25 |
| Peak memory | 221228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467037163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.467037163 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1160528851 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 557064899 ps |
| CPU time | 10.18 seconds |
| Started | Feb 08 02:04:46 PM UTC 25 |
| Finished | Feb 08 02:04:58 PM UTC 25 |
| Peak memory | 221152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160528851 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.1160528851 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.3013163126 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1827940625 ps |
| CPU time | 10.33 seconds |
| Started | Feb 08 02:07:17 PM UTC 25 |
| Finished | Feb 08 02:07:28 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013163126 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3013163126 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.495618460 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1212045412 ps |
| CPU time | 105.3 seconds |
| Started | Feb 08 02:07:11 PM UTC 25 |
| Finished | Feb 08 02:08:59 PM UTC 25 |
| Peak memory | 258372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495618460 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.495618460 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.917334171 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1857224169 ps |
| CPU time | 11.47 seconds |
| Started | Feb 08 02:07:11 PM UTC 25 |
| Finished | Feb 08 02:07:24 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917334171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.917334171 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.652128858 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 391639588 ps |
| CPU time | 11.54 seconds |
| Started | Feb 08 02:07:07 PM UTC 25 |
| Finished | Feb 08 02:07:20 PM UTC 25 |
| Peak memory | 223328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652128858 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.652128858 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.741744297 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 395641609 ps |
| CPU time | 5.33 seconds |
| Started | Feb 08 02:07:29 PM UTC 25 |
| Finished | Feb 08 02:07:36 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741744297 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.741744297 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3568840746 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1072971938 ps |
| CPU time | 73.11 seconds |
| Started | Feb 08 02:07:21 PM UTC 25 |
| Finished | Feb 08 02:08:36 PM UTC 25 |
| Peak memory | 243988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568840746 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.3568840746 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.122511772 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1658238587 ps |
| CPU time | 17.22 seconds |
| Started | Feb 08 02:07:24 PM UTC 25 |
| Finished | Feb 08 02:07:42 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122511772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.122511772 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.3296945420 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 138197832 ps |
| CPU time | 9.95 seconds |
| Started | Feb 08 02:07:20 PM UTC 25 |
| Finished | Feb 08 02:07:31 PM UTC 25 |
| Peak memory | 221148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296945420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3296945420 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.4077050138 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 129731135 ps |
| CPU time | 9.45 seconds |
| Started | Feb 08 02:07:20 PM UTC 25 |
| Finished | Feb 08 02:07:30 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077050138 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.4077050138 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3385284255 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2239955937 ps |
| CPU time | 11.62 seconds |
| Started | Feb 08 02:07:43 PM UTC 25 |
| Finished | Feb 08 02:07:56 PM UTC 25 |
| Peak memory | 221204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385284255 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3385284255 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1885521435 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1301567848 ps |
| CPU time | 72.12 seconds |
| Started | Feb 08 02:07:32 PM UTC 25 |
| Finished | Feb 08 02:08:46 PM UTC 25 |
| Peak memory | 244292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885521435 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.1885521435 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.2892180590 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 170299523 ps |
| CPU time | 13.87 seconds |
| Started | Feb 08 02:07:34 PM UTC 25 |
| Finished | Feb 08 02:07:49 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892180590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2892180590 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.604961449 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 5880381717 ps |
| CPU time | 22.75 seconds |
| Started | Feb 08 02:07:29 PM UTC 25 |
| Finished | Feb 08 02:07:53 PM UTC 25 |
| Peak memory | 225376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604961449 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.604961449 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.4165035760 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 128990022 ps |
| CPU time | 6.79 seconds |
| Started | Feb 08 02:08:02 PM UTC 25 |
| Finished | Feb 08 02:08:10 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165035760 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.4165035760 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2786251867 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 3222488773 ps |
| CPU time | 167.06 seconds |
| Started | Feb 08 02:07:54 PM UTC 25 |
| Finished | Feb 08 02:10:44 PM UTC 25 |
| Peak memory | 257388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786251867 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.2786251867 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.1528739621 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1081662309 ps |
| CPU time | 14.78 seconds |
| Started | Feb 08 02:07:55 PM UTC 25 |
| Finished | Feb 08 02:08:12 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528739621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1528739621 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.1866613297 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 198321689 ps |
| CPU time | 9.28 seconds |
| Started | Feb 08 02:07:50 PM UTC 25 |
| Finished | Feb 08 02:08:01 PM UTC 25 |
| Peak memory | 221276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866613297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1866613297 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1489326140 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 500990753 ps |
| CPU time | 8.08 seconds |
| Started | Feb 08 02:08:35 PM UTC 25 |
| Finished | Feb 08 02:08:44 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489326140 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1489326140 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3044441682 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2463085147 ps |
| CPU time | 168.51 seconds |
| Started | Feb 08 02:08:13 PM UTC 25 |
| Finished | Feb 08 02:11:04 PM UTC 25 |
| Peak memory | 257316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044441682 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.3044441682 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.1335869562 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 715190483 ps |
| CPU time | 15.76 seconds |
| Started | Feb 08 02:08:21 PM UTC 25 |
| Finished | Feb 08 02:08:38 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335869562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1335869562 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.4044293884 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 353366511 ps |
| CPU time | 8.12 seconds |
| Started | Feb 08 02:08:11 PM UTC 25 |
| Finished | Feb 08 02:08:20 PM UTC 25 |
| Peak memory | 221276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044293884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4044293884 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.449034009 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 225757422 ps |
| CPU time | 20.2 seconds |
| Started | Feb 08 02:08:11 PM UTC 25 |
| Finished | Feb 08 02:08:32 PM UTC 25 |
| Peak memory | 225440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449034009 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.449034009 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1838442379 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 179864112126 ps |
| CPU time | 1989.3 seconds |
| Started | Feb 08 02:08:33 PM UTC 25 |
| Finished | Feb 08 02:42:05 PM UTC 25 |
| Peak memory | 248164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1838442379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctr l_stress_all_with_rand_reset.1838442379 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.554483162 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 128882369 ps |
| CPU time | 5.55 seconds |
| Started | Feb 08 02:08:53 PM UTC 25 |
| Finished | Feb 08 02:09:00 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554483162 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.554483162 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4047608199 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 3917772119 ps |
| CPU time | 157.97 seconds |
| Started | Feb 08 02:08:45 PM UTC 25 |
| Finished | Feb 08 02:11:26 PM UTC 25 |
| Peak memory | 223584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047608199 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.4047608199 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.1371641706 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 994461402 ps |
| CPU time | 14.73 seconds |
| Started | Feb 08 02:08:47 PM UTC 25 |
| Finished | Feb 08 02:09:03 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371641706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1371641706 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.102722039 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 105000976 ps |
| CPU time | 8.79 seconds |
| Started | Feb 08 02:08:39 PM UTC 25 |
| Finished | Feb 08 02:08:49 PM UTC 25 |
| Peak memory | 221268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102722039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.102722039 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.736111783 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 219959590 ps |
| CPU time | 17.22 seconds |
| Started | Feb 08 02:08:37 PM UTC 25 |
| Finished | Feb 08 02:08:55 PM UTC 25 |
| Peak memory | 223264 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736111783 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.736111783 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.2496275326 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 348118479 ps |
| CPU time | 5.92 seconds |
| Started | Feb 08 02:09:09 PM UTC 25 |
| Finished | Feb 08 02:09:16 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496275326 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2496275326 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3872912469 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 3831621946 ps |
| CPU time | 74.95 seconds |
| Started | Feb 08 02:08:59 PM UTC 25 |
| Finished | Feb 08 02:10:16 PM UTC 25 |
| Peak memory | 223584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872912469 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.3872912469 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.3610873004 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 726390972 ps |
| CPU time | 11.07 seconds |
| Started | Feb 08 02:09:01 PM UTC 25 |
| Finished | Feb 08 02:09:13 PM UTC 25 |
| Peak memory | 223340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610873004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3610873004 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.796962820 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 537349424 ps |
| CPU time | 7.11 seconds |
| Started | Feb 08 02:08:59 PM UTC 25 |
| Finished | Feb 08 02:09:08 PM UTC 25 |
| Peak memory | 221204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796962820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.796962820 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1339183457 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2255518080 ps |
| CPU time | 29.88 seconds |
| Started | Feb 08 02:08:56 PM UTC 25 |
| Finished | Feb 08 02:09:28 PM UTC 25 |
| Peak memory | 225380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339183457 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.1339183457 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.4033127456 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 297760132 ps |
| CPU time | 5.75 seconds |
| Started | Feb 08 02:09:27 PM UTC 25 |
| Finished | Feb 08 02:09:34 PM UTC 25 |
| Peak memory | 221284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033127456 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4033127456 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2001255935 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 4161852494 ps |
| CPU time | 137.39 seconds |
| Started | Feb 08 02:09:14 PM UTC 25 |
| Finished | Feb 08 02:11:34 PM UTC 25 |
| Peak memory | 257332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001255935 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.2001255935 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1532938037 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 171787475 ps |
| CPU time | 13.41 seconds |
| Started | Feb 08 02:09:17 PM UTC 25 |
| Finished | Feb 08 02:09:32 PM UTC 25 |
| Peak memory | 221228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532938037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1532938037 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.3920074720 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 378065393 ps |
| CPU time | 5.74 seconds |
| Started | Feb 08 02:09:13 PM UTC 25 |
| Finished | Feb 08 02:09:20 PM UTC 25 |
| Peak memory | 221212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920074720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3920074720 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.660817116 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1761955166 ps |
| CPU time | 28.67 seconds |
| Started | Feb 08 02:09:10 PM UTC 25 |
| Finished | Feb 08 02:09:40 PM UTC 25 |
| Peak memory | 227360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660817116 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.660817116 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.384195868 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 29520589801 ps |
| CPU time | 1277.44 seconds |
| Started | Feb 08 02:09:21 PM UTC 25 |
| Finished | Feb 08 02:30:53 PM UTC 25 |
| Peak memory | 246120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=384195868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl _stress_all_with_rand_reset.384195868 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.1304602230 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 735184394 ps |
| CPU time | 6.95 seconds |
| Started | Feb 08 02:09:43 PM UTC 25 |
| Finished | Feb 08 02:09:52 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304602230 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1304602230 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3271166622 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1999637708 ps |
| CPU time | 128.96 seconds |
| Started | Feb 08 02:09:35 PM UTC 25 |
| Finished | Feb 08 02:11:47 PM UTC 25 |
| Peak memory | 244884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271166622 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.3271166622 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2576511524 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 174380408 ps |
| CPU time | 13.05 seconds |
| Started | Feb 08 02:09:36 PM UTC 25 |
| Finished | Feb 08 02:09:51 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576511524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2576511524 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.3135055482 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 476539786 ps |
| CPU time | 9.37 seconds |
| Started | Feb 08 02:09:32 PM UTC 25 |
| Finished | Feb 08 02:09:43 PM UTC 25 |
| Peak memory | 221276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135055482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3135055482 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.1488772693 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2663153393 ps |
| CPU time | 19.52 seconds |
| Started | Feb 08 02:09:28 PM UTC 25 |
| Finished | Feb 08 02:09:49 PM UTC 25 |
| Peak memory | 225380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488772693 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.1488772693 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2629457101 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 529037456152 ps |
| CPU time | 2841.75 seconds |
| Started | Feb 08 02:09:40 PM UTC 25 |
| Finished | Feb 08 02:57:33 PM UTC 25 |
| Peak memory | 248228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2629457101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctr l_stress_all_with_rand_reset.2629457101 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.2238231481 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 89257650 ps |
| CPU time | 5.76 seconds |
| Started | Feb 08 02:10:11 PM UTC 25 |
| Finished | Feb 08 02:10:18 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238231481 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2238231481 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.392373105 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 4930490925 ps |
| CPU time | 106.76 seconds |
| Started | Feb 08 02:09:52 PM UTC 25 |
| Finished | Feb 08 02:11:42 PM UTC 25 |
| Peak memory | 257448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392373105 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.392373105 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.604403180 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 172804528 ps |
| CPU time | 13.07 seconds |
| Started | Feb 08 02:09:56 PM UTC 25 |
| Finished | Feb 08 02:10:10 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604403180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.604403180 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.3565606899 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 346618129 ps |
| CPU time | 6.44 seconds |
| Started | Feb 08 02:09:51 PM UTC 25 |
| Finished | Feb 08 02:09:59 PM UTC 25 |
| Peak memory | 221212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565606899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3565606899 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.4195571657 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 73755368267 ps |
| CPU time | 3442.3 seconds |
| Started | Feb 08 02:10:00 PM UTC 25 |
| Finished | Feb 08 03:07:59 PM UTC 25 |
| Peak memory | 264720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4195571657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctr l_stress_all_with_rand_reset.4195571657 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.606521914 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 498718520 ps |
| CPU time | 7.57 seconds |
| Started | Feb 08 02:05:05 PM UTC 25 |
| Finished | Feb 08 02:05:14 PM UTC 25 |
| Peak memory | 221168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606521914 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.606521914 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.4175482535 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 360966331 ps |
| CPU time | 10.13 seconds |
| Started | Feb 08 02:05:02 PM UTC 25 |
| Finished | Feb 08 02:05:13 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175482535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4175482535 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1876912228 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 191742751 ps |
| CPU time | 9.02 seconds |
| Started | Feb 08 02:05:01 PM UTC 25 |
| Finished | Feb 08 02:05:11 PM UTC 25 |
| Peak memory | 221332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876912228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1876912228 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.17958393 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 270038064 ps |
| CPU time | 55.34 seconds |
| Started | Feb 08 02:05:04 PM UTC 25 |
| Finished | Feb 08 02:06:01 PM UTC 25 |
| Peak memory | 257424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17958393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b ase_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_ 32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.17958393 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1239680806 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 271796444 ps |
| CPU time | 7.95 seconds |
| Started | Feb 08 02:04:57 PM UTC 25 |
| Finished | Feb 08 02:05:07 PM UTC 25 |
| Peak memory | 221228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239680806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1239680806 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3501170459 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 787908713 ps |
| CPU time | 15.17 seconds |
| Started | Feb 08 02:04:58 PM UTC 25 |
| Finished | Feb 08 02:05:15 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501170459 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.3501170459 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.1625763666 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 130324497 ps |
| CPU time | 6.68 seconds |
| Started | Feb 08 02:10:45 PM UTC 25 |
| Finished | Feb 08 02:10:53 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625763666 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1625763666 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3455487560 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1902519622 ps |
| CPU time | 157.41 seconds |
| Started | Feb 08 02:10:19 PM UTC 25 |
| Finished | Feb 08 02:12:59 PM UTC 25 |
| Peak memory | 245012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455487560 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.3455487560 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.2667069649 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 2075777009 ps |
| CPU time | 18.02 seconds |
| Started | Feb 08 02:10:28 PM UTC 25 |
| Finished | Feb 08 02:10:48 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667069649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2667069649 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.3402031660 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 558839330 ps |
| CPU time | 8.47 seconds |
| Started | Feb 08 02:10:17 PM UTC 25 |
| Finished | Feb 08 02:10:27 PM UTC 25 |
| Peak memory | 221340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402031660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3402031660 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.1028308723 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1128901312 ps |
| CPU time | 17.2 seconds |
| Started | Feb 08 02:10:12 PM UTC 25 |
| Finished | Feb 08 02:10:30 PM UTC 25 |
| Peak memory | 225316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028308723 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.1028308723 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2839069363 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 13156579533 ps |
| CPU time | 7017.84 seconds |
| Started | Feb 08 02:10:31 PM UTC 25 |
| Finished | Feb 08 04:08:21 PM UTC 25 |
| Peak memory | 246092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2839069363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctr l_stress_all_with_rand_reset.2839069363 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.3383695124 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 518131401 ps |
| CPU time | 6.75 seconds |
| Started | Feb 08 02:11:18 PM UTC 25 |
| Finished | Feb 08 02:11:27 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383695124 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3383695124 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2132126070 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 5997480920 ps |
| CPU time | 165.02 seconds |
| Started | Feb 08 02:11:05 PM UTC 25 |
| Finished | Feb 08 02:13:53 PM UTC 25 |
| Peak memory | 258488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132126070 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.2132126070 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.102694281 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 693296716 ps |
| CPU time | 9.77 seconds |
| Started | Feb 08 02:11:06 PM UTC 25 |
| Finished | Feb 08 02:11:18 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102694281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.102694281 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.2749537519 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 273748499 ps |
| CPU time | 9.82 seconds |
| Started | Feb 08 02:10:54 PM UTC 25 |
| Finished | Feb 08 02:11:05 PM UTC 25 |
| Peak memory | 221276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749537519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2749537519 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.3765283142 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 261112866 ps |
| CPU time | 18.78 seconds |
| Started | Feb 08 02:10:49 PM UTC 25 |
| Finished | Feb 08 02:11:09 PM UTC 25 |
| Peak memory | 223396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765283142 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.3765283142 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.2871199150 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 172668760 ps |
| CPU time | 7.04 seconds |
| Started | Feb 08 02:11:48 PM UTC 25 |
| Finished | Feb 08 02:11:56 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871199150 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2871199150 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1030833945 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 5898359646 ps |
| CPU time | 206.99 seconds |
| Started | Feb 08 02:11:35 PM UTC 25 |
| Finished | Feb 08 02:15:05 PM UTC 25 |
| Peak memory | 253220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030833945 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.1030833945 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.2682114512 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 511063305 ps |
| CPU time | 17.31 seconds |
| Started | Feb 08 02:11:40 PM UTC 25 |
| Finished | Feb 08 02:11:59 PM UTC 25 |
| Peak memory | 223340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682114512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2682114512 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.1338354493 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 181432323 ps |
| CPU time | 8.27 seconds |
| Started | Feb 08 02:11:28 PM UTC 25 |
| Finished | Feb 08 02:11:39 PM UTC 25 |
| Peak memory | 221212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338354493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1338354493 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2591823296 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 176653695 ps |
| CPU time | 16.71 seconds |
| Started | Feb 08 02:11:27 PM UTC 25 |
| Finished | Feb 08 02:11:47 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591823296 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.2591823296 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3211936198 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 256631895 ps |
| CPU time | 7.38 seconds |
| Started | Feb 08 02:12:07 PM UTC 25 |
| Finished | Feb 08 02:12:16 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211936198 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3211936198 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3224110721 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 25660134847 ps |
| CPU time | 105.31 seconds |
| Started | Feb 08 02:11:57 PM UTC 25 |
| Finished | Feb 08 02:13:45 PM UTC 25 |
| Peak memory | 257068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224110721 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.3224110721 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1179433402 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 288548430 ps |
| CPU time | 15.15 seconds |
| Started | Feb 08 02:11:59 PM UTC 25 |
| Finished | Feb 08 02:12:16 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179433402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1179433402 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2926229629 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 540303889 ps |
| CPU time | 8.97 seconds |
| Started | Feb 08 02:11:53 PM UTC 25 |
| Finished | Feb 08 02:12:04 PM UTC 25 |
| Peak memory | 221212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926229629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2926229629 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.524283586 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 213881558 ps |
| CPU time | 16.72 seconds |
| Started | Feb 08 02:11:48 PM UTC 25 |
| Finished | Feb 08 02:12:06 PM UTC 25 |
| Peak memory | 223328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524283586 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.524283586 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.4088201956 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 127147551 ps |
| CPU time | 6.53 seconds |
| Started | Feb 08 02:13:00 PM UTC 25 |
| Finished | Feb 08 02:13:08 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088201956 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4088201956 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3964361113 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 3856699929 ps |
| CPU time | 110.79 seconds |
| Started | Feb 08 02:12:26 PM UTC 25 |
| Finished | Feb 08 02:14:20 PM UTC 25 |
| Peak memory | 223584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964361113 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.3964361113 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.2760488861 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 251952466 ps |
| CPU time | 14.8 seconds |
| Started | Feb 08 02:12:30 PM UTC 25 |
| Finished | Feb 08 02:12:47 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760488861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2760488861 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.70150878 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 545677652 ps |
| CPU time | 6.66 seconds |
| Started | Feb 08 02:12:17 PM UTC 25 |
| Finished | Feb 08 02:12:26 PM UTC 25 |
| Peak memory | 221332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70150878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.70150878 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2668564057 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 364960949 ps |
| CPU time | 11.83 seconds |
| Started | Feb 08 02:12:16 PM UTC 25 |
| Finished | Feb 08 02:12:30 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668564057 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.2668564057 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.876894515 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 88886842 ps |
| CPU time | 6.64 seconds |
| Started | Feb 08 02:13:46 PM UTC 25 |
| Finished | Feb 08 02:13:55 PM UTC 25 |
| Peak memory | 221100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876894515 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.876894515 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3464783072 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1747756307 ps |
| CPU time | 108.57 seconds |
| Started | Feb 08 02:13:29 PM UTC 25 |
| Finished | Feb 08 02:15:20 PM UTC 25 |
| Peak memory | 245112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464783072 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.3464783072 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.2665347329 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 507058213 ps |
| CPU time | 14.61 seconds |
| Started | Feb 08 02:13:29 PM UTC 25 |
| Finished | Feb 08 02:13:45 PM UTC 25 |
| Peak memory | 223340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665347329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2665347329 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.178962915 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 179764838 ps |
| CPU time | 8.21 seconds |
| Started | Feb 08 02:13:26 PM UTC 25 |
| Finished | Feb 08 02:13:36 PM UTC 25 |
| Peak memory | 221204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178962915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.178962915 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.1566932529 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 297845302 ps |
| CPU time | 17.1 seconds |
| Started | Feb 08 02:13:09 PM UTC 25 |
| Finished | Feb 08 02:13:28 PM UTC 25 |
| Peak memory | 225380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566932529 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.1566932529 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3014554236 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 110430967178 ps |
| CPU time | 2755.4 seconds |
| Started | Feb 08 02:13:37 PM UTC 25 |
| Finished | Feb 08 03:00:03 PM UTC 25 |
| Peak memory | 256356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3014554236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctr l_stress_all_with_rand_reset.3014554236 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.2548333275 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 598280497 ps |
| CPU time | 4.37 seconds |
| Started | Feb 08 02:14:21 PM UTC 25 |
| Finished | Feb 08 02:14:26 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548333275 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2548333275 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2784758533 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3156155613 ps |
| CPU time | 127.51 seconds |
| Started | Feb 08 02:13:55 PM UTC 25 |
| Finished | Feb 08 02:16:06 PM UTC 25 |
| Peak memory | 223584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784758533 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.2784758533 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.3679789050 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 498238090 ps |
| CPU time | 16.36 seconds |
| Started | Feb 08 02:14:09 PM UTC 25 |
| Finished | Feb 08 02:14:27 PM UTC 25 |
| Peak memory | 223340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679789050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3679789050 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2771305609 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 521387198 ps |
| CPU time | 11.49 seconds |
| Started | Feb 08 02:13:54 PM UTC 25 |
| Finished | Feb 08 02:14:08 PM UTC 25 |
| Peak memory | 221276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771305609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2771305609 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1118125715 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 19493748564 ps |
| CPU time | 806.09 seconds |
| Started | Feb 08 02:14:09 PM UTC 25 |
| Finished | Feb 08 02:27:45 PM UTC 25 |
| Peak memory | 234780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1118125715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctr l_stress_all_with_rand_reset.1118125715 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.4227137754 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 335578323 ps |
| CPU time | 5.78 seconds |
| Started | Feb 08 02:14:42 PM UTC 25 |
| Finished | Feb 08 02:14:49 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227137754 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.4227137754 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1283634338 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 16907196172 ps |
| CPU time | 149.72 seconds |
| Started | Feb 08 02:14:38 PM UTC 25 |
| Finished | Feb 08 02:17:10 PM UTC 25 |
| Peak memory | 256360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283634338 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.1283634338 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.2808383994 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 178953761 ps |
| CPU time | 10.73 seconds |
| Started | Feb 08 02:14:38 PM UTC 25 |
| Finished | Feb 08 02:14:50 PM UTC 25 |
| Peak memory | 223264 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808383994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2808383994 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.2285068909 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 2190255497 ps |
| CPU time | 8.3 seconds |
| Started | Feb 08 02:14:28 PM UTC 25 |
| Finished | Feb 08 02:14:37 PM UTC 25 |
| Peak memory | 221276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285068909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2285068909 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.1771890101 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 307003733 ps |
| CPU time | 13.31 seconds |
| Started | Feb 08 02:14:27 PM UTC 25 |
| Finished | Feb 08 02:14:41 PM UTC 25 |
| Peak memory | 221148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771890101 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.1771890101 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.2776951228 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 520000761 ps |
| CPU time | 6.68 seconds |
| Started | Feb 08 02:15:22 PM UTC 25 |
| Finished | Feb 08 02:15:30 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776951228 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2776951228 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2617637199 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 9771368046 ps |
| CPU time | 195.53 seconds |
| Started | Feb 08 02:15:00 PM UTC 25 |
| Finished | Feb 08 02:18:19 PM UTC 25 |
| Peak memory | 256348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617637199 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.2617637199 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.581398637 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 471910531 ps |
| CPU time | 14.95 seconds |
| Started | Feb 08 02:15:06 PM UTC 25 |
| Finished | Feb 08 02:15:23 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581398637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.581398637 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.305411669 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 278704826 ps |
| CPU time | 8.25 seconds |
| Started | Feb 08 02:14:50 PM UTC 25 |
| Finished | Feb 08 02:15:00 PM UTC 25 |
| Peak memory | 221204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305411669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.305411669 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.1661128720 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1208511662 ps |
| CPU time | 20.56 seconds |
| Started | Feb 08 02:14:50 PM UTC 25 |
| Finished | Feb 08 02:15:12 PM UTC 25 |
| Peak memory | 225380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661128720 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.1661128720 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3678550578 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 173936054083 ps |
| CPU time | 1484.67 seconds |
| Started | Feb 08 02:15:14 PM UTC 25 |
| Finished | Feb 08 02:40:15 PM UTC 25 |
| Peak memory | 245256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3678550578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctr l_stress_all_with_rand_reset.3678550578 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.952348008 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 131725716 ps |
| CPU time | 6.69 seconds |
| Started | Feb 08 02:16:07 PM UTC 25 |
| Finished | Feb 08 02:16:15 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952348008 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.952348008 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.525042699 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 6902681176 ps |
| CPU time | 149.23 seconds |
| Started | Feb 08 02:15:40 PM UTC 25 |
| Finished | Feb 08 02:18:12 PM UTC 25 |
| Peak memory | 257468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525042699 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.525042699 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.1260419734 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 616140588 ps |
| CPU time | 16 seconds |
| Started | Feb 08 02:15:44 PM UTC 25 |
| Finished | Feb 08 02:16:01 PM UTC 25 |
| Peak memory | 223340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260419734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1260419734 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.716373916 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 486640115 ps |
| CPU time | 10.34 seconds |
| Started | Feb 08 02:15:31 PM UTC 25 |
| Finished | Feb 08 02:15:43 PM UTC 25 |
| Peak memory | 221204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716373916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.716373916 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2457269284 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 164724510 ps |
| CPU time | 14.22 seconds |
| Started | Feb 08 02:15:24 PM UTC 25 |
| Finished | Feb 08 02:15:39 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457269284 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.2457269284 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.4146840023 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 50459039759 ps |
| CPU time | 7416.01 seconds |
| Started | Feb 08 02:16:02 PM UTC 25 |
| Finished | Feb 08 04:20:38 PM UTC 25 |
| Peak memory | 248208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4146840023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctr l_stress_all_with_rand_reset.4146840023 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1878294265 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 126790665 ps |
| CPU time | 6.8 seconds |
| Started | Feb 08 02:05:21 PM UTC 25 |
| Finished | Feb 08 02:05:30 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878294265 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1878294265 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2018873302 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 252612694 ps |
| CPU time | 17.41 seconds |
| Started | Feb 08 02:05:14 PM UTC 25 |
| Finished | Feb 08 02:05:33 PM UTC 25 |
| Peak memory | 223332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018873302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2018873302 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.2717984059 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 384668943 ps |
| CPU time | 123.01 seconds |
| Started | Feb 08 02:05:17 PM UTC 25 |
| Finished | Feb 08 02:07:23 PM UTC 25 |
| Peak memory | 257424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717984059 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2717984059 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1194727468 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 291186179 ps |
| CPU time | 9.05 seconds |
| Started | Feb 08 02:05:06 PM UTC 25 |
| Finished | Feb 08 02:05:16 PM UTC 25 |
| Peak memory | 221228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194727468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1194727468 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.1024392395 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 479587976 ps |
| CPU time | 6.38 seconds |
| Started | Feb 08 02:17:58 PM UTC 25 |
| Finished | Feb 08 02:18:05 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024392395 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1024392395 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3097356649 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 937009224 ps |
| CPU time | 70.36 seconds |
| Started | Feb 08 02:16:44 PM UTC 25 |
| Finished | Feb 08 02:17:56 PM UTC 25 |
| Peak memory | 257260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097356649 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.3097356649 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.2483643750 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 979002852 ps |
| CPU time | 13.43 seconds |
| Started | Feb 08 02:17:11 PM UTC 25 |
| Finished | Feb 08 02:17:26 PM UTC 25 |
| Peak memory | 223340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483643750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2483643750 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.1545233784 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 1840936310 ps |
| CPU time | 8.83 seconds |
| Started | Feb 08 02:16:33 PM UTC 25 |
| Finished | Feb 08 02:16:43 PM UTC 25 |
| Peak memory | 221340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545233784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1545233784 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3636684257 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 159905803 ps |
| CPU time | 14.46 seconds |
| Started | Feb 08 02:16:16 PM UTC 25 |
| Finished | Feb 08 02:16:32 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636684257 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.3636684257 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2244348122 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 164904621383 ps |
| CPU time | 1822.48 seconds |
| Started | Feb 08 02:17:26 PM UTC 25 |
| Finished | Feb 08 02:48:09 PM UTC 25 |
| Peak memory | 246116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2244348122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctr l_stress_all_with_rand_reset.2244348122 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3467521013 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 87511572 ps |
| CPU time | 6.98 seconds |
| Started | Feb 08 02:18:29 PM UTC 25 |
| Finished | Feb 08 02:18:37 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467521013 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3467521013 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4115459267 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1923393590 ps |
| CPU time | 93.88 seconds |
| Started | Feb 08 02:18:20 PM UTC 25 |
| Finished | Feb 08 02:19:56 PM UTC 25 |
| Peak memory | 244012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115459267 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.4115459267 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.4095297590 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 666840268 ps |
| CPU time | 13.98 seconds |
| Started | Feb 08 02:18:25 PM UTC 25 |
| Finished | Feb 08 02:18:41 PM UTC 25 |
| Peak memory | 223404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095297590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4095297590 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.1533492598 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 8401017219 ps |
| CPU time | 12.08 seconds |
| Started | Feb 08 02:18:12 PM UTC 25 |
| Finished | Feb 08 02:18:26 PM UTC 25 |
| Peak memory | 221276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533492598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1533492598 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.3275010840 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1185821695 ps |
| CPU time | 15 seconds |
| Started | Feb 08 02:18:07 PM UTC 25 |
| Finished | Feb 08 02:18:23 PM UTC 25 |
| Peak memory | 225380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275010840 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.3275010840 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.914560549 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 86230960 ps |
| CPU time | 5.77 seconds |
| Started | Feb 08 02:19:57 PM UTC 25 |
| Finished | Feb 08 02:20:04 PM UTC 25 |
| Peak memory | 221216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914560549 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.914560549 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4077154123 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 7130367179 ps |
| CPU time | 123.83 seconds |
| Started | Feb 08 02:18:51 PM UTC 25 |
| Finished | Feb 08 02:20:57 PM UTC 25 |
| Peak memory | 259372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077154123 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.4077154123 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.2695297878 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 990606066 ps |
| CPU time | 17.35 seconds |
| Started | Feb 08 02:18:54 PM UTC 25 |
| Finished | Feb 08 02:19:12 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695297878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2695297878 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2208065307 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 395290231 ps |
| CPU time | 6.79 seconds |
| Started | Feb 08 02:18:42 PM UTC 25 |
| Finished | Feb 08 02:18:50 PM UTC 25 |
| Peak memory | 221276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208065307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2208065307 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.1476557904 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 207920614 ps |
| CPU time | 13.85 seconds |
| Started | Feb 08 02:18:38 PM UTC 25 |
| Finished | Feb 08 02:18:53 PM UTC 25 |
| Peak memory | 225316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476557904 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.1476557904 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.648737190 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 95766328450 ps |
| CPU time | 2430.58 seconds |
| Started | Feb 08 02:19:13 PM UTC 25 |
| Finished | Feb 08 03:00:10 PM UTC 25 |
| Peak memory | 256360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=648737190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl _stress_all_with_rand_reset.648737190 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.56099956 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 131471710 ps |
| CPU time | 6.71 seconds |
| Started | Feb 08 02:20:58 PM UTC 25 |
| Finished | Feb 08 02:21:06 PM UTC 25 |
| Peak memory | 221224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56099956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.56099956 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2277925184 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 8835013115 ps |
| CPU time | 219.07 seconds |
| Started | Feb 08 02:20:25 PM UTC 25 |
| Finished | Feb 08 02:24:07 PM UTC 25 |
| Peak memory | 244564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277925184 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.2277925184 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2434698469 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1661518058 ps |
| CPU time | 12.69 seconds |
| Started | Feb 08 02:20:30 PM UTC 25 |
| Finished | Feb 08 02:20:44 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434698469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2434698469 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.1819790144 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 572784352 ps |
| CPU time | 8.32 seconds |
| Started | Feb 08 02:20:20 PM UTC 25 |
| Finished | Feb 08 02:20:29 PM UTC 25 |
| Peak memory | 221276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819790144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1819790144 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.1353132283 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 247840205 ps |
| CPU time | 17.51 seconds |
| Started | Feb 08 02:20:05 PM UTC 25 |
| Finished | Feb 08 02:20:24 PM UTC 25 |
| Peak memory | 225380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353132283 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.1353132283 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/33.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.1638243937 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 261689775 ps |
| CPU time | 6.65 seconds |
| Started | Feb 08 02:22:22 PM UTC 25 |
| Finished | Feb 08 02:22:30 PM UTC 25 |
| Peak memory | 221284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638243937 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1638243937 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.997801034 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 751094991 ps |
| CPU time | 79.13 seconds |
| Started | Feb 08 02:21:35 PM UTC 25 |
| Finished | Feb 08 02:22:56 PM UTC 25 |
| Peak memory | 252596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997801034 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.997801034 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.4043306563 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 639299668 ps |
| CPU time | 9.59 seconds |
| Started | Feb 08 02:21:59 PM UTC 25 |
| Finished | Feb 08 02:22:10 PM UTC 25 |
| Peak memory | 223204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043306563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4043306563 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.4294420255 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 368263010 ps |
| CPU time | 7.57 seconds |
| Started | Feb 08 02:21:26 PM UTC 25 |
| Finished | Feb 08 02:21:35 PM UTC 25 |
| Peak memory | 221276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294420255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4294420255 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.777423288 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 215017903 ps |
| CPU time | 17.25 seconds |
| Started | Feb 08 02:21:07 PM UTC 25 |
| Finished | Feb 08 02:21:25 PM UTC 25 |
| Peak memory | 223328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777423288 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.777423288 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/34.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.2525568601 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 126316455 ps |
| CPU time | 8.08 seconds |
| Started | Feb 08 02:23:04 PM UTC 25 |
| Finished | Feb 08 02:23:13 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525568601 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2525568601 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1236750234 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 971548187 ps |
| CPU time | 85.02 seconds |
| Started | Feb 08 02:22:42 PM UTC 25 |
| Finished | Feb 08 02:24:10 PM UTC 25 |
| Peak memory | 257364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236750234 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.1236750234 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.3493381933 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 169501394 ps |
| CPU time | 15.58 seconds |
| Started | Feb 08 02:22:45 PM UTC 25 |
| Finished | Feb 08 02:23:02 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493381933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3493381933 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.1106359580 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 138260549 ps |
| CPU time | 8.41 seconds |
| Started | Feb 08 02:22:32 PM UTC 25 |
| Finished | Feb 08 02:22:42 PM UTC 25 |
| Peak memory | 221276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106359580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1106359580 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.472976187 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1188460868 ps |
| CPU time | 12.67 seconds |
| Started | Feb 08 02:22:31 PM UTC 25 |
| Finished | Feb 08 02:22:45 PM UTC 25 |
| Peak memory | 221216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472976187 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.472976187 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3446191773 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 38038889730 ps |
| CPU time | 7969.17 seconds |
| Started | Feb 08 02:22:57 PM UTC 25 |
| Finished | Feb 08 04:36:44 PM UTC 25 |
| Peak memory | 241992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3446191773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctr l_stress_all_with_rand_reset.3446191773 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1916529121 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 460083617 ps |
| CPU time | 7.37 seconds |
| Started | Feb 08 02:23:46 PM UTC 25 |
| Finished | Feb 08 02:23:54 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916529121 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1916529121 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1179457759 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 11681918338 ps |
| CPU time | 152.29 seconds |
| Started | Feb 08 02:23:21 PM UTC 25 |
| Finished | Feb 08 02:25:56 PM UTC 25 |
| Peak memory | 259372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179457759 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.1179457759 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.2250081387 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 260645596 ps |
| CPU time | 17.73 seconds |
| Started | Feb 08 02:23:26 PM UTC 25 |
| Finished | Feb 08 02:23:45 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250081387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2250081387 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.190385046 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 531658928 ps |
| CPU time | 12.43 seconds |
| Started | Feb 08 02:23:21 PM UTC 25 |
| Finished | Feb 08 02:23:34 PM UTC 25 |
| Peak memory | 221204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190385046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.190385046 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1126576815 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 492008289 ps |
| CPU time | 10.39 seconds |
| Started | Feb 08 02:23:14 PM UTC 25 |
| Finished | Feb 08 02:23:25 PM UTC 25 |
| Peak memory | 221284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126576815 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.1126576815 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/36.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.1321021348 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 347690998 ps |
| CPU time | 5.65 seconds |
| Started | Feb 08 02:24:27 PM UTC 25 |
| Finished | Feb 08 02:24:34 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321021348 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1321021348 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1843720171 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 10781278613 ps |
| CPU time | 77.86 seconds |
| Started | Feb 08 02:24:08 PM UTC 25 |
| Finished | Feb 08 02:25:28 PM UTC 25 |
| Peak memory | 244160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843720171 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.1843720171 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2296183100 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1087238580 ps |
| CPU time | 14.88 seconds |
| Started | Feb 08 02:24:10 PM UTC 25 |
| Finished | Feb 08 02:24:26 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296183100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2296183100 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.2249930995 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 142365127 ps |
| CPU time | 10.58 seconds |
| Started | Feb 08 02:24:08 PM UTC 25 |
| Finished | Feb 08 02:24:20 PM UTC 25 |
| Peak memory | 221276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249930995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2249930995 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2912817973 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 691497787 ps |
| CPU time | 11.07 seconds |
| Started | Feb 08 02:23:55 PM UTC 25 |
| Finished | Feb 08 02:24:07 PM UTC 25 |
| Peak memory | 223396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912817973 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.2912817973 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/37.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.4063750431 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 309824686 ps |
| CPU time | 5.71 seconds |
| Started | Feb 08 02:25:57 PM UTC 25 |
| Finished | Feb 08 02:26:04 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063750431 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4063750431 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.415238641 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3425053842 ps |
| CPU time | 132.09 seconds |
| Started | Feb 08 02:25:10 PM UTC 25 |
| Finished | Feb 08 02:27:25 PM UTC 25 |
| Peak memory | 245056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415238641 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.415238641 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.3150243633 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1041318322 ps |
| CPU time | 14.64 seconds |
| Started | Feb 08 02:25:29 PM UTC 25 |
| Finished | Feb 08 02:25:45 PM UTC 25 |
| Peak memory | 223340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150243633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3150243633 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.3093263619 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 283336273 ps |
| CPU time | 6.51 seconds |
| Started | Feb 08 02:25:01 PM UTC 25 |
| Finished | Feb 08 02:25:08 PM UTC 25 |
| Peak memory | 221212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093263619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3093263619 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.204352351 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 1272993022 ps |
| CPU time | 22.63 seconds |
| Started | Feb 08 02:24:35 PM UTC 25 |
| Finished | Feb 08 02:25:00 PM UTC 25 |
| Peak memory | 225312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204352351 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.204352351 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.792304401 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 504150127 ps |
| CPU time | 10.58 seconds |
| Started | Feb 08 02:26:58 PM UTC 25 |
| Finished | Feb 08 02:27:10 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792304401 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.792304401 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.756915677 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5713169954 ps |
| CPU time | 104.08 seconds |
| Started | Feb 08 02:26:20 PM UTC 25 |
| Finished | Feb 08 02:28:06 PM UTC 25 |
| Peak memory | 223592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756915677 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.756915677 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.3435820284 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1660211770 ps |
| CPU time | 12.6 seconds |
| Started | Feb 08 02:26:27 PM UTC 25 |
| Finished | Feb 08 02:26:41 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435820284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3435820284 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.4156616500 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 140730031 ps |
| CPU time | 8.98 seconds |
| Started | Feb 08 02:26:09 PM UTC 25 |
| Finished | Feb 08 02:26:19 PM UTC 25 |
| Peak memory | 221340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156616500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4156616500 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3299775098 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 411246551 ps |
| CPU time | 20.57 seconds |
| Started | Feb 08 02:26:05 PM UTC 25 |
| Finished | Feb 08 02:26:27 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299775098 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.3299775098 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2073183379 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 397108069 ps |
| CPU time | 6.45 seconds |
| Started | Feb 08 02:05:42 PM UTC 25 |
| Finished | Feb 08 02:05:49 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073183379 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2073183379 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1966789533 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5359214020 ps |
| CPU time | 113.16 seconds |
| Started | Feb 08 02:05:33 PM UTC 25 |
| Finished | Feb 08 02:07:28 PM UTC 25 |
| Peak memory | 257420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966789533 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.1966789533 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.147724244 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4992662980 ps |
| CPU time | 16.07 seconds |
| Started | Feb 08 02:05:34 PM UTC 25 |
| Finished | Feb 08 02:05:51 PM UTC 25 |
| Peak memory | 223328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147724244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.147724244 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.1114994135 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 634829397 ps |
| CPU time | 8.39 seconds |
| Started | Feb 08 02:05:31 PM UTC 25 |
| Finished | Feb 08 02:05:40 PM UTC 25 |
| Peak memory | 221204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114994135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1114994135 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.903943895 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 195549483 ps |
| CPU time | 145.21 seconds |
| Started | Feb 08 02:05:42 PM UTC 25 |
| Finished | Feb 08 02:08:10 PM UTC 25 |
| Peak memory | 257224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903943895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.903943895 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.4015599790 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 374950771 ps |
| CPU time | 7.13 seconds |
| Started | Feb 08 02:05:23 PM UTC 25 |
| Finished | Feb 08 02:05:32 PM UTC 25 |
| Peak memory | 221228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015599790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.4015599790 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3631397221 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 322229725 ps |
| CPU time | 14.04 seconds |
| Started | Feb 08 02:05:25 PM UTC 25 |
| Finished | Feb 08 02:05:41 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631397221 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.3631397221 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1357813243 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 14385296618 ps |
| CPU time | 6813.75 seconds |
| Started | Feb 08 02:05:41 PM UTC 25 |
| Finished | Feb 08 04:00:05 PM UTC 25 |
| Peak memory | 235920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1357813243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl _stress_all_with_rand_reset.1357813243 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.676689927 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 129098716 ps |
| CPU time | 5.06 seconds |
| Started | Feb 08 02:27:51 PM UTC 25 |
| Finished | Feb 08 02:27:57 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676689927 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.676689927 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3609491037 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 6183519904 ps |
| CPU time | 84.57 seconds |
| Started | Feb 08 02:27:32 PM UTC 25 |
| Finished | Feb 08 02:28:58 PM UTC 25 |
| Peak memory | 252956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609491037 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.3609491037 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.1540226854 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 615348508 ps |
| CPU time | 12.63 seconds |
| Started | Feb 08 02:27:36 PM UTC 25 |
| Finished | Feb 08 02:27:50 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540226854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1540226854 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3950229182 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 96442148 ps |
| CPU time | 7.81 seconds |
| Started | Feb 08 02:27:26 PM UTC 25 |
| Finished | Feb 08 02:27:35 PM UTC 25 |
| Peak memory | 221212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950229182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3950229182 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2759048821 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 202255192 ps |
| CPU time | 18.21 seconds |
| Started | Feb 08 02:27:11 PM UTC 25 |
| Finished | Feb 08 02:27:31 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759048821 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.2759048821 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1938701445 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 16802359646 ps |
| CPU time | 858.61 seconds |
| Started | Feb 08 02:27:46 PM UTC 25 |
| Finished | Feb 08 02:42:15 PM UTC 25 |
| Peak memory | 245084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1938701445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctr l_stress_all_with_rand_reset.1938701445 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.417050783 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 513237898 ps |
| CPU time | 13.14 seconds |
| Started | Feb 08 02:28:59 PM UTC 25 |
| Finished | Feb 08 02:29:14 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417050783 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.417050783 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.753418366 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1661863840 ps |
| CPU time | 104.39 seconds |
| Started | Feb 08 02:28:17 PM UTC 25 |
| Finished | Feb 08 02:30:04 PM UTC 25 |
| Peak memory | 257280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753418366 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.753418366 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2771853164 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 508363328 ps |
| CPU time | 13.28 seconds |
| Started | Feb 08 02:28:22 PM UTC 25 |
| Finished | Feb 08 02:28:37 PM UTC 25 |
| Peak memory | 223340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771853164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2771853164 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1820289979 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 533279884 ps |
| CPU time | 8.37 seconds |
| Started | Feb 08 02:28:07 PM UTC 25 |
| Finished | Feb 08 02:28:16 PM UTC 25 |
| Peak memory | 221276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820289979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1820289979 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.4190766225 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 1208561197 ps |
| CPU time | 22.03 seconds |
| Started | Feb 08 02:27:58 PM UTC 25 |
| Finished | Feb 08 02:28:21 PM UTC 25 |
| Peak memory | 225316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190766225 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.4190766225 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.249605026 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 350029536 ps |
| CPU time | 5.68 seconds |
| Started | Feb 08 02:30:30 PM UTC 25 |
| Finished | Feb 08 02:30:37 PM UTC 25 |
| Peak memory | 221284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249605026 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.249605026 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3669195165 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 3780996315 ps |
| CPU time | 248.95 seconds |
| Started | Feb 08 02:29:49 PM UTC 25 |
| Finished | Feb 08 02:34:01 PM UTC 25 |
| Peak memory | 257324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669195165 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.3669195165 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1650715146 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 698384145 ps |
| CPU time | 13.68 seconds |
| Started | Feb 08 02:30:05 PM UTC 25 |
| Finished | Feb 08 02:30:20 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650715146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1650715146 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.4103497709 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 492494319 ps |
| CPU time | 7.36 seconds |
| Started | Feb 08 02:29:39 PM UTC 25 |
| Finished | Feb 08 02:29:48 PM UTC 25 |
| Peak memory | 221212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103497709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4103497709 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1795059859 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 292052473 ps |
| CPU time | 22.61 seconds |
| Started | Feb 08 02:29:14 PM UTC 25 |
| Finished | Feb 08 02:29:38 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795059859 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.1795059859 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/42.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1261605712 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 133940339 ps |
| CPU time | 5.22 seconds |
| Started | Feb 08 02:31:28 PM UTC 25 |
| Finished | Feb 08 02:31:46 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261605712 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1261605712 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.311130669 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2794881885 ps |
| CPU time | 152.03 seconds |
| Started | Feb 08 02:31:07 PM UTC 25 |
| Finished | Feb 08 02:33:44 PM UTC 25 |
| Peak memory | 258436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311130669 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.311130669 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3992853138 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 1556155087 ps |
| CPU time | 14.78 seconds |
| Started | Feb 08 02:31:08 PM UTC 25 |
| Finished | Feb 08 02:31:27 PM UTC 25 |
| Peak memory | 223340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992853138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3992853138 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.2709342464 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 543774735 ps |
| CPU time | 10.07 seconds |
| Started | Feb 08 02:30:54 PM UTC 25 |
| Finished | Feb 08 02:31:06 PM UTC 25 |
| Peak memory | 221276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709342464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2709342464 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3390799179 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 676873033 ps |
| CPU time | 27.88 seconds |
| Started | Feb 08 02:30:38 PM UTC 25 |
| Finished | Feb 08 02:31:07 PM UTC 25 |
| Peak memory | 225316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390799179 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.3390799179 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3541567770 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 36774231333 ps |
| CPU time | 780.45 seconds |
| Started | Feb 08 02:31:27 PM UTC 25 |
| Finished | Feb 08 02:44:48 PM UTC 25 |
| Peak memory | 245020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3541567770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctr l_stress_all_with_rand_reset.3541567770 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.3211668032 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 86751565 ps |
| CPU time | 5.73 seconds |
| Started | Feb 08 02:33:20 PM UTC 25 |
| Finished | Feb 08 02:33:28 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211668032 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3211668032 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1437394919 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3817508347 ps |
| CPU time | 134.83 seconds |
| Started | Feb 08 02:32:28 PM UTC 25 |
| Finished | Feb 08 02:34:47 PM UTC 25 |
| Peak memory | 257440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437394919 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.1437394919 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.1795330213 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 169991174 ps |
| CPU time | 14.06 seconds |
| Started | Feb 08 02:32:34 PM UTC 25 |
| Finished | Feb 08 02:32:51 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795330213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1795330213 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.269056448 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 138237705 ps |
| CPU time | 10.13 seconds |
| Started | Feb 08 02:32:14 PM UTC 25 |
| Finished | Feb 08 02:32:26 PM UTC 25 |
| Peak memory | 221204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269056448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.269056448 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.2684225926 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 306915077 ps |
| CPU time | 21.2 seconds |
| Started | Feb 08 02:31:49 PM UTC 25 |
| Finished | Feb 08 02:32:13 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684225926 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.2684225926 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/44.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.2850713850 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 132527519 ps |
| CPU time | 6.7 seconds |
| Started | Feb 08 02:34:18 PM UTC 25 |
| Finished | Feb 08 02:34:26 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850713850 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2850713850 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.199999776 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1666084264 ps |
| CPU time | 112.35 seconds |
| Started | Feb 08 02:33:53 PM UTC 25 |
| Finished | Feb 08 02:35:51 PM UTC 25 |
| Peak memory | 257280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199999776 -assert nopostproc +UVM_TESTNAME=rom_ct rl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.199999776 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.2260461983 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1036382146 ps |
| CPU time | 17.94 seconds |
| Started | Feb 08 02:33:55 PM UTC 25 |
| Finished | Feb 08 02:34:17 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260461983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2260461983 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.861329506 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 99331986 ps |
| CPU time | 7.77 seconds |
| Started | Feb 08 02:33:45 PM UTC 25 |
| Finished | Feb 08 02:33:54 PM UTC 25 |
| Peak memory | 221332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861329506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.861329506 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.3345757997 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 797733913 ps |
| CPU time | 18.58 seconds |
| Started | Feb 08 02:33:29 PM UTC 25 |
| Finished | Feb 08 02:33:52 PM UTC 25 |
| Peak memory | 225316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345757997 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.3345757997 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.1678795444 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 129166233 ps |
| CPU time | 6.6 seconds |
| Started | Feb 08 02:35:13 PM UTC 25 |
| Finished | Feb 08 02:35:20 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678795444 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1678795444 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1209186642 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 7812022555 ps |
| CPU time | 129.05 seconds |
| Started | Feb 08 02:34:48 PM UTC 25 |
| Finished | Feb 08 02:37:00 PM UTC 25 |
| Peak memory | 252720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209186642 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.1209186642 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.2875785176 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 998066971 ps |
| CPU time | 15.97 seconds |
| Started | Feb 08 02:34:54 PM UTC 25 |
| Finished | Feb 08 02:35:12 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875785176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2875785176 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.466491203 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 544856023 ps |
| CPU time | 7.96 seconds |
| Started | Feb 08 02:34:44 PM UTC 25 |
| Finished | Feb 08 02:34:54 PM UTC 25 |
| Peak memory | 221268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466491203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.466491203 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.1049302043 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 350643003 ps |
| CPU time | 13.79 seconds |
| Started | Feb 08 02:34:27 PM UTC 25 |
| Finished | Feb 08 02:34:43 PM UTC 25 |
| Peak memory | 221152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049302043 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.1049302043 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/46.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.185605182 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 269292750 ps |
| CPU time | 5.61 seconds |
| Started | Feb 08 02:36:08 PM UTC 25 |
| Finished | Feb 08 02:36:15 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185605182 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.185605182 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2440390272 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 9933769826 ps |
| CPU time | 179.71 seconds |
| Started | Feb 08 02:35:33 PM UTC 25 |
| Finished | Feb 08 02:38:36 PM UTC 25 |
| Peak memory | 257452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440390272 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.2440390272 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.784530357 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 253597241 ps |
| CPU time | 16.19 seconds |
| Started | Feb 08 02:35:49 PM UTC 25 |
| Finished | Feb 08 02:36:07 PM UTC 25 |
| Peak memory | 223332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784530357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.784530357 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1038051045 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 97738410 ps |
| CPU time | 7.08 seconds |
| Started | Feb 08 02:35:24 PM UTC 25 |
| Finished | Feb 08 02:35:32 PM UTC 25 |
| Peak memory | 221212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038051045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1038051045 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.3082421910 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1436951810 ps |
| CPU time | 24.03 seconds |
| Started | Feb 08 02:35:22 PM UTC 25 |
| Finished | Feb 08 02:35:48 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082421910 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.3082421910 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.567583786 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 89188139 ps |
| CPU time | 4.39 seconds |
| Started | Feb 08 02:37:00 PM UTC 25 |
| Finished | Feb 08 02:37:07 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567583786 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.567583786 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2587989129 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 4852021315 ps |
| CPU time | 123.49 seconds |
| Started | Feb 08 02:36:35 PM UTC 25 |
| Finished | Feb 08 02:38:41 PM UTC 25 |
| Peak memory | 244732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587989129 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.2587989129 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.678759715 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 2251701704 ps |
| CPU time | 12.24 seconds |
| Started | Feb 08 02:36:41 PM UTC 25 |
| Finished | Feb 08 02:36:55 PM UTC 25 |
| Peak memory | 223332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678759715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.678759715 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.1664833719 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 397543318 ps |
| CPU time | 9.22 seconds |
| Started | Feb 08 02:36:30 PM UTC 25 |
| Finished | Feb 08 02:36:41 PM UTC 25 |
| Peak memory | 221140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664833719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1664833719 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.199588042 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 642898029 ps |
| CPU time | 11.25 seconds |
| Started | Feb 08 02:36:16 PM UTC 25 |
| Finished | Feb 08 02:36:29 PM UTC 25 |
| Peak memory | 221216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199588042 -assert no postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.199588042 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/48.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.960089007 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 733478617 ps |
| CPU time | 6.56 seconds |
| Started | Feb 08 02:37:45 PM UTC 25 |
| Finished | Feb 08 02:37:55 PM UTC 25 |
| Peak memory | 221152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960089007 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.960089007 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3762714170 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 13136331793 ps |
| CPU time | 179.97 seconds |
| Started | Feb 08 02:37:29 PM UTC 25 |
| Finished | Feb 08 02:40:33 PM UTC 25 |
| Peak memory | 259452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762714170 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.3762714170 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.2915664509 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 170242487 ps |
| CPU time | 11.36 seconds |
| Started | Feb 08 02:37:31 PM UTC 25 |
| Finished | Feb 08 02:37:44 PM UTC 25 |
| Peak memory | 223340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915664509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2915664509 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.3682610414 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 190728481 ps |
| CPU time | 7.53 seconds |
| Started | Feb 08 02:37:27 PM UTC 25 |
| Finished | Feb 08 02:37:36 PM UTC 25 |
| Peak memory | 221212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682610414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3682610414 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.2212736955 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 286778890 ps |
| CPU time | 20.25 seconds |
| Started | Feb 08 02:37:07 PM UTC 25 |
| Finished | Feb 08 02:37:30 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212736955 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.2212736955 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/49.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.711988719 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 85656204 ps |
| CPU time | 6.11 seconds |
| Started | Feb 08 02:06:02 PM UTC 25 |
| Finished | Feb 08 02:06:10 PM UTC 25 |
| Peak memory | 221168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711988719 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctr l_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.711988719 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3730863037 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2954700847 ps |
| CPU time | 190.4 seconds |
| Started | Feb 08 02:05:58 PM UTC 25 |
| Finished | Feb 08 02:09:12 PM UTC 25 |
| Peak memory | 223588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730863037 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.3730863037 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3597609139 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 999798957 ps |
| CPU time | 16.45 seconds |
| Started | Feb 08 02:06:00 PM UTC 25 |
| Finished | Feb 08 02:06:18 PM UTC 25 |
| Peak memory | 223332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597609139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3597609139 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.3800552275 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 108087861 ps |
| CPU time | 8.35 seconds |
| Started | Feb 08 02:05:52 PM UTC 25 |
| Finished | Feb 08 02:06:02 PM UTC 25 |
| Peak memory | 221268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800552275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3800552275 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.421106976 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 366404983 ps |
| CPU time | 8.36 seconds |
| Started | Feb 08 02:05:50 PM UTC 25 |
| Finished | Feb 08 02:05:59 PM UTC 25 |
| Peak memory | 221292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421106976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.421106976 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.3673614006 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1024181984 ps |
| CPU time | 17.5 seconds |
| Started | Feb 08 02:05:51 PM UTC 25 |
| Finished | Feb 08 02:06:10 PM UTC 25 |
| Peak memory | 223332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673614006 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.3673614006 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.59998850 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 45541361293 ps |
| CPU time | 1865.58 seconds |
| Started | Feb 08 02:06:01 PM UTC 25 |
| Finished | Feb 08 02:37:27 PM UTC 25 |
| Peak memory | 246188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=59998850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_s tress_all_with_rand_reset.59998850 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.3226882307 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 176350718 ps |
| CPU time | 5.95 seconds |
| Started | Feb 08 02:06:23 PM UTC 25 |
| Finished | Feb 08 02:06:30 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226882307 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3226882307 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1197431903 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 3638434358 ps |
| CPU time | 195.63 seconds |
| Started | Feb 08 02:06:16 PM UTC 25 |
| Finished | Feb 08 02:09:35 PM UTC 25 |
| Peak memory | 245224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197431903 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.1197431903 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.841188458 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 981686301 ps |
| CPU time | 23.94 seconds |
| Started | Feb 08 02:06:19 PM UTC 25 |
| Finished | Feb 08 02:06:44 PM UTC 25 |
| Peak memory | 221280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841188458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.841188458 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.289575168 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 202871924 ps |
| CPU time | 8.64 seconds |
| Started | Feb 08 02:06:10 PM UTC 25 |
| Finished | Feb 08 02:06:20 PM UTC 25 |
| Peak memory | 221208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289575168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.289575168 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1055683325 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 510541421 ps |
| CPU time | 11.86 seconds |
| Started | Feb 08 02:06:08 PM UTC 25 |
| Finished | Feb 08 02:06:21 PM UTC 25 |
| Peak memory | 223340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055683325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1055683325 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1992039104 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 592665447 ps |
| CPU time | 18.38 seconds |
| Started | Feb 08 02:06:10 PM UTC 25 |
| Finished | Feb 08 02:06:30 PM UTC 25 |
| Peak memory | 223320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992039104 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.1992039104 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2069169480 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 127444105 ps |
| CPU time | 6.52 seconds |
| Started | Feb 08 02:06:39 PM UTC 25 |
| Finished | Feb 08 02:06:47 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069169480 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2069169480 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3162284083 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 19261534783 ps |
| CPU time | 153.33 seconds |
| Started | Feb 08 02:06:33 PM UTC 25 |
| Finished | Feb 08 02:09:09 PM UTC 25 |
| Peak memory | 253068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162284083 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.3162284083 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.400617005 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 497664721 ps |
| CPU time | 14.6 seconds |
| Started | Feb 08 02:06:34 PM UTC 25 |
| Finished | Feb 08 02:06:50 PM UTC 25 |
| Peak memory | 223328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400617005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.400617005 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1194045866 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 97683141 ps |
| CPU time | 6.76 seconds |
| Started | Feb 08 02:06:31 PM UTC 25 |
| Finished | Feb 08 02:06:39 PM UTC 25 |
| Peak memory | 221332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194045866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1194045866 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.2377710696 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1024106713 ps |
| CPU time | 12.59 seconds |
| Started | Feb 08 02:06:28 PM UTC 25 |
| Finished | Feb 08 02:06:42 PM UTC 25 |
| Peak memory | 221228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377710696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2377710696 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2079236634 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 289956762 ps |
| CPU time | 12.3 seconds |
| Started | Feb 08 02:06:31 PM UTC 25 |
| Finished | Feb 08 02:06:45 PM UTC 25 |
| Peak memory | 223268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079236634 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.2079236634 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3053032721 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 216846210 ps |
| CPU time | 5.34 seconds |
| Started | Feb 08 02:06:55 PM UTC 25 |
| Finished | Feb 08 02:07:01 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053032721 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ct rl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3053032721 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1964051003 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3746693046 ps |
| CPU time | 158.52 seconds |
| Started | Feb 08 02:06:45 PM UTC 25 |
| Finished | Feb 08 02:09:27 PM UTC 25 |
| Peak memory | 257352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964051003 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.1964051003 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3089462079 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2018562999 ps |
| CPU time | 17.9 seconds |
| Started | Feb 08 02:06:47 PM UTC 25 |
| Finished | Feb 08 02:07:07 PM UTC 25 |
| Peak memory | 221220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089462079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3089462079 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.3664219509 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2012246128 ps |
| CPU time | 14.11 seconds |
| Started | Feb 08 02:06:40 PM UTC 25 |
| Finished | Feb 08 02:06:56 PM UTC 25 |
| Peak memory | 223276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664219509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3664219509 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.1489812393 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 839998090 ps |
| CPU time | 26.43 seconds |
| Started | Feb 08 02:06:42 PM UTC 25 |
| Finished | Feb 08 02:07:10 PM UTC 25 |
| Peak memory | 225380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489812393 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.1489812393 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.10522556 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 89213068 ps |
| CPU time | 5.85 seconds |
| Started | Feb 08 02:07:05 PM UTC 25 |
| Finished | Feb 08 02:07:12 PM UTC 25 |
| Peak memory | 221156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10522556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl _32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.10522556 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2818736230 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2899679974 ps |
| CPU time | 115.16 seconds |
| Started | Feb 08 02:07:01 PM UTC 25 |
| Finished | Feb 08 02:08:59 PM UTC 25 |
| Peak memory | 244140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818736230 -assert nopostproc +UVM_TESTNAME=rom_c trl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.2818736230 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.952509917 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 480811545 ps |
| CPU time | 14.99 seconds |
| Started | Feb 08 02:07:02 PM UTC 25 |
| Finished | Feb 08 02:07:18 PM UTC 25 |
| Peak memory | 223264 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952509917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.952509917 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.534871293 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 103181676 ps |
| CPU time | 6.45 seconds |
| Started | Feb 08 02:07:01 PM UTC 25 |
| Finished | Feb 08 02:07:09 PM UTC 25 |
| Peak memory | 221208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534871293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.534871293 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2662327490 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 411170188 ps |
| CPU time | 8.61 seconds |
| Started | Feb 08 02:06:55 PM UTC 25 |
| Finished | Feb 08 02:07:04 PM UTC 25 |
| Peak memory | 221228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662327490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ= rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2662327490 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3635928460 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 236556954 ps |
| CPU time | 17.52 seconds |
| Started | Feb 08 02:06:57 PM UTC 25 |
| Finished | Feb 08 02:07:16 PM UTC 25 |
| Peak memory | 223332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635928460 -assert n opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.3635928460 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.723369582 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 53434674865 ps |
| CPU time | 963.01 seconds |
| Started | Feb 08 02:07:05 PM UTC 25 |
| Finished | Feb 08 02:23:20 PM UTC 25 |
| Peak memory | 246184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom _ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=723369582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_ stress_all_with_rand_reset.723369582 |
| Directory | /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest |
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