Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 96.89 91.85 97.67 100.00 98.28 97.45 98.37


Total tests in report: 427
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
64.53 64.53 92.58 92.58 67.13 67.13 51.85 51.85 40.00 40.00 88.62 88.62 93.54 93.54 17.95 17.95 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.3311905353
75.44 10.91 92.58 0.00 72.33 5.20 87.67 35.83 73.33 33.33 89.66 1.03 93.84 0.30 18.65 0.70 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1495020021
83.23 7.79 92.94 0.36 78.93 6.60 88.58 0.90 73.33 0.00 91.72 2.07 95.35 1.50 61.77 43.12 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1385254275
88.22 4.99 96.29 3.35 85.39 6.46 95.55 6.97 86.67 13.33 94.14 2.41 95.65 0.30 63.87 2.10 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3472943142
90.49 2.26 96.29 0.00 85.39 0.00 95.55 0.00 86.67 0.00 94.14 0.00 95.65 0.00 79.72 15.85 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3040035426
92.58 2.09 96.41 0.12 85.53 0.14 95.55 0.00 100.00 13.33 94.48 0.34 95.65 0.00 80.42 0.70 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3802827253
93.59 1.01 96.65 0.24 86.24 0.70 95.55 0.00 100.00 0.00 95.52 1.03 95.65 0.00 85.55 5.13 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3501247363
94.60 1.00 96.65 0.00 89.75 3.51 96.75 1.20 100.00 0.00 96.21 0.69 95.65 0.00 87.18 1.63 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.785116412
95.25 0.65 96.65 0.00 90.03 0.28 97.05 0.30 100.00 0.00 96.21 0.00 95.65 0.00 91.14 3.96 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.3315584974
95.85 0.60 96.89 0.24 91.43 1.40 97.25 0.20 100.00 0.00 97.59 1.38 95.95 0.30 91.84 0.70 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.4029870248
96.18 0.33 96.89 0.00 91.43 0.00 97.25 0.00 100.00 0.00 97.59 0.00 95.95 0.00 94.17 2.33 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.3383595241
96.38 0.20 96.89 0.00 91.43 0.00 97.25 0.00 100.00 0.00 97.59 0.00 95.95 0.00 95.57 1.40 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3600238302
96.57 0.19 96.89 0.00 91.57 0.14 97.25 0.00 100.00 0.00 97.59 0.00 97.15 1.20 95.57 0.00 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3538910744
96.68 0.11 96.89 0.00 91.71 0.14 97.53 0.28 100.00 0.00 97.93 0.34 97.15 0.00 95.57 0.00 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.858374471
96.76 0.08 96.89 0.00 91.85 0.14 97.58 0.05 100.00 0.00 98.28 0.34 97.15 0.00 95.57 0.00 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.849222881
96.83 0.07 96.89 0.00 91.85 0.00 97.58 0.00 100.00 0.00 98.28 0.00 97.15 0.00 96.04 0.47 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1782282485
96.89 0.07 96.89 0.00 91.85 0.00 97.58 0.00 100.00 0.00 98.28 0.00 97.15 0.00 96.50 0.47 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1798246458
96.96 0.07 96.89 0.00 91.85 0.00 97.58 0.00 100.00 0.00 98.28 0.00 97.15 0.00 96.97 0.47 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1630121588
97.03 0.07 96.89 0.00 91.85 0.00 97.58 0.00 100.00 0.00 98.28 0.00 97.15 0.00 97.44 0.47 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.2942321007
97.09 0.07 96.89 0.00 91.85 0.00 97.58 0.00 100.00 0.00 98.28 0.00 97.15 0.00 97.90 0.47 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2131565277
97.13 0.03 96.89 0.00 91.85 0.00 97.58 0.00 100.00 0.00 98.28 0.00 97.15 0.00 98.14 0.23 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2153083419
97.16 0.03 96.89 0.00 91.85 0.00 97.58 0.00 100.00 0.00 98.28 0.00 97.15 0.00 98.37 0.23 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.4023781243
97.18 0.02 96.89 0.00 91.85 0.00 97.58 0.00 100.00 0.00 98.28 0.00 97.30 0.15 98.37 0.00 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2056937061
97.20 0.02 96.89 0.00 91.85 0.00 97.58 0.00 100.00 0.00 98.28 0.00 97.45 0.15 98.37 0.00 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.1360276403
97.22 0.01 96.89 0.00 91.85 0.00 97.67 0.10 100.00 0.00 98.28 0.00 97.45 0.00 98.37 0.00 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.3284561173

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3399011519
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1533466096
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2220365458
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2204689021
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3940490560
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.182671497
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2434586561
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2983930885
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.982430956
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3849868943
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2076348216
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2817794940
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.175532098
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.21049709
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2269183012
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4062934428
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1281795482
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.358065233
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3075096449
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2115107450
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2294939574
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.118294482
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1516608924
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.29390879
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3024168723
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.644499447
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.234664354
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3215250853
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2194113603
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1881595014
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2583065840
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3674207978
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1815413878
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.458904090
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2252120657
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.131060966
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2898893148
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3320305830
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1887042228
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2062187641
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1964131856
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3879151690
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2327832327
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2915212514
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3835663519
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2323177061
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3014994949
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3024072017
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4112337986
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.537087976
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2113434742
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.859567024
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1468642560
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1129418520
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1525288958
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2460754746
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3359691739
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.506317168
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.434593441
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4047517173
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4055186526
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2653183321
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2204642663
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4243696734
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3909370478
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2629979893
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3799989248
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1544627286
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3346591342
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2813706038
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1242207360
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3785601138
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.295874766
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.863622778
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.618676605
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3767388301
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.666992082
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3833757222
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.831907680
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.754150649
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2171958466
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2519295223
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1917821515
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1250748904
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3845285355
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.67644686
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2452610337
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1319755182
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2772635186
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3465350418
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.313117685
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1371521879
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1465631305
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3379090864
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3123306246
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4181210234
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1120223460
/workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4174084442
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Total test records in report: 427
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.4023781243 Feb 08 02:04:27 PM UTC 25 Feb 08 02:04:35 PM UTC 25 136498769 ps
T2 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.3311132336 Feb 08 02:04:35 PM UTC 25 Feb 08 02:04:43 PM UTC 25 97337838 ps
T3 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.3311905353 Feb 08 02:04:29 PM UTC 25 Feb 08 02:04:44 PM UTC 25 261657211 ps
T4 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.407497226 Feb 08 02:04:44 PM UTC 25 Feb 08 02:04:51 PM UTC 25 349897141 ps
T5 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.858374471 Feb 08 02:04:38 PM UTC 25 Feb 08 02:04:53 PM UTC 25 2390074825 ps
T6 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.467037163 Feb 08 02:04:45 PM UTC 25 Feb 08 02:04:55 PM UTC 25 144112493 ps
T7 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1160528851 Feb 08 02:04:46 PM UTC 25 Feb 08 02:04:58 PM UTC 25 557064899 ps
T8 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.1875605557 Feb 08 02:04:50 PM UTC 25 Feb 08 02:05:00 PM UTC 25 193504057 ps
T9 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.849222881 Feb 08 02:04:51 PM UTC 25 Feb 08 02:05:03 PM UTC 25 348414014 ps
T10 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3472943142 Feb 08 02:04:57 PM UTC 25 Feb 08 02:05:05 PM UTC 25 89262169 ps
T17 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.1239680806 Feb 08 02:04:57 PM UTC 25 Feb 08 02:05:07 PM UTC 25 271796444 ps
T18 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1876912228 Feb 08 02:05:01 PM UTC 25 Feb 08 02:05:11 PM UTC 25 191742751 ps
T27 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.4175482535 Feb 08 02:05:02 PM UTC 25 Feb 08 02:05:13 PM UTC 25 360966331 ps
T28 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.606521914 Feb 08 02:05:05 PM UTC 25 Feb 08 02:05:14 PM UTC 25 498718520 ps
T19 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.3501170459 Feb 08 02:04:58 PM UTC 25 Feb 08 02:05:15 PM UTC 25 787908713 ps
T14 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1194727468 Feb 08 02:05:06 PM UTC 25 Feb 08 02:05:16 PM UTC 25 291186179 ps
T20 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.3315584974 Feb 08 02:05:12 PM UTC 25 Feb 08 02:05:20 PM UTC 25 952982853 ps
T66 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1878294265 Feb 08 02:05:21 PM UTC 25 Feb 08 02:05:30 PM UTC 25 126790665 ps
T68 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.4015599790 Feb 08 02:05:23 PM UTC 25 Feb 08 02:05:32 PM UTC 25 374950771 ps
T16 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.2018873302 Feb 08 02:05:14 PM UTC 25 Feb 08 02:05:33 PM UTC 25 252612694 ps
T124 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.1114994135 Feb 08 02:05:31 PM UTC 25 Feb 08 02:05:40 PM UTC 25 634829397 ps
T15 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.785116412 Feb 08 02:05:08 PM UTC 25 Feb 08 02:05:40 PM UTC 25 3466332855 ps
T67 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3631397221 Feb 08 02:05:25 PM UTC 25 Feb 08 02:05:41 PM UTC 25 322229725 ps
T72 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2073183379 Feb 08 02:05:42 PM UTC 25 Feb 08 02:05:49 PM UTC 25 397108069 ps
T203 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.147724244 Feb 08 02:05:34 PM UTC 25 Feb 08 02:05:51 PM UTC 25 4992662980 ps
T83 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.421106976 Feb 08 02:05:50 PM UTC 25 Feb 08 02:05:59 PM UTC 25 366404983 ps
T24 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.17958393 Feb 08 02:05:04 PM UTC 25 Feb 08 02:06:01 PM UTC 25 270038064 ps
T34 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.3800552275 Feb 08 02:05:52 PM UTC 25 Feb 08 02:06:02 PM UTC 25 108087861 ps
T25 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.4029870248 Feb 08 02:04:43 PM UTC 25 Feb 08 02:06:08 PM UTC 25 297265088 ps
T35 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.711988719 Feb 08 02:06:02 PM UTC 25 Feb 08 02:06:10 PM UTC 25 85656204 ps
T36 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.3673614006 Feb 08 02:05:51 PM UTC 25 Feb 08 02:06:10 PM UTC 25 1024181984 ps
T26 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.1866211115 Feb 08 02:04:56 PM UTC 25 Feb 08 02:06:16 PM UTC 25 260928269 ps
T37 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.3597609139 Feb 08 02:06:00 PM UTC 25 Feb 08 02:06:18 PM UTC 25 999798957 ps
T38 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.289575168 Feb 08 02:06:10 PM UTC 25 Feb 08 02:06:20 PM UTC 25 202871924 ps
T39 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1055683325 Feb 08 02:06:08 PM UTC 25 Feb 08 02:06:21 PM UTC 25 510541421 ps
T40 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.3226882307 Feb 08 02:06:23 PM UTC 25 Feb 08 02:06:30 PM UTC 25 176350718 ps
T31 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1992039104 Feb 08 02:06:10 PM UTC 25 Feb 08 02:06:30 PM UTC 25 592665447 ps
T125 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.1194045866 Feb 08 02:06:31 PM UTC 25 Feb 08 02:06:39 PM UTC 25 97683141 ps
T143 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.2377710696 Feb 08 02:06:28 PM UTC 25 Feb 08 02:06:42 PM UTC 25 1024106713 ps
T29 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.841188458 Feb 08 02:06:19 PM UTC 25 Feb 08 02:06:44 PM UTC 25 981686301 ps
T185 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.2079236634 Feb 08 02:06:31 PM UTC 25 Feb 08 02:06:45 PM UTC 25 289956762 ps
T73 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2069169480 Feb 08 02:06:39 PM UTC 25 Feb 08 02:06:47 PM UTC 25 127444105 ps
T30 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.400617005 Feb 08 02:06:34 PM UTC 25 Feb 08 02:06:50 PM UTC 25 497664721 ps
T145 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.3040035426 Feb 08 02:06:44 PM UTC 25 Feb 08 02:06:54 PM UTC 25 142336371 ps
T84 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.3664219509 Feb 08 02:06:40 PM UTC 25 Feb 08 02:06:56 PM UTC 25 2012246128 ps
T21 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1495020021 Feb 08 02:04:50 PM UTC 25 Feb 08 02:07:00 PM UTC 25 10050429788 ps
T74 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3053032721 Feb 08 02:06:55 PM UTC 25 Feb 08 02:07:01 PM UTC 25 216846210 ps
T85 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2662327490 Feb 08 02:06:55 PM UTC 25 Feb 08 02:07:04 PM UTC 25 411170188 ps
T171 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3089462079 Feb 08 02:06:47 PM UTC 25 Feb 08 02:07:07 PM UTC 25 2018562999 ps
T144 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.534871293 Feb 08 02:07:01 PM UTC 25 Feb 08 02:07:09 PM UTC 25 103181676 ps
T86 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.1489812393 Feb 08 02:06:42 PM UTC 25 Feb 08 02:07:10 PM UTC 25 839998090 ps
T22 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2380134053 Feb 08 02:04:37 PM UTC 25 Feb 08 02:07:11 PM UTC 25 3193067484 ps
T75 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.10522556 Feb 08 02:07:05 PM UTC 25 Feb 08 02:07:12 PM UTC 25 89213068 ps
T43 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3635928460 Feb 08 02:06:57 PM UTC 25 Feb 08 02:07:16 PM UTC 25 236556954 ps
T204 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.952509917 Feb 08 02:07:02 PM UTC 25 Feb 08 02:07:18 PM UTC 25 480811545 ps
T146 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.2942321007 Feb 08 02:07:09 PM UTC 25 Feb 08 02:07:19 PM UTC 25 153900638 ps
T152 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.652128858 Feb 08 02:07:07 PM UTC 25 Feb 08 02:07:20 PM UTC 25 391639588 ps
T32 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.2717984059 Feb 08 02:05:17 PM UTC 25 Feb 08 02:07:23 PM UTC 25 384668943 ps
T45 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.917334171 Feb 08 02:07:11 PM UTC 25 Feb 08 02:07:24 PM UTC 25 1857224169 ps
T167 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.3013163126 Feb 08 02:07:17 PM UTC 25 Feb 08 02:07:28 PM UTC 25 1827940625 ps
T23 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1966789533 Feb 08 02:05:33 PM UTC 25 Feb 08 02:07:28 PM UTC 25 5359214020 ps
T87 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.4077050138 Feb 08 02:07:20 PM UTC 25 Feb 08 02:07:30 PM UTC 25 129731135 ps
T147 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.3296945420 Feb 08 02:07:20 PM UTC 25 Feb 08 02:07:31 PM UTC 25 138197832 ps
T205 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.741744297 Feb 08 02:07:29 PM UTC 25 Feb 08 02:07:36 PM UTC 25 395641609 ps
T149 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.3383595241 Feb 08 02:07:31 PM UTC 25 Feb 08 02:07:42 PM UTC 25 136917145 ps
T197 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.122511772 Feb 08 02:07:24 PM UTC 25 Feb 08 02:07:42 PM UTC 25 1658238587 ps
T199 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.2892180590 Feb 08 02:07:34 PM UTC 25 Feb 08 02:07:49 PM UTC 25 170299523 ps
T181 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.604961449 Feb 08 02:07:29 PM UTC 25 Feb 08 02:07:53 PM UTC 25 5880381717 ps
T206 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.3284561173 Feb 08 02:07:43 PM UTC 25 Feb 08 02:07:55 PM UTC 25 166053975 ps
T182 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3385284255 Feb 08 02:07:43 PM UTC 25 Feb 08 02:07:56 PM UTC 25 2239955937 ps
T148 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.1866613297 Feb 08 02:07:50 PM UTC 25 Feb 08 02:08:01 PM UTC 25 198321689 ps
T179 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.4165035760 Feb 08 02:08:02 PM UTC 25 Feb 08 02:08:10 PM UTC 25 128990022 ps
T33 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.903943895 Feb 08 02:05:42 PM UTC 25 Feb 08 02:08:10 PM UTC 25 195549483 ps
T207 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.1528739621 Feb 08 02:07:55 PM UTC 25 Feb 08 02:08:12 PM UTC 25 1081662309 ps
T208 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.4044293884 Feb 08 02:08:11 PM UTC 25 Feb 08 02:08:20 PM UTC 25 353366511 ps
T188 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.449034009 Feb 08 02:08:11 PM UTC 25 Feb 08 02:08:32 PM UTC 25 225757422 ps
T41 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3802827253 Feb 08 02:05:01 PM UTC 25 Feb 08 02:08:34 PM UTC 25 20553639407 ps
T209 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3568840746 Feb 08 02:07:21 PM UTC 25 Feb 08 02:08:36 PM UTC 25 1072971938 ps
T210 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.1335869562 Feb 08 02:08:21 PM UTC 25 Feb 08 02:08:38 PM UTC 25 715190483 ps
T211 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1489326140 Feb 08 02:08:35 PM UTC 25 Feb 08 02:08:44 PM UTC 25 500990753 ps
T180 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1885521435 Feb 08 02:07:32 PM UTC 25 Feb 08 02:08:46 PM UTC 25 1301567848 ps
T212 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.102722039 Feb 08 02:08:39 PM UTC 25 Feb 08 02:08:49 PM UTC 25 105000976 ps
T150 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.736111783 Feb 08 02:08:37 PM UTC 25 Feb 08 02:08:55 PM UTC 25 219959590 ps
T42 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2818736230 Feb 08 02:07:01 PM UTC 25 Feb 08 02:08:59 PM UTC 25 2899679974 ps
T168 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.495618460 Feb 08 02:07:11 PM UTC 25 Feb 08 02:08:59 PM UTC 25 1212045412 ps
T191 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.554483162 Feb 08 02:08:53 PM UTC 25 Feb 08 02:09:00 PM UTC 25 128882369 ps
T44 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.1371641706 Feb 08 02:08:47 PM UTC 25 Feb 08 02:09:03 PM UTC 25 994461402 ps
T213 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.796962820 Feb 08 02:08:59 PM UTC 25 Feb 08 02:09:08 PM UTC 25 537349424 ps
T47 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3162284083 Feb 08 02:06:33 PM UTC 25 Feb 08 02:09:09 PM UTC 25 19261534783 ps
T166 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3730863037 Feb 08 02:05:58 PM UTC 25 Feb 08 02:09:12 PM UTC 25 2954700847 ps
T214 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.3610873004 Feb 08 02:09:01 PM UTC 25 Feb 08 02:09:13 PM UTC 25 726390972 ps
T174 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.2496275326 Feb 08 02:09:09 PM UTC 25 Feb 08 02:09:16 PM UTC 25 348118479 ps
T215 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.3920074720 Feb 08 02:09:13 PM UTC 25 Feb 08 02:09:20 PM UTC 25 378065393 ps
T169 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1964051003 Feb 08 02:06:45 PM UTC 25 Feb 08 02:09:27 PM UTC 25 3746693046 ps
T157 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.1339183457 Feb 08 02:08:56 PM UTC 25 Feb 08 02:09:28 PM UTC 25 2255518080 ps
T46 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.1532938037 Feb 08 02:09:17 PM UTC 25 Feb 08 02:09:32 PM UTC 25 171787475 ps
T193 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.4033127456 Feb 08 02:09:27 PM UTC 25 Feb 08 02:09:34 PM UTC 25 297760132 ps
T216 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1197431903 Feb 08 02:06:16 PM UTC 25 Feb 08 02:09:35 PM UTC 25 3638434358 ps
T153 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.660817116 Feb 08 02:09:10 PM UTC 25 Feb 08 02:09:40 PM UTC 25 1761955166 ps
T217 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.3135055482 Feb 08 02:09:32 PM UTC 25 Feb 08 02:09:43 PM UTC 25 476539786 ps
T218 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.1488772693 Feb 08 02:09:28 PM UTC 25 Feb 08 02:09:49 PM UTC 25 2663153393 ps
T163 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2576511524 Feb 08 02:09:36 PM UTC 25 Feb 08 02:09:51 PM UTC 25 174380408 ps
T219 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.1304602230 Feb 08 02:09:43 PM UTC 25 Feb 08 02:09:52 PM UTC 25 735184394 ps
T220 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.3565606899 Feb 08 02:09:51 PM UTC 25 Feb 08 02:09:59 PM UTC 25 346618129 ps
T194 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.604403180 Feb 08 02:09:56 PM UTC 25 Feb 08 02:10:10 PM UTC 25 172804528 ps
T154 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.2131565277 Feb 08 02:09:50 PM UTC 25 Feb 08 02:10:11 PM UTC 25 2050947387 ps
T176 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3872912469 Feb 08 02:08:59 PM UTC 25 Feb 08 02:10:16 PM UTC 25 3831621946 ps
T200 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.2238231481 Feb 08 02:10:11 PM UTC 25 Feb 08 02:10:18 PM UTC 25 89257650 ps
T221 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.3402031660 Feb 08 02:10:17 PM UTC 25 Feb 08 02:10:27 PM UTC 25 558839330 ps
T222 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.1028308723 Feb 08 02:10:12 PM UTC 25 Feb 08 02:10:30 PM UTC 25 1128901312 ps
T186 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2786251867 Feb 08 02:07:54 PM UTC 25 Feb 08 02:10:44 PM UTC 25 3222488773 ps
T223 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.2667069649 Feb 08 02:10:28 PM UTC 25 Feb 08 02:10:48 PM UTC 25 2075777009 ps
T183 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.1625763666 Feb 08 02:10:45 PM UTC 25 Feb 08 02:10:53 PM UTC 25 130324497 ps
T164 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3044441682 Feb 08 02:08:13 PM UTC 25 Feb 08 02:11:04 PM UTC 25 2463085147 ps
T224 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.2749537519 Feb 08 02:10:54 PM UTC 25 Feb 08 02:11:05 PM UTC 25 273748499 ps
T155 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.3765283142 Feb 08 02:10:49 PM UTC 25 Feb 08 02:11:09 PM UTC 25 261112866 ps
T170 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.102694281 Feb 08 02:11:06 PM UTC 25 Feb 08 02:11:18 PM UTC 25 693296716 ps
T225 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4047608199 Feb 08 02:08:45 PM UTC 25 Feb 08 02:11:26 PM UTC 25 3917772119 ps
T187 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.3383695124 Feb 08 02:11:18 PM UTC 25 Feb 08 02:11:27 PM UTC 25 518131401 ps
T226 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2001255935 Feb 08 02:09:14 PM UTC 25 Feb 08 02:11:34 PM UTC 25 4161852494 ps
T227 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.1338354493 Feb 08 02:11:28 PM UTC 25 Feb 08 02:11:39 PM UTC 25 181432323 ps
T177 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.392373105 Feb 08 02:09:52 PM UTC 25 Feb 08 02:11:42 PM UTC 25 4930490925 ps
T159 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2591823296 Feb 08 02:11:27 PM UTC 25 Feb 08 02:11:47 PM UTC 25 176653695 ps
T165 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3271166622 Feb 08 02:09:35 PM UTC 25 Feb 08 02:11:47 PM UTC 25 1999637708 ps
T228 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.2871199150 Feb 08 02:11:48 PM UTC 25 Feb 08 02:11:56 PM UTC 25 172668760 ps
T178 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.2682114512 Feb 08 02:11:40 PM UTC 25 Feb 08 02:11:59 PM UTC 25 511063305 ps
T229 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.2926229629 Feb 08 02:11:53 PM UTC 25 Feb 08 02:12:04 PM UTC 25 540303889 ps
T230 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.524283586 Feb 08 02:11:48 PM UTC 25 Feb 08 02:12:06 PM UTC 25 213881558 ps
T158 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.3211936198 Feb 08 02:12:07 PM UTC 25 Feb 08 02:12:16 PM UTC 25 256631895 ps
T231 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.1179433402 Feb 08 02:11:59 PM UTC 25 Feb 08 02:12:16 PM UTC 25 288548430 ps
T232 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.70150878 Feb 08 02:12:17 PM UTC 25 Feb 08 02:12:26 PM UTC 25 545677652 ps
T233 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2668564057 Feb 08 02:12:16 PM UTC 25 Feb 08 02:12:30 PM UTC 25 364960949 ps
T198 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.2760488861 Feb 08 02:12:30 PM UTC 25 Feb 08 02:12:47 PM UTC 25 251952466 ps
T156 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3455487560 Feb 08 02:10:19 PM UTC 25 Feb 08 02:12:59 PM UTC 25 1902519622 ps
T234 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.4088201956 Feb 08 02:13:00 PM UTC 25 Feb 08 02:13:08 PM UTC 25 127147551 ps
T235 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.1566932529 Feb 08 02:13:09 PM UTC 25 Feb 08 02:13:28 PM UTC 25 297845302 ps
T236 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.178962915 Feb 08 02:13:26 PM UTC 25 Feb 08 02:13:36 PM UTC 25 179764838 ps
T237 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3224110721 Feb 08 02:11:57 PM UTC 25 Feb 08 02:13:45 PM UTC 25 25660134847 ps
T238 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.2665347329 Feb 08 02:13:29 PM UTC 25 Feb 08 02:13:45 PM UTC 25 507058213 ps
T184 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2132126070 Feb 08 02:11:05 PM UTC 25 Feb 08 02:13:53 PM UTC 25 5997480920 ps
T239 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.876894515 Feb 08 02:13:46 PM UTC 25 Feb 08 02:13:55 PM UTC 25 88886842 ps
T240 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.2771305609 Feb 08 02:13:54 PM UTC 25 Feb 08 02:14:08 PM UTC 25 521387198 ps
T105 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.1360276403 Feb 08 02:13:46 PM UTC 25 Feb 08 02:14:09 PM UTC 25 3989897898 ps
T106 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3964361113 Feb 08 02:12:26 PM UTC 25 Feb 08 02:14:20 PM UTC 25 3856699929 ps
T107 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.2548333275 Feb 08 02:14:21 PM UTC 25 Feb 08 02:14:26 PM UTC 25 598280497 ps
T108 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.3679789050 Feb 08 02:14:09 PM UTC 25 Feb 08 02:14:27 PM UTC 25 498238090 ps
T109 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.2285068909 Feb 08 02:14:28 PM UTC 25 Feb 08 02:14:37 PM UTC 25 2190255497 ps
T110 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.1771890101 Feb 08 02:14:27 PM UTC 25 Feb 08 02:14:41 PM UTC 25 307003733 ps
T111 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.4227137754 Feb 08 02:14:42 PM UTC 25 Feb 08 02:14:49 PM UTC 25 335578323 ps
T112 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.2808383994 Feb 08 02:14:38 PM UTC 25 Feb 08 02:14:50 PM UTC 25 178953761 ps
T113 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.305411669 Feb 08 02:14:50 PM UTC 25 Feb 08 02:15:00 PM UTC 25 278704826 ps
T114 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1030833945 Feb 08 02:11:35 PM UTC 25 Feb 08 02:15:05 PM UTC 25 5898359646 ps
T151 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.1661128720 Feb 08 02:14:50 PM UTC 25 Feb 08 02:15:12 PM UTC 25 1208511662 ps
T241 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3464783072 Feb 08 02:13:29 PM UTC 25 Feb 08 02:15:20 PM UTC 25 1747756307 ps
T242 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.581398637 Feb 08 02:15:06 PM UTC 25 Feb 08 02:15:23 PM UTC 25 471910531 ps
T243 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.2776951228 Feb 08 02:15:22 PM UTC 25 Feb 08 02:15:30 PM UTC 25 520000761 ps
T201 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.2457269284 Feb 08 02:15:24 PM UTC 25 Feb 08 02:15:39 PM UTC 25 164724510 ps
T244 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.716373916 Feb 08 02:15:31 PM UTC 25 Feb 08 02:15:43 PM UTC 25 486640115 ps
T245 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.1260419734 Feb 08 02:15:44 PM UTC 25 Feb 08 02:16:01 PM UTC 25 616140588 ps
T189 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2784758533 Feb 08 02:13:55 PM UTC 25 Feb 08 02:16:06 PM UTC 25 3156155613 ps
T196 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.952348008 Feb 08 02:16:07 PM UTC 25 Feb 08 02:16:15 PM UTC 25 131725716 ps
T246 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3636684257 Feb 08 02:16:16 PM UTC 25 Feb 08 02:16:32 PM UTC 25 159905803 ps
T247 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.1545233784 Feb 08 02:16:33 PM UTC 25 Feb 08 02:16:43 PM UTC 25 1840936310 ps
T173 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1283634338 Feb 08 02:14:38 PM UTC 25 Feb 08 02:17:10 PM UTC 25 16907196172 ps
T248 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.2483643750 Feb 08 02:17:11 PM UTC 25 Feb 08 02:17:26 PM UTC 25 979002852 ps
T192 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3097356649 Feb 08 02:16:44 PM UTC 25 Feb 08 02:17:56 PM UTC 25 937009224 ps
T249 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.1024392395 Feb 08 02:17:58 PM UTC 25 Feb 08 02:18:05 PM UTC 25 479587976 ps
T190 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.525042699 Feb 08 02:15:40 PM UTC 25 Feb 08 02:18:12 PM UTC 25 6902681176 ps
T250 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2617637199 Feb 08 02:15:00 PM UTC 25 Feb 08 02:18:19 PM UTC 25 9771368046 ps
T160 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.3275010840 Feb 08 02:18:07 PM UTC 25 Feb 08 02:18:23 PM UTC 25 1185821695 ps
T251 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.1533492598 Feb 08 02:18:12 PM UTC 25 Feb 08 02:18:26 PM UTC 25 8401017219 ps
T252 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.3467521013 Feb 08 02:18:29 PM UTC 25 Feb 08 02:18:37 PM UTC 25 87511572 ps
T253 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.4095297590 Feb 08 02:18:25 PM UTC 25 Feb 08 02:18:41 PM UTC 25 666840268 ps
T254 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.2208065307 Feb 08 02:18:42 PM UTC 25 Feb 08 02:18:50 PM UTC 25 395290231 ps
T172 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.1476557904 Feb 08 02:18:38 PM UTC 25 Feb 08 02:18:53 PM UTC 25 207920614 ps
T255 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.2695297878 Feb 08 02:18:54 PM UTC 25 Feb 08 02:19:12 PM UTC 25 990606066 ps
T161 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4115459267 Feb 08 02:18:20 PM UTC 25 Feb 08 02:19:56 PM UTC 25 1923393590 ps
T202 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.914560549 Feb 08 02:19:57 PM UTC 25 Feb 08 02:20:04 PM UTC 25 86230960 ps
T162 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.1353132283 Feb 08 02:20:05 PM UTC 25 Feb 08 02:20:24 PM UTC 25 247840205 ps
T256 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.1819790144 Feb 08 02:20:20 PM UTC 25 Feb 08 02:20:29 PM UTC 25 572784352 ps
T257 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.2434698469 Feb 08 02:20:30 PM UTC 25 Feb 08 02:20:44 PM UTC 25 1661518058 ps
T258 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4077154123 Feb 08 02:18:51 PM UTC 25 Feb 08 02:20:57 PM UTC 25 7130367179 ps
T175 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.56099956 Feb 08 02:20:58 PM UTC 25 Feb 08 02:21:06 PM UTC 25 131471710 ps
T259 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.777423288 Feb 08 02:21:07 PM UTC 25 Feb 08 02:21:25 PM UTC 25 215017903 ps
T260 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.4294420255 Feb 08 02:21:26 PM UTC 25 Feb 08 02:21:35 PM UTC 25 368263010 ps
T261 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.4043306563 Feb 08 02:21:59 PM UTC 25 Feb 08 02:22:10 PM UTC 25 639299668 ps
T195 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.1638243937 Feb 08 02:22:22 PM UTC 25 Feb 08 02:22:30 PM UTC 25 261689775 ps
T262 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.1106359580 Feb 08 02:22:32 PM UTC 25 Feb 08 02:22:42 PM UTC 25 138260549 ps
T263 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.472976187 Feb 08 02:22:31 PM UTC 25 Feb 08 02:22:45 PM UTC 25 1188460868 ps
T264 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.997801034 Feb 08 02:21:35 PM UTC 25 Feb 08 02:22:56 PM UTC 25 751094991 ps
T265 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.3493381933 Feb 08 02:22:45 PM UTC 25 Feb 08 02:23:02 PM UTC 25 169501394 ps
T266 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.2525568601 Feb 08 02:23:04 PM UTC 25 Feb 08 02:23:13 PM UTC 25 126316455 ps
T11 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.723369582 Feb 08 02:07:05 PM UTC 25 Feb 08 02:23:20 PM UTC 25 53434674865 ps
T12 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1385254275 Feb 08 02:05:16 PM UTC 25 Feb 08 02:23:20 PM UTC 25 96787275098 ps
T55 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1126576815 Feb 08 02:23:14 PM UTC 25 Feb 08 02:23:25 PM UTC 25 492008289 ps
T56 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.190385046 Feb 08 02:23:21 PM UTC 25 Feb 08 02:23:34 PM UTC 25 531658928 ps
T57 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.2250081387 Feb 08 02:23:26 PM UTC 25 Feb 08 02:23:45 PM UTC 25 260645596 ps
T58 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.1916529121 Feb 08 02:23:46 PM UTC 25 Feb 08 02:23:54 PM UTC 25 460083617 ps
T59 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2277925184 Feb 08 02:20:25 PM UTC 25 Feb 08 02:24:07 PM UTC 25 8835013115 ps
T60 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2912817973 Feb 08 02:23:55 PM UTC 25 Feb 08 02:24:07 PM UTC 25 691497787 ps
T61 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1236750234 Feb 08 02:22:42 PM UTC 25 Feb 08 02:24:10 PM UTC 25 971548187 ps
T62 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.2249930995 Feb 08 02:24:08 PM UTC 25 Feb 08 02:24:20 PM UTC 25 142365127 ps
T267 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2296183100 Feb 08 02:24:10 PM UTC 25 Feb 08 02:24:26 PM UTC 25 1087238580 ps
T268 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.1321021348 Feb 08 02:24:27 PM UTC 25 Feb 08 02:24:34 PM UTC 25 347690998 ps
T269 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.204352351 Feb 08 02:24:35 PM UTC 25 Feb 08 02:25:00 PM UTC 25 1272993022 ps
T270 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.3093263619 Feb 08 02:25:01 PM UTC 25 Feb 08 02:25:08 PM UTC 25 283336273 ps
T271 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1843720171 Feb 08 02:24:08 PM UTC 25 Feb 08 02:25:28 PM UTC 25 10781278613 ps
T272 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.3150243633 Feb 08 02:25:29 PM UTC 25 Feb 08 02:25:45 PM UTC 25 1041318322 ps
T273 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1179457759 Feb 08 02:23:21 PM UTC 25 Feb 08 02:25:56 PM UTC 25 11681918338 ps
T274 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.4063750431 Feb 08 02:25:57 PM UTC 25 Feb 08 02:26:04 PM UTC 25 309824686 ps
T275 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.4156616500 Feb 08 02:26:09 PM UTC 25 Feb 08 02:26:19 PM UTC 25 140730031 ps
T276 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.3299775098 Feb 08 02:26:05 PM UTC 25 Feb 08 02:26:27 PM UTC 25 411246551 ps
T277 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.3435820284 Feb 08 02:26:27 PM UTC 25 Feb 08 02:26:41 PM UTC 25 1660211770 ps
T278 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.792304401 Feb 08 02:26:58 PM UTC 25 Feb 08 02:27:10 PM UTC 25 504150127 ps
T279 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.415238641 Feb 08 02:25:10 PM UTC 25 Feb 08 02:27:25 PM UTC 25 3425053842 ps
T280 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.2759048821 Feb 08 02:27:11 PM UTC 25 Feb 08 02:27:31 PM UTC 25 202255192 ps
T281 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3950229182 Feb 08 02:27:26 PM UTC 25 Feb 08 02:27:35 PM UTC 25 96442148 ps
T13 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1118125715 Feb 08 02:14:09 PM UTC 25 Feb 08 02:27:45 PM UTC 25 19493748564 ps
T282 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.1540226854 Feb 08 02:27:36 PM UTC 25 Feb 08 02:27:50 PM UTC 25 615348508 ps
T283 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.676689927 Feb 08 02:27:51 PM UTC 25 Feb 08 02:27:57 PM UTC 25 129098716 ps
T284 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.756915677 Feb 08 02:26:20 PM UTC 25 Feb 08 02:28:06 PM UTC 25 5713169954 ps
T285 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.1820289979 Feb 08 02:28:07 PM UTC 25 Feb 08 02:28:16 PM UTC 25 533279884 ps
T286 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.4190766225 Feb 08 02:27:58 PM UTC 25 Feb 08 02:28:21 PM UTC 25 1208561197 ps
T287 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2771853164 Feb 08 02:28:22 PM UTC 25 Feb 08 02:28:37 PM UTC 25 508363328 ps
T288 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3609491037 Feb 08 02:27:32 PM UTC 25 Feb 08 02:28:58 PM UTC 25 6183519904 ps
T289 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.417050783 Feb 08 02:28:59 PM UTC 25 Feb 08 02:29:14 PM UTC 25 513237898 ps
T290 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.1795059859 Feb 08 02:29:14 PM UTC 25 Feb 08 02:29:38 PM UTC 25 292052473 ps
T291 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.4103497709 Feb 08 02:29:39 PM UTC 25 Feb 08 02:29:48 PM UTC 25 492494319 ps
T292 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.753418366 Feb 08 02:28:17 PM UTC 25 Feb 08 02:30:04 PM UTC 25 1661863840 ps
T293 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1650715146 Feb 08 02:30:05 PM UTC 25 Feb 08 02:30:20 PM UTC 25 698384145 ps
T294 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.249605026 Feb 08 02:30:30 PM UTC 25 Feb 08 02:30:37 PM UTC 25 350029536 ps
T48 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.384195868 Feb 08 02:09:21 PM UTC 25 Feb 08 02:30:53 PM UTC 25 29520589801 ps
T295 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.2709342464 Feb 08 02:30:54 PM UTC 25 Feb 08 02:31:06 PM UTC 25 543774735 ps
T296 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3390799179 Feb 08 02:30:38 PM UTC 25 Feb 08 02:31:07 PM UTC 25 676873033 ps
T297 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.3992853138 Feb 08 02:31:08 PM UTC 25 Feb 08 02:31:27 PM UTC 25 1556155087 ps
T298 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.1261605712 Feb 08 02:31:28 PM UTC 25 Feb 08 02:31:46 PM UTC 25 133940339 ps
T299 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.2684225926 Feb 08 02:31:49 PM UTC 25 Feb 08 02:32:13 PM UTC 25 306915077 ps
T300 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.269056448 Feb 08 02:32:14 PM UTC 25 Feb 08 02:32:26 PM UTC 25 138237705 ps
T301 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.1795330213 Feb 08 02:32:34 PM UTC 25 Feb 08 02:32:51 PM UTC 25 169991174 ps
T302 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.3211668032 Feb 08 02:33:20 PM UTC 25 Feb 08 02:33:28 PM UTC 25 86751565 ps
T303 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.311130669 Feb 08 02:31:07 PM UTC 25 Feb 08 02:33:44 PM UTC 25 2794881885 ps
T304 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.3345757997 Feb 08 02:33:29 PM UTC 25 Feb 08 02:33:52 PM UTC 25 797733913 ps
T305 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.861329506 Feb 08 02:33:45 PM UTC 25 Feb 08 02:33:54 PM UTC 25 99331986 ps
T306 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3669195165 Feb 08 02:29:49 PM UTC 25 Feb 08 02:34:01 PM UTC 25 3780996315 ps
T307 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.2260461983 Feb 08 02:33:55 PM UTC 25 Feb 08 02:34:17 PM UTC 25 1036382146 ps
T308 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.2850713850 Feb 08 02:34:18 PM UTC 25 Feb 08 02:34:26 PM UTC 25 132527519 ps
T309 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.1049302043 Feb 08 02:34:27 PM UTC 25 Feb 08 02:34:43 PM UTC 25 350643003 ps
T310 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1437394919 Feb 08 02:32:28 PM UTC 25 Feb 08 02:34:47 PM UTC 25 3817508347 ps
T311 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.466491203 Feb 08 02:34:44 PM UTC 25 Feb 08 02:34:54 PM UTC 25 544856023 ps
T312 /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.2875785176 Feb 08 02:34:54 PM UTC 25 Feb 08 02:35:12 PM UTC 25 998066971 ps
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