Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 48926 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 936042 1 T1 9 T2 9 T3 7



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 265159 1 T1 9 T2 85 T3 70
values[0x0] 353505 1 T16 47818 T17 11257 T18 51338
values[0x1] 366304 1 T16 49002 T17 11674 T18 53278



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 24630 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 960338 1 T1 9 T2 52 T3 46



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 4025 1 T5 2 T79 1 T133 12
valid_sources[0x01] 3850 1 T13 5 T80 4 T133 3
valid_sources[0x02] 3695 1 T2 4 T7 8 T12 9
valid_sources[0x03] 3721 1 T7 1 T13 1 T134 4
valid_sources[0x04] 3680 1 T2 1 T7 1 T12 1
valid_sources[0x05] 3653 1 T2 1 T5 1 T12 3
valid_sources[0x06] 3796 1 T13 2 T14 2 T117 4
valid_sources[0x07] 3674 1 T2 2 T3 21 T7 1
valid_sources[0x08] 3645 1 T2 2 T11 1 T50 1
valid_sources[0x09] 3686 1 T2 1 T7 1 T13 4
valid_sources[0x0a] 4056 1 T5 1 T7 4 T14 10
valid_sources[0x0b] 3949 1 T7 5 T13 3 T117 2
valid_sources[0x0c] 3473 1 T5 1 T14 2 T117 4
valid_sources[0x0d] 3637 1 T5 1 T12 4 T117 1
valid_sources[0x0e] 3409 1 T7 8 T12 1 T13 3
valid_sources[0x0f] 3514 1 T7 1 T12 1 T13 2
valid_sources[0x10] 3608 1 T2 1 T13 2 T75 1
valid_sources[0x11] 4017 1 T7 1 T13 3 T133 2
valid_sources[0x12] 4346 1 T2 2 T12 7 T13 2
valid_sources[0x13] 3880 1 T2 1 T5 1 T12 1
valid_sources[0x14] 3551 1 T7 18 T12 1 T14 1
valid_sources[0x15] 3601 1 T5 1 T13 4 T11 2
valid_sources[0x16] 5106 1 T7 1 T13 1 T133 2
valid_sources[0x17] 4138 1 T2 2 T5 3 T7 1
valid_sources[0x18] 3766 1 T117 2 T11 1 T133 8
valid_sources[0x19] 3649 1 T13 1 T79 1 T25 3
valid_sources[0x1a] 3588 1 T2 3 T7 3 T12 7
valid_sources[0x1b] 3674 1 T12 1 T14 1 T79 2
valid_sources[0x1c] 3809 1 T5 1 T7 3 T12 1
valid_sources[0x1d] 3670 1 T13 1 T14 1 T117 1
valid_sources[0x1e] 3827 1 T7 4 T13 1 T133 4
valid_sources[0x1f] 3571 1 T2 2 T13 3 T50 4
valid_sources[0x20] 3433 1 T12 1 T13 5 T14 5
valid_sources[0x21] 3735 1 T2 1 T7 1 T13 2
valid_sources[0x22] 4248 1 T5 1 T14 10 T133 2
valid_sources[0x23] 3543 1 T2 2 T7 1 T14 2
valid_sources[0x24] 3647 1 T5 1 T7 2 T13 1
valid_sources[0x25] 3506 1 T5 1 T7 2 T13 1
valid_sources[0x26] 3665 1 T6 94 T13 5 T117 2
valid_sources[0x27] 3674 1 T117 1 T79 1 T50 3
valid_sources[0x28] 3677 1 T1 1 T7 2 T117 1
valid_sources[0x29] 3742 1 T7 4 T12 5 T13 1
valid_sources[0x2a] 4047 1 T14 8 T133 2 T40 1
valid_sources[0x2b] 3923 1 T7 3 T14 2 T117 2
valid_sources[0x2c] 3547 1 T12 2 T13 3 T93 5
valid_sources[0x2d] 3644 1 T2 1 T13 1 T117 1
valid_sources[0x2e] 3707 1 T14 2 T50 1 T74 15
valid_sources[0x2f] 3531 1 T5 2 T7 5 T13 2
valid_sources[0x30] 4402 1 T5 1 T12 1 T13 1
valid_sources[0x31] 3938 1 T5 3 T13 1 T133 4
valid_sources[0x32] 4164 1 T6 23 T12 1 T13 1
valid_sources[0x33] 4759 1 T117 1 T79 1 T133 4
valid_sources[0x34] 3499 1 T13 3 T75 2 T37 2
valid_sources[0x35] 3891 1 T7 7 T13 1 T11 1
valid_sources[0x36] 3858 1 T7 6 T12 3 T13 2
valid_sources[0x37] 4349 1 T4 1 T13 1 T133 3
valid_sources[0x38] 3835 1 T7 5 T12 1 T13 4
valid_sources[0x39] 3699 1 T2 1 T7 2 T12 4
valid_sources[0x3a] 3770 1 T7 9 T13 1 T117 1
valid_sources[0x3b] 3678 1 T2 2 T12 1 T117 1
valid_sources[0x3c] 3461 1 T13 4 T133 1 T135 5
valid_sources[0x3d] 3762 1 T2 1 T79 1 T133 8
valid_sources[0x3e] 4041 1 T13 6 T14 2 T117 1
valid_sources[0x3f] 3558 1 T13 2 T133 4 T38 1
valid_sources[0x40] 3676 1 T7 10 T13 2 T117 1
valid_sources[0x41] 3685 1 T133 2 T75 3 T40 3
valid_sources[0x42] 3575 1 T12 4 T13 4 T117 2
valid_sources[0x43] 3713 1 T7 1 T14 2 T117 2
valid_sources[0x44] 3829 1 T7 1 T12 4 T13 4
valid_sources[0x45] 3867 1 T3 35 T13 5 T14 4
valid_sources[0x46] 3592 1 T13 2 T117 1 T79 1
valid_sources[0x47] 4119 1 T13 1 T117 2 T79 2
valid_sources[0x48] 4646 1 T11 1 T133 5 T74 1
valid_sources[0x49] 3785 1 T2 4 T5 1 T14 5
valid_sources[0x4a] 3526 1 T7 2 T12 2 T13 1
valid_sources[0x4b] 3669 1 T2 1 T7 4 T12 2
valid_sources[0x4c] 3721 1 T12 1 T14 14 T133 1
valid_sources[0x4d] 4165 1 T2 2 T13 1 T14 7
valid_sources[0x4e] 4235 1 T2 1 T12 1 T13 2
valid_sources[0x4f] 3625 1 T7 10 T12 3 T13 1
valid_sources[0x50] 3517 1 T7 4 T12 1 T13 1
valid_sources[0x51] 4077 1 T12 4 T13 2 T11 2
valid_sources[0x52] 5110 1 T2 2 T12 1 T13 4
valid_sources[0x53] 3651 1 T7 2 T12 3 T13 3
valid_sources[0x54] 3672 1 T5 1 T13 3 T11 5
valid_sources[0x55] 3784 1 T13 3 T14 3 T117 10
valid_sources[0x56] 4392 1 T5 1 T7 1 T14 1
valid_sources[0x57] 4248 1 T7 7 T13 3 T117 2
valid_sources[0x58] 3846 1 T117 1 T75 3 T37 1
valid_sources[0x59] 4002 1 T4 1 T7 1 T117 3
valid_sources[0x5a] 3766 1 T117 2 T79 1 T37 1
valid_sources[0x5b] 3982 1 T2 1 T13 1 T117 1
valid_sources[0x5c] 3746 1 T7 6 T13 2 T40 1
valid_sources[0x5d] 3974 1 T12 1 T13 1 T117 1
valid_sources[0x5e] 3676 1 T2 2 T7 3 T14 6
valid_sources[0x5f] 3774 1 T2 4 T13 6 T14 5
valid_sources[0x60] 3730 1 T13 3 T14 4 T117 5
valid_sources[0x61] 3682 1 T13 1 T117 3 T133 3
valid_sources[0x62] 3778 1 T7 2 T12 2 T13 2
valid_sources[0x63] 3637 1 T7 2 T13 1 T75 1
valid_sources[0x64] 3563 1 T6 15 T7 1 T13 2
valid_sources[0x65] 3765 1 T7 4 T13 3 T79 1
valid_sources[0x66] 3783 1 T2 3 T4 2 T12 1
valid_sources[0x67] 3834 1 T7 1 T12 1 T14 1
valid_sources[0x68] 3643 1 T5 3 T12 4 T13 1
valid_sources[0x69] 3599 1 T5 1 T6 37 T7 7
valid_sources[0x6a] 3594 1 T12 1 T117 3 T11 1
valid_sources[0x6b] 4712 1 T7 5 T13 1 T11 1
valid_sources[0x6c] 4060 1 T7 4 T13 2 T11 2
valid_sources[0x6d] 3827 1 T5 1 T7 1 T133 3
valid_sources[0x6e] 3599 1 T5 1 T13 1 T117 4
valid_sources[0x6f] 3525 1 T7 3 T13 2 T14 20
valid_sources[0x70] 3469 1 T13 4 T14 4 T117 5
valid_sources[0x71] 3722 1 T7 3 T12 1 T117 3
valid_sources[0x72] 3470 1 T12 3 T79 1 T74 10
valid_sources[0x73] 3726 1 T4 10 T14 1 T117 3
valid_sources[0x74] 3781 1 T12 2 T14 2 T117 7
valid_sources[0x75] 4300 1 T133 1 T75 2 T37 3
valid_sources[0x76] 4074 1 T4 4 T12 1 T13 1
valid_sources[0x77] 3818 1 T4 1 T5 1 T13 1
valid_sources[0x78] 3833 1 T12 2 T13 2 T134 1
valid_sources[0x79] 3933 1 T2 2 T5 5 T12 2
valid_sources[0x7a] 4640 1 T1 1 T14 9 T117 8
valid_sources[0x7b] 3825 1 T5 1 T12 1 T93 10
valid_sources[0x7c] 3871 1 T5 1 T7 1 T12 2
valid_sources[0x7d] 3639 1 T133 2 T93 11 T37 2
valid_sources[0x7e] 3473 1 T5 4 T13 5 T37 1
valid_sources[0x7f] 3569 1 T2 1 T12 5 T13 1
valid_sources[0x80] 4039 1 T5 1 T12 3 T13 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 235628 1 T1 9 T2 9 T3 7
values[0x0] all_enables biggest_size 350353 1 T16 47373 T17 11171 T18 50910
values[0x1] all_enables biggest_size 350061 1 T16 46902 T17 11139 T18 51048


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 73489 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 716934 1 T1 9 T2 13 T3 12



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 199554 1 T1 23 T2 32 T3 32
values[0x0] 273958 1 T8 5 T9 6 T10 5
values[0x1] 316911 1 T9 3 T10 7 T46 4



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 33913 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 756510 1 T1 10 T2 15 T3 19



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2686 1 T11 1 T79 1 T80 5
valid_sources[0x01] 3226 1 T9 1 T29 1 T42 1
valid_sources[0x02] 3051 1 T1 2 T6 2 T135 1
valid_sources[0x03] 3736 1 T6 2 T10 1 T51 2
valid_sources[0x04] 3435 1 T6 1 T42 1 T136 1
valid_sources[0x05] 4062 1 T79 2 T93 1 T137 1
valid_sources[0x06] 4136 1 T6 1 T28 1 T42 1
valid_sources[0x07] 2855 1 T28 1 T39 1 T96 1
valid_sources[0x08] 2601 1 T37 2 T39 1 T49 2
valid_sources[0x09] 3064 1 T10 1 T37 1 T42 1
valid_sources[0x0a] 3440 1 T12 3 T79 1 T50 1
valid_sources[0x0b] 3219 1 T5 1 T135 1 T94 1
valid_sources[0x0c] 3483 1 T55 2 T42 1 T94 1
valid_sources[0x0d] 4146 1 T12 8 T55 1 T94 1
valid_sources[0x0e] 2389 1 T6 1 T9 1 T50 1
valid_sources[0x0f] 3231 1 T39 1 T42 1 T94 2
valid_sources[0x10] 3256 1 T135 1 T138 2 T49 1
valid_sources[0x11] 3196 1 T50 1 T27 2 T93 1
valid_sources[0x12] 2860 1 T37 2 T42 1 T16 658
valid_sources[0x13] 2709 1 T5 1 T16 235 T17 173
valid_sources[0x14] 3035 1 T27 1 T139 1 T16 270
valid_sources[0x15] 3413 1 T42 1 T96 1 T140 1
valid_sources[0x16] 3564 1 T81 2 T50 1 T38 14
valid_sources[0x17] 3265 1 T6 1 T12 1 T16 612
valid_sources[0x18] 2155 1 T6 1 T135 2 T31 1
valid_sources[0x19] 2423 1 T141 1 T135 1 T39 1
valid_sources[0x1a] 2931 1 T5 2 T37 1 T16 346
valid_sources[0x1b] 2532 1 T11 1 T37 1 T138 1
valid_sources[0x1c] 3453 1 T1 1 T6 1 T12 16
valid_sources[0x1d] 3765 1 T26 1 T31 1 T142 1
valid_sources[0x1e] 3089 1 T12 2 T51 2 T139 1
valid_sources[0x1f] 4046 1 T141 1 T28 1 T39 1
valid_sources[0x20] 2593 1 T39 1 T48 4 T143 1
valid_sources[0x21] 3407 1 T29 1 T37 1 T42 1
valid_sources[0x22] 2742 1 T5 1 T12 1 T42 1
valid_sources[0x23] 2567 1 T134 3 T26 2 T39 1
valid_sources[0x24] 2940 1 T5 2 T6 1 T79 1
valid_sources[0x25] 4178 1 T5 1 T11 1 T83 8
valid_sources[0x26] 2907 1 T27 2 T135 1 T95 7
valid_sources[0x27] 3082 1 T1 1 T6 2 T26 1
valid_sources[0x28] 3054 1 T93 2 T39 1 T47 33
valid_sources[0x29] 2432 1 T6 1 T12 2 T93 1
valid_sources[0x2a] 3018 1 T1 1 T8 1 T79 5
valid_sources[0x2b] 2804 1 T79 2 T26 3 T39 1
valid_sources[0x2c] 4292 1 T6 1 T12 7 T37 2
valid_sources[0x2d] 2894 1 T96 1 T144 2 T16 434
valid_sources[0x2e] 4170 1 T6 1 T134 1 T31 2
valid_sources[0x2f] 2407 1 T6 1 T134 1 T50 1
valid_sources[0x30] 2661 1 T93 1 T39 1 T42 1
valid_sources[0x31] 2024 1 T15 1 T53 3 T136 1
valid_sources[0x32] 2867 1 T6 1 T29 1 T137 1
valid_sources[0x33] 2650 1 T93 2 T37 2 T42 1
valid_sources[0x34] 2858 1 T6 1 T12 10 T55 1
valid_sources[0x35] 3759 1 T6 1 T141 1 T93 1
valid_sources[0x36] 2270 1 T6 1 T50 1 T136 1
valid_sources[0x37] 3075 1 T26 1 T96 1 T49 1
valid_sources[0x38] 2167 1 T29 1 T37 1 T16 112
valid_sources[0x39] 3191 1 T25 19 T145 1 T144 4
valid_sources[0x3a] 3942 1 T6 1 T26 1 T50 1
valid_sources[0x3b] 2444 1 T51 1 T39 1 T94 2
valid_sources[0x3c] 2707 1 T96 1 T49 1 T146 3
valid_sources[0x3d] 3224 1 T6 2 T50 1 T135 2
valid_sources[0x3e] 2957 1 T50 1 T93 1 T37 1
valid_sources[0x3f] 2911 1 T81 3 T79 1 T39 1
valid_sources[0x40] 2843 1 T147 1 T16 244 T17 69
valid_sources[0x41] 3483 1 T135 1 T147 3 T16 344
valid_sources[0x42] 3576 1 T6 1 T28 1 T42 1
valid_sources[0x43] 3428 1 T93 1 T142 1 T29 1
valid_sources[0x44] 3001 1 T6 1 T11 1 T26 2
valid_sources[0x45] 3487 1 T146 2 T139 1 T16 550
valid_sources[0x46] 3181 1 T39 1 T136 1 T16 570
valid_sources[0x47] 3431 1 T1 1 T135 1 T37 1
valid_sources[0x48] 2974 1 T79 1 T29 1 T94 1
valid_sources[0x49] 3523 1 T5 1 T6 1 T94 1
valid_sources[0x4a] 2455 1 T39 3 T42 1 T96 1
valid_sources[0x4b] 2303 1 T9 1 T80 1 T31 1
valid_sources[0x4c] 3357 1 T11 2 T79 2 T93 1
valid_sources[0x4d] 3561 1 T42 1 T137 1 T136 1
valid_sources[0x4e] 2455 1 T12 1 T11 1 T95 3
valid_sources[0x4f] 4137 1 T50 1 T95 1 T96 1
valid_sources[0x50] 3449 1 T6 1 T12 1 T27 1
valid_sources[0x51] 2930 1 T93 2 T96 1 T148 1
valid_sources[0x52] 3251 1 T134 1 T39 1 T95 6
valid_sources[0x53] 2507 1 T12 1 T39 2 T136 1
valid_sources[0x54] 3888 1 T1 1 T93 1 T29 1
valid_sources[0x55] 3157 1 T6 1 T10 1 T27 3
valid_sources[0x56] 3256 1 T37 1 T42 1 T48 2
valid_sources[0x57] 3951 1 T93 1 T29 1 T42 1
valid_sources[0x58] 3499 1 T6 1 T10 2 T12 4
valid_sources[0x59] 3595 1 T6 1 T26 2 T137 1
valid_sources[0x5a] 3384 1 T6 2 T8 2 T141 1
valid_sources[0x5b] 2576 1 T50 1 T27 1 T39 1
valid_sources[0x5c] 3347 1 T1 1 T6 1 T50 1
valid_sources[0x5d] 3834 1 T79 4 T149 1 T146 1
valid_sources[0x5e] 3319 1 T81 5 T42 1 T16 989
valid_sources[0x5f] 2456 1 T11 1 T42 1 T136 1
valid_sources[0x60] 3614 1 T2 32 T10 1 T79 1
valid_sources[0x61] 2105 1 T11 1 T141 1 T29 1
valid_sources[0x62] 2788 1 T53 2 T135 1 T95 2
valid_sources[0x63] 2442 1 T31 1 T93 1 T29 1
valid_sources[0x64] 3603 1 T26 1 T27 1 T142 2
valid_sources[0x65] 2810 1 T141 1 T37 2 T39 1
valid_sources[0x66] 2592 1 T6 2 T28 1 T96 1
valid_sources[0x67] 3211 1 T6 2 T12 1 T94 1
valid_sources[0x68] 3046 1 T6 2 T11 1 T39 1
valid_sources[0x69] 3544 1 T84 5 T27 1 T37 2
valid_sources[0x6a] 2084 1 T135 2 T37 1 T42 2
valid_sources[0x6b] 3516 1 T1 1 T12 1 T37 2
valid_sources[0x6c] 2875 1 T27 2 T16 311 T17 68
valid_sources[0x6d] 3135 1 T6 2 T135 1 T37 1
valid_sources[0x6e] 2661 1 T1 1 T12 2 T141 1
valid_sources[0x6f] 3316 1 T55 5 T37 2 T148 2
valid_sources[0x70] 3204 1 T28 1 T137 1 T95 8
valid_sources[0x71] 2390 1 T26 1 T27 1 T55 3
valid_sources[0x72] 2883 1 T5 1 T6 1 T11 1
valid_sources[0x73] 3390 1 T93 1 T29 1 T39 1
valid_sources[0x74] 3016 1 T26 1 T39 1 T95 2
valid_sources[0x75] 2321 1 T1 1 T80 1 T29 1
valid_sources[0x76] 3353 1 T93 1 T137 2 T96 1
valid_sources[0x77] 2720 1 T50 2 T135 1 T147 1
valid_sources[0x78] 2874 1 T1 1 T11 1 T50 1
valid_sources[0x79] 3315 1 T12 5 T51 3 T142 1
valid_sources[0x7a] 2469 1 T29 1 T146 4 T16 278
valid_sources[0x7b] 3887 1 T46 8 T39 1 T42 1
valid_sources[0x7c] 3419 1 T50 1 T27 1 T37 1
valid_sources[0x7d] 3849 1 T42 1 T150 2 T149 1
valid_sources[0x7e] 3067 1 T39 1 T151 7 T16 559
valid_sources[0x7f] 3171 1 T5 2 T6 2 T44 32
valid_sources[0x80] 2248 1 T5 2 T6 4 T80 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 181416 1 T1 9 T2 13 T3 12
values[0x0] all_enables biggest_size 268143 1 T8 1 T9 2 T10 2
values[0x1] all_enables biggest_size 267375 1 T10 1 T46 1 T82 2

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