Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1740312

1

T2

76

T3

63

T4

59

full_word

1094251

1

T1

6

T2

9

T3

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2834283	1			T1	6		T2	85		T3	70
auto[TlIntgErrCmd]	81	1			T72	6		T73	2		T118	2
auto[TlIntgErrData]	103	1			T71	5		T72	10		T73	4
auto[TlIntgErrBoth]	96	1			T71	5		T72	4		T73	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

456774

1

T1

6

T2

85

T3

70

auto[1]

2377789

1

T16

324793

T17

73377

T18

336095

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	198114	1			T2	76		T3	63		T4	59
auto[TlIntgErrNone]	partial	auto[1]	1541940	1			T16	211957		T17	46970		T18	215102
auto[TlIntgErrNone]	full_word	auto[0]	258519	1			T1	6		T2	9		T3	7
auto[TlIntgErrNone]	full_word	auto[1]	835710	1			T16	112836		T17	26407		T18	120993
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T72	1		T73	1		T118	2
auto[TlIntgErrCmd]	partial	auto[1]	36	1			T72	4		T125	3		T128	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T73	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T72	1		T129	1		-	-
auto[TlIntgErrData]	partial	auto[0]	52	1			T71	2		T72	4		T73	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T71	2		T72	4		T73	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T71	1		T72	1		T130	2
auto[TlIntgErrData]	full_word	auto[1]	3	1			T72	1		T131	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T71	3		T72	2		T73	1
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T71	2		T72	1		T73	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T72	1		T118	1		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T73	1		T129	2		T121	2