ROM_CTRL/64KB Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.334m	8.172ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	35.190s	9.436ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	32.300s	8.679ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	29.660s	3.585ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	27.330s	7.669ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	30.450s	4.699ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	32.300s	8.679ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.330s	7.669ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	30.440s	16.025ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	31.760s	8.058ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	33.380s	16.020ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.497m	26.976ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.199m	169.800ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	33.140s	59.726ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	38.580s	14.845ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	38.580s	14.845ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	35.190s	9.436ms	5	5	100.00
		rom_ctrl_csr_rw	32.300s	8.679ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.330s	7.669ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	31.750s	15.942ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	35.190s	9.436ms	5	5	100.00
		rom_ctrl_csr_rw	32.300s	8.679ms	20	20	100.00
		rom_ctrl_csr_aliasing	27.330s	7.669ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	31.750s	15.942ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	13.891m	83.902ms	48	50	96.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.209m	147.657ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.133m	17.243ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.935m	4.104ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.133m	17.243ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.891m	83.902ms	48	50	96.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.891m	83.902ms	48	50	96.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	13.891m	83.902ms	48	50	96.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.891m	83.902ms	48	50	96.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.891m	83.902ms	48	50	96.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.133m	17.243ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.133m	17.243ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.334m	8.172ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.334m	8.172ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.334m	8.172ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.935m	4.104ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	13.891m	83.902ms	48	50	96.00
		rom_ctrl_kmac_err_chk	1.199m	169.800ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	13.891m	83.902ms	48	50	96.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.891m	83.902ms	48	50	96.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	13.891m	83.902ms	48	50	96.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.209m	147.657ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.133m	17.243ms	5	5	100.00
V2S		TOTAL			93	95	97.89
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.708h	138.210ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			457	500	91.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.48	96.97	92.87	97.88	100.00	98.37	97.89	98.37

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.22335713061116954538939493248083273276313214858940810557274257434092352805867
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 107046438 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 107046438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.rom_ctrl_stress_all_with_rand_reset.29431024142057659693086512885355799602288718548996183646216332357315175303730
      Line 331, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26924699880 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 26924699880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 9 failures.

    • 6.rom_ctrl_stress_all_with_rand_reset.8147084003098665454250364176533016931415446140283983999716104027375625031460
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:106429f1-13e4-43bb-8224-3f2e83ebbf60
      

    • 7.rom_ctrl_stress_all_with_rand_reset.42000279749773936454792505791103018052191691309547677310681532960703156075112
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:480249f2-e561-49be-ac2c-1b0a55a0189f
      

    • ... and 7 more failures.

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 6 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 6 failures.

    • 1.rom_ctrl_stress_all_with_rand_reset.23436431263027137578818021315625294946792574450652240848012758897919931745866
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10011386324 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x6a0a7b0b
        UVM_INFO @ 10011386324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.rom_ctrl_stress_all_with_rand_reset.78859645832964150819244751819835880827248258919577903668764143468594629398426
      Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10371190463 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xfbe7e0b3
        UVM_INFO @ 10371190463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:

  • Test rom_ctrl_kmac_err_chk has 1 failures.

    • 4.rom_ctrl_kmac_err_chk.51967200475078848016835905812765450335096558023824125828808053584034752366825
      Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest/run.log

        UVM_ERROR @ 169799620045 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 169799620045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 44.rom_ctrl_corrupt_sig_fatal_chk.53081009909705670336002754013059543460300151164920811654702962595796872859675
      Line 287, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 46459950924 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 46459950924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 11.rom_ctrl_corrupt_sig_fatal_chk.79432777001917413548176350502863403354851528363089796404528869223930134525084
      Line 297, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test rom_ctrl_smoke has 1 failures.

    • 47.rom_ctrl_smoke.30458014300461783900978546271810761599398030394833408673297210640238541318914
      Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_smoke/latest/run.log

        UVM_FATAL @ 40016561452 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x14e87620
        UVM_INFO @ 40016561452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest