ROM_CTRL/64KB Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 18.850s 808.912us 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 25.260s 214.115us 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 15.270s 288.774us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 15.030s 555.256us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 11.680s 292.788us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 15.870s 2.052ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 15.270s 288.774us 20 20 100.00
rom_ctrl_csr_aliasing 11.680s 292.788us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 15.320s 289.983us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 13.140s 214.158us 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 17.920s 713.257us 50 50 100.00
V2 stress_all rom_ctrl_stress_all 53.940s 2.125ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 33.130s 543.288us 50 50 100.00
V2 alert_test rom_ctrl_alert_test 21.600s 5.212ms 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 26.440s 5.478ms 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 26.440s 5.478ms 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 25.260s 214.115us 5 5 100.00
rom_ctrl_csr_rw 15.270s 288.774us 20 20 100.00
rom_ctrl_csr_aliasing 11.680s 292.788us 5 5 100.00
rom_ctrl_same_csr_outstanding 16.930s 226.302us 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 25.260s 214.115us 5 5 100.00
rom_ctrl_csr_rw 15.270s 288.774us 20 20 100.00
rom_ctrl_csr_aliasing 11.680s 292.788us 5 5 100.00
rom_ctrl_same_csr_outstanding 16.930s 226.302us 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 8.006m 35.031ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 1.345m 1.975ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 4.353m 1.437ms 5 5 100.00
rom_ctrl_tl_intg_err 2.884m 477.705us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 4.353m 1.437ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 8.006m 35.031ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 8.006m 35.031ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 8.006m 35.031ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 8.006m 35.031ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 8.006m 35.031ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 4.353m 1.437ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 4.353m 1.437ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 18.850s 808.912us 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 18.850s 808.912us 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 18.850s 808.912us 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 2.884m 477.705us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 8.006m 35.031ms 50 50 100.00
rom_ctrl_kmac_err_chk 33.130s 543.288us 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 8.006m 35.031ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 8.006m 35.031ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 8.006m 35.031ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 1.345m 1.975ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 4.353m 1.437ms 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 4.654m 31.215ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 460 460 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.83 99.36 92.28 97.68 100.00 98.55 97.91 99.06

Past Results