ROM_CTRL/64KB Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: `ecd9f08747`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.369m	13.814ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	34.200s	11.636ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	31.220s	32.024ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	28.810s	14.643ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	32.610s	8.168ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	31.220s	29.600ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	31.220s	32.024ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.610s	8.168ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	26.400s	11.419ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	30.040s	14.678ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.590s	4.159ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.828m	26.218ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.148m	33.582ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.980s	17.924ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	38.530s	4.440ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	38.530s	4.440ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	34.200s	11.636ms	5	5	100.00
		rom_ctrl_csr_rw	31.220s	32.024ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.610s	8.168ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.330s	4.506ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	34.200s	11.636ms	5	5	100.00
		rom_ctrl_csr_rw	31.220s	32.024ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.610s	8.168ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.330s	4.506ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	21.396m	273.662ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.121m	23.883ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.354m	17.442ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.912m	4.550ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.354m	17.442ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.396m	273.662ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.396m	273.662ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	21.396m	273.662ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.396m	273.662ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.396m	273.662ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.354m	17.442ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.354m	17.442ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.369m	13.814ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.369m	13.814ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.369m	13.814ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.912m	4.550ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	21.396m	273.662ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.148m	33.582ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	21.396m	273.662ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	21.396m	273.662ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	21.396m	273.662ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.121m	23.883ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.354m	17.442ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.087h	70.352ms	5	50	10.00
V3		TOTAL			5	50	10.00
		TOTAL			453	500	90.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.48	96.97	92.87	97.88	100.00	98.37	97.88	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 35 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.78832721541591556342482352328415283019335284387706215061904870023829477082199
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3101007337 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3101007337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.81280688696637258847150446775927640807711005901414783735838513316539823262482
    Line 314, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11424577398 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11424577398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 22.rom_ctrl_stress_all_with_rand_reset.72843735961882846372851646434371120036533837249889018140850943049815511871263
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10528995165 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xd8a124a
  UVM_INFO @ 10528995165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.rom_ctrl_stress_all_with_rand_reset.10982497668241472161889738674812408154723614194096903437259080989205875318746
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10003710773 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x36f97068
  UVM_INFO @ 10003710773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 11.rom_ctrl_stress_all_with_rand_reset.38643646183992305142536920495269318592988556461136225143373370899778867892438
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:476c601f-ec8c-4b60-84d3-e6b0f9842221
```
  - 20.rom_ctrl_stress_all_with_rand_reset.63489990955302694571052988597839454624069149770356628375675573652460090218066
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a7cfba45-74d9-43f6-b1d7-8ea05ba5bed7
```
  - ... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_smoke has 1 failures.
  - 35.rom_ctrl_smoke.67220799276777725483674141685971141318370500792399827074366103268701153937000
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40017711867 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x1fcdf538
  UVM_INFO @ 40017711867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all has 1 failures.
  - 47.rom_ctrl_stress_all.69674254858321137957493460313965557638482411724721347654666412963018633683955
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40036214154 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xf1e1b7fa
  UVM_INFO @ 40036214154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ecd9f08747`