ROM_CTRL/64KB Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: `9f20940d49`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	24.260s	1.937ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	23.080s	1.044ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.970s	991.185us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.450s	688.974us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.280s	1.070ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	22.100s	1.027ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.970s	991.185us	20	20	100.00
		rom_ctrl_csr_aliasing	16.280s	1.070ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.920s	989.704us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.320s	990.544us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	23.990s	3.964ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.117m	3.818ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	55.060s	8.198ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	25.130s	3.644ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	23.800s	1.177ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	23.800s	1.177ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	23.080s	1.044ms	5	5	100.00
		rom_ctrl_csr_rw	14.970s	991.185us	20	20	100.00
		rom_ctrl_csr_aliasing	16.280s	1.070ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	26.690s	3.609ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	23.080s	1.044ms	5	5	100.00
		rom_ctrl_csr_rw	14.970s	991.185us	20	20	100.00
		rom_ctrl_csr_aliasing	16.280s	1.070ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	26.690s	3.609ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	10.262m	32.840ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.887m	6.338ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.517m	500.633us	5	5	100.00
		rom_ctrl_tl_intg_err	4.605m	492.316us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.517m	500.633us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.262m	32.840ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.262m	32.840ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.262m	32.840ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.262m	32.840ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.262m	32.840ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.517m	500.633us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.517m	500.633us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	24.260s	1.937ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	24.260s	1.937ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	24.260s	1.937ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	4.605m	492.316us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.262m	32.840ms	49	50	98.00
		rom_ctrl_kmac_err_chk	55.060s	8.198ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	10.262m	32.840ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.262m	32.840ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	10.262m	32.840ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.887m	6.338ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.517m	500.633us	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.576h	20.893ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			424	460	92.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.28	96.89	92.13	97.68	100.00	98.62	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 15 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.74584519294946716196091401818194438144114659855084699355578386820833560116648
    Line 80, in log /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 774431923 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 774431923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rom_ctrl_stress_all_with_rand_reset.9301198733544766972954244826720208505920432854276577320708063411241088848609
    Line 296, in log /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 95864340973 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 95864340973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
Job timed out after * minutes has 15 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 15 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.43162289223452525437178120720800706936911435776003083208056901645272959294476
    Log /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - 5.rom_ctrl_stress_all_with_rand_reset.11727309633451877052319287772966852785479850221408805243192243523944634066953
    Log /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - ... and 13 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 23.rom_ctrl_stress_all_with_rand_reset.43832071706548972914673917453916860262520157330796614022140698436489742082682
    Line 225, in log /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28720634492 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 28720634492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.rom_ctrl_stress_all_with_rand_reset.103641276397095888266912477709045111613381353061367197248955456859253634929800
    Line 140, in log /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21486759659 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 21486759659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 25.rom_ctrl_stress_all_with_rand_reset.3649589018623988099705807453331848762204113155644173231979065338750644072731
    Line 72, in log /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1172257394 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 1172257394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.rom_ctrl_stress_all_with_rand_reset.9838370347554635117029957642700969065692499768096424208215271446885350394416
    Line 163, in log /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 32894373421 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 32894373421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 39.rom_ctrl_corrupt_sig_fatal_chk.53160625764992777691537191583421468884307980317875730786346132671403047811547
    Line 117, in log /workspaces/repo/scratch/os_regression/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 87536862936 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 87536862936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9f20940d49`