Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

994809

1

T1

61

T3

237

T4

78

full_word

618422

1

T1

3

T2

6

T3

28

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1612921	1			T1	64		T2	6		T3	265
auto[TlIntgErrCmd]	92	1			T47	4		T49	1		T50	2
auto[TlIntgErrData]	113	1			T47	9		T49	3		T50	3
auto[TlIntgErrBoth]	105	1			T47	7		T49	6		T50	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

268706

1

T1

64

T2

6

T3

265

auto[1]

1344525

1

T11

208584

T17

116923

T18

332522

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	121333	1			T1	61		T3	237		T4	78
auto[TlIntgErrNone]	partial	auto[1]	873193	1			T11	137032		T17	74936		T18	217753
auto[TlIntgErrNone]	full_word	auto[0]	147239	1			T1	3		T2	6		T3	28
auto[TlIntgErrNone]	full_word	auto[1]	471156	1			T11	71552		T17	41987		T18	114769
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T97	1		T98	3		T103	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T47	4		T49	1		T50	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T108	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T100	1		T105	1		T109	2
auto[TlIntgErrData]	partial	auto[0]	45	1			T47	5		T50	2		T97	1
auto[TlIntgErrData]	partial	auto[1]	52	1			T47	3		T49	2		T50	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T49	1		T103	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T47	1		T103	2		T106	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T47	1		T49	4		T50	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T47	4		T49	1		T50	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T47	2		T49	1		T100	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T97	1		-	-		-	-