Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 53819 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1145952 1 T1 28 T2 11 T4 5



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 319355 1 T1 212 T2 86 T4 53
values[0x0] 432060 1 T13 24102 T14 23085 T15 28447
values[0x1] 448356 1 T13 24793 T14 24106 T15 29267



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 27234 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1172537 1 T1 138 T2 49 T4 35



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 4485 1 T11 3 T12 1 T108 3
valid_sources[0x01] 4794 1 T1 4 T36 1 T107 2
valid_sources[0x02] 4566 1 T5 1 T9 2 T11 1
valid_sources[0x03] 4300 1 T5 1 T7 1 T11 5
valid_sources[0x04] 4514 1 T1 2 T9 3 T36 1
valid_sources[0x05] 5525 1 T5 2 T7 1 T8 3
valid_sources[0x06] 4630 1 T5 1 T11 1 T36 2
valid_sources[0x07] 4610 1 T5 2 T9 1 T11 1
valid_sources[0x08] 4564 1 T11 1 T107 3 T98 1
valid_sources[0x09] 4611 1 T9 2 T36 2 T107 2
valid_sources[0x0a] 4608 1 T7 1 T9 1 T36 1
valid_sources[0x0b] 4476 1 T11 1 T36 1 T107 1
valid_sources[0x0c] 5047 1 T9 1 T11 2 T36 1
valid_sources[0x0d] 4431 1 T9 1 T11 2 T36 2
valid_sources[0x0e] 4911 1 T12 4 T107 2 T40 2
valid_sources[0x0f] 4703 1 T1 4 T5 3 T11 1
valid_sources[0x10] 4556 1 T1 6 T5 1 T7 2
valid_sources[0x11] 4499 1 T5 2 T9 3 T11 4
valid_sources[0x12] 4730 1 T12 7 T36 1 T107 4
valid_sources[0x13] 4386 1 T4 1 T11 2 T12 12
valid_sources[0x14] 4705 1 T5 2 T9 1 T11 4
valid_sources[0x15] 4901 1 T1 5 T12 1 T107 5
valid_sources[0x16] 4606 1 T5 1 T11 3 T12 3
valid_sources[0x17] 4631 1 T5 1 T11 1 T107 4
valid_sources[0x18] 4401 1 T1 4 T5 5 T11 4
valid_sources[0x19] 4874 1 T4 2 T5 1 T9 1
valid_sources[0x1a] 4442 1 T5 1 T9 1 T11 1
valid_sources[0x1b] 4466 1 T5 1 T9 1 T11 1
valid_sources[0x1c] 4654 1 T1 1 T5 1 T9 1
valid_sources[0x1d] 5434 1 T5 1 T7 6 T11 3
valid_sources[0x1e] 5211 1 T5 1 T12 1 T107 1
valid_sources[0x1f] 4851 1 T5 2 T107 1 T108 2
valid_sources[0x20] 4898 1 T1 3 T11 1 T107 2
valid_sources[0x21] 5079 1 T1 1 T11 3 T51 37
valid_sources[0x22] 4581 1 T1 5 T11 1 T12 10
valid_sources[0x23] 4544 1 T1 2 T5 1 T11 1
valid_sources[0x24] 4313 1 T5 2 T9 2 T12 6
valid_sources[0x25] 4354 1 T9 3 T11 1 T36 1
valid_sources[0x26] 4960 1 T2 10 T9 1 T107 1
valid_sources[0x27] 4293 1 T11 2 T107 3 T108 3
valid_sources[0x28] 4619 1 T1 1 T5 1 T107 1
valid_sources[0x29] 5607 1 T5 1 T36 2 T108 1
valid_sources[0x2a] 4400 1 T5 1 T11 1 T12 4
valid_sources[0x2b] 4524 1 T2 4 T5 2 T9 4
valid_sources[0x2c] 5375 1 T5 3 T9 1 T36 2
valid_sources[0x2d] 4139 1 T7 1 T9 2 T41 5
valid_sources[0x2e] 4483 1 T5 1 T107 1 T108 1
valid_sources[0x2f] 5107 1 T5 1 T36 2 T107 1
valid_sources[0x30] 4766 1 T11 2 T12 1 T36 1
valid_sources[0x31] 4975 1 T11 1 T107 1 T40 4
valid_sources[0x32] 4321 1 T9 3 T11 5 T107 2
valid_sources[0x33] 4418 1 T11 2 T36 1 T107 2
valid_sources[0x34] 5345 1 T4 2 T5 1 T36 1
valid_sources[0x35] 4360 1 T11 4 T107 5 T108 1
valid_sources[0x36] 4386 1 T9 1 T11 2 T107 2
valid_sources[0x37] 4782 1 T11 5 T107 1 T108 3
valid_sources[0x38] 5004 1 T2 7 T9 2 T11 1
valid_sources[0x39] 4774 1 T7 1 T9 1 T36 3
valid_sources[0x3a] 4910 1 T40 4 T98 1 T99 3
valid_sources[0x3b] 5368 1 T5 1 T9 1 T11 3
valid_sources[0x3c] 4335 1 T11 1 T100 1 T13 234
valid_sources[0x3d] 4399 1 T5 1 T9 1 T107 2
valid_sources[0x3e] 5034 1 T5 2 T7 3 T11 1
valid_sources[0x3f] 4682 1 T5 2 T9 2 T11 4
valid_sources[0x40] 4424 1 T1 1 T5 1 T7 3
valid_sources[0x41] 4421 1 T5 1 T9 2 T11 1
valid_sources[0x42] 4543 1 T5 1 T9 1 T11 2
valid_sources[0x43] 5048 1 T11 1 T36 1 T107 1
valid_sources[0x44] 4829 1 T5 1 T11 1 T108 1
valid_sources[0x45] 4619 1 T1 1 T2 9 T5 2
valid_sources[0x46] 4453 1 T9 1 T11 2 T107 3
valid_sources[0x47] 4606 1 T7 3 T9 1 T36 1
valid_sources[0x48] 4313 1 T9 1 T107 1 T108 1
valid_sources[0x49] 4419 1 T1 1 T5 3 T9 2
valid_sources[0x4a] 5530 1 T11 1 T36 1 T107 1
valid_sources[0x4b] 4495 1 T9 1 T11 2 T107 2
valid_sources[0x4c] 4721 1 T5 1 T9 1 T11 1
valid_sources[0x4d] 4554 1 T1 5 T5 1 T9 1
valid_sources[0x4e] 5045 1 T5 1 T9 1 T11 1
valid_sources[0x4f] 4890 1 T2 3 T9 1 T11 1
valid_sources[0x50] 4988 1 T1 1 T5 1 T11 2
valid_sources[0x51] 4336 1 T5 1 T7 1 T36 2
valid_sources[0x52] 4218 1 T1 1 T7 15 T9 1
valid_sources[0x53] 4684 1 T1 1 T5 1 T9 2
valid_sources[0x54] 4339 1 T7 1 T9 1 T11 1
valid_sources[0x55] 4397 1 T1 1 T5 1 T7 1
valid_sources[0x56] 4890 1 T4 8 T11 1 T40 3
valid_sources[0x57] 5559 1 T5 1 T7 5 T9 1
valid_sources[0x58] 4510 1 T1 1 T11 2 T107 4
valid_sources[0x59] 5589 1 T1 1 T5 1 T11 3
valid_sources[0x5a] 4504 1 T9 1 T108 3 T41 1
valid_sources[0x5b] 5568 1 T1 1 T9 1 T11 1
valid_sources[0x5c] 4775 1 T12 5 T36 1 T107 4
valid_sources[0x5d] 4391 1 T4 1 T5 1 T107 1
valid_sources[0x5e] 4364 1 T11 2 T107 2 T108 3
valid_sources[0x5f] 4505 1 T1 5 T7 6 T11 2
valid_sources[0x60] 4710 1 T11 2 T12 2 T36 1
valid_sources[0x61] 4342 1 T10 11 T11 1 T36 1
valid_sources[0x62] 4459 1 T1 2 T5 1 T9 1
valid_sources[0x63] 4347 1 T9 4 T36 2 T107 1
valid_sources[0x64] 5047 1 T4 2 T5 1 T11 2
valid_sources[0x65] 4457 1 T36 1 T108 1 T99 4
valid_sources[0x66] 5854 1 T1 1 T9 2 T11 1
valid_sources[0x67] 5139 1 T9 4 T107 1 T108 2
valid_sources[0x68] 4331 1 T5 1 T36 1 T107 2
valid_sources[0x69] 4371 1 T1 1 T5 1 T9 2
valid_sources[0x6a] 5411 1 T1 3 T11 3 T36 1
valid_sources[0x6b] 4768 1 T2 6 T36 1 T107 2
valid_sources[0x6c] 5247 1 T9 1 T11 1 T107 2
valid_sources[0x6d] 4990 1 T1 3 T5 1 T9 1
valid_sources[0x6e] 4461 1 T1 2 T5 1 T7 2
valid_sources[0x6f] 4305 1 T5 1 T7 1 T11 2
valid_sources[0x70] 4307 1 T9 2 T11 5 T107 1
valid_sources[0x71] 4928 1 T7 1 T36 1 T107 2
valid_sources[0x72] 4339 1 T5 1 T9 1 T11 1
valid_sources[0x73] 5028 1 T7 2 T10 22 T36 1
valid_sources[0x74] 4478 1 T11 1 T36 3 T108 1
valid_sources[0x75] 4955 1 T5 2 T9 1 T108 1
valid_sources[0x76] 4694 1 T9 1 T11 5 T107 1
valid_sources[0x77] 4296 1 T5 4 T7 3 T11 2
valid_sources[0x78] 4253 1 T5 1 T7 2 T11 1
valid_sources[0x79] 4806 1 T5 1 T9 2 T11 1
valid_sources[0x7a] 5472 1 T5 1 T11 5 T107 2
valid_sources[0x7b] 4402 1 T11 3 T36 1 T107 2
valid_sources[0x7c] 4494 1 T11 2 T12 1 T107 1
valid_sources[0x7d] 4572 1 T1 1 T5 1 T12 15
valid_sources[0x7e] 4970 1 T2 10 T11 3 T36 2
valid_sources[0x7f] 4591 1 T1 6 T5 3 T7 3
valid_sources[0x80] 4789 1 T11 4 T81 13 T107 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 288945 1 T1 28 T2 11 T4 5
values[0x0] all_enables biggest_size 428352 1 T13 23919 T14 22877 T15 28188
values[0x1] all_enables biggest_size 428655 1 T13 23783 T14 22988 T15 28010


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 86789 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 876958 1 T1 53 T2 15 T3 4



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 242915 1 T1 96 T2 32 T4 32
values[0x0] 334326 1 T3 10 T34 6 T35 3
values[0x1] 386506 1 T3 8 T34 7 T35 5



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 39950 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 923797 1 T1 62 T2 20 T3 7



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3206 1 T13 237 T22 2 T121 1
valid_sources[0x01] 4299 1 T1 1 T8 2 T13 254
valid_sources[0x02] 3472 1 T12 5 T36 1 T13 193
valid_sources[0x03] 3142 1 T13 174 T122 1 T14 230
valid_sources[0x04] 3853 1 T1 1 T5 1 T8 1
valid_sources[0x05] 3648 1 T12 1 T40 28 T13 232
valid_sources[0x06] 3516 1 T5 1 T46 1 T13 201
valid_sources[0x07] 4072 1 T35 1 T26 1 T98 1
valid_sources[0x08] 3478 1 T13 220 T47 1 T61 1
valid_sources[0x09] 4232 1 T1 1 T5 2 T13 218
valid_sources[0x0a] 3883 1 T1 1 T5 1 T13 225
valid_sources[0x0b] 3978 1 T13 216 T121 1 T123 1
valid_sources[0x0c] 3692 1 T13 213 T60 1 T14 181
valid_sources[0x0d] 3682 1 T5 3 T13 289 T121 1
valid_sources[0x0e] 3914 1 T13 201 T57 2 T121 1
valid_sources[0x0f] 3827 1 T13 178 T122 1 T121 1
valid_sources[0x10] 3505 1 T1 1 T99 1 T13 233
valid_sources[0x11] 3879 1 T1 1 T81 10 T120 1
valid_sources[0x12] 4099 1 T99 1 T13 279 T14 169
valid_sources[0x13] 4248 1 T5 1 T99 2 T13 164
valid_sources[0x14] 4218 1 T40 27 T13 190 T57 1
valid_sources[0x15] 3903 1 T5 1 T81 4 T120 1
valid_sources[0x16] 4119 1 T5 1 T98 1 T99 1
valid_sources[0x17] 3820 1 T13 216 T124 2 T14 139
valid_sources[0x18] 3423 1 T1 1 T5 1 T13 193
valid_sources[0x19] 3723 1 T1 1 T13 256 T59 1
valid_sources[0x1a] 3330 1 T36 1 T98 1 T125 1
valid_sources[0x1b] 3936 1 T1 1 T8 3 T81 1
valid_sources[0x1c] 3082 1 T34 9 T120 1 T13 172
valid_sources[0x1d] 3617 1 T1 1 T40 1 T13 243
valid_sources[0x1e] 3581 1 T13 179 T57 1 T121 1
valid_sources[0x1f] 3577 1 T1 1 T51 2 T126 26
valid_sources[0x20] 3464 1 T98 1 T120 1 T13 174
valid_sources[0x21] 3246 1 T5 1 T36 1 T13 211
valid_sources[0x22] 3427 1 T12 8 T36 1 T99 2
valid_sources[0x23] 3529 1 T13 214 T14 189 T127 3
valid_sources[0x24] 3546 1 T36 1 T13 213 T47 1
valid_sources[0x25] 4472 1 T27 3 T13 246 T121 1
valid_sources[0x26] 4007 1 T13 254 T57 1 T121 1
valid_sources[0x27] 3692 1 T13 180 T22 6 T60 1
valid_sources[0x28] 3191 1 T1 1 T13 201 T121 2
valid_sources[0x29] 3610 1 T36 1 T98 1 T13 139
valid_sources[0x2a] 3517 1 T13 228 T48 3 T122 1
valid_sources[0x2b] 3321 1 T12 2 T13 184 T60 1
valid_sources[0x2c] 3188 1 T1 1 T36 1 T13 164
valid_sources[0x2d] 3974 1 T13 191 T60 1 T121 1
valid_sources[0x2e] 3556 1 T1 1 T42 1 T98 1
valid_sources[0x2f] 2699 1 T1 2 T13 274 T59 1
valid_sources[0x30] 4319 1 T36 2 T13 266 T121 1
valid_sources[0x31] 3581 1 T1 2 T99 1 T120 1
valid_sources[0x32] 4009 1 T40 2 T13 199 T59 1
valid_sources[0x33] 3468 1 T36 2 T13 214 T48 1
valid_sources[0x34] 3136 1 T1 1 T25 1 T13 248
valid_sources[0x35] 4088 1 T36 1 T40 4 T27 3
valid_sources[0x36] 3363 1 T36 1 T13 205 T47 1
valid_sources[0x37] 2828 1 T36 1 T81 3 T13 268
valid_sources[0x38] 3286 1 T1 1 T5 2 T81 2
valid_sources[0x39] 4750 1 T1 3 T8 1 T13 215
valid_sources[0x3a] 3985 1 T5 3 T36 1 T13 218
valid_sources[0x3b] 4202 1 T1 1 T41 3 T13 249
valid_sources[0x3c] 4352 1 T1 1 T5 1 T13 218
valid_sources[0x3d] 3300 1 T5 1 T13 175 T57 1
valid_sources[0x3e] 2923 1 T28 2 T13 163 T122 1
valid_sources[0x3f] 3675 1 T41 1 T98 1 T99 5
valid_sources[0x40] 4033 1 T13 266 T122 1 T128 2
valid_sources[0x41] 3693 1 T5 1 T98 1 T13 233
valid_sources[0x42] 3388 1 T13 220 T57 7 T60 1
valid_sources[0x43] 4943 1 T1 1 T5 1 T36 1
valid_sources[0x44] 3575 1 T1 1 T12 5 T120 2
valid_sources[0x45] 4169 1 T5 1 T13 177 T60 1
valid_sources[0x46] 4313 1 T5 1 T36 2 T35 7
valid_sources[0x47] 3798 1 T5 1 T36 1 T40 3
valid_sources[0x48] 3457 1 T1 1 T13 203 T57 1
valid_sources[0x49] 3876 1 T98 1 T120 1 T13 202
valid_sources[0x4a] 3451 1 T13 173 T59 2 T121 2
valid_sources[0x4b] 3033 1 T1 1 T13 171 T57 2
valid_sources[0x4c] 3328 1 T13 202 T122 1 T129 2
valid_sources[0x4d] 3622 1 T40 2 T13 160 T61 4
valid_sources[0x4e] 4967 1 T5 1 T13 201 T57 1
valid_sources[0x4f] 4272 1 T5 1 T81 4 T13 288
valid_sources[0x50] 3976 1 T8 1 T40 11 T13 227
valid_sources[0x51] 4011 1 T1 1 T13 259 T14 243
valid_sources[0x52] 4185 1 T8 1 T40 4 T13 210
valid_sources[0x53] 3374 1 T1 1 T36 1 T40 11
valid_sources[0x54] 3060 1 T1 1 T5 1 T120 1
valid_sources[0x55] 3581 1 T1 1 T36 1 T13 215
valid_sources[0x56] 3992 1 T1 1 T12 4 T13 200
valid_sources[0x57] 3704 1 T98 1 T13 263 T14 177
valid_sources[0x58] 4439 1 T13 226 T50 1 T124 1
valid_sources[0x59] 3268 1 T1 1 T12 6 T13 206
valid_sources[0x5a] 3459 1 T13 177 T32 4 T129 1
valid_sources[0x5b] 3405 1 T1 1 T27 3 T13 221
valid_sources[0x5c] 4015 1 T5 1 T13 227 T121 1
valid_sources[0x5d] 3807 1 T18 1 T13 172 T14 276
valid_sources[0x5e] 3062 1 T36 1 T98 1 T13 197
valid_sources[0x5f] 3737 1 T5 1 T98 1 T13 254
valid_sources[0x60] 3481 1 T1 1 T8 2 T81 2
valid_sources[0x61] 3510 1 T69 1 T13 229 T121 3
valid_sources[0x62] 3948 1 T13 230 T59 1 T70 1
valid_sources[0x63] 3407 1 T2 32 T13 211 T14 205
valid_sources[0x64] 3645 1 T13 224 T14 142 T15 220
valid_sources[0x65] 3586 1 T1 4 T36 2 T27 2
valid_sources[0x66] 4272 1 T1 1 T40 8 T13 237
valid_sources[0x67] 3116 1 T27 1 T13 237 T121 1
valid_sources[0x68] 3054 1 T1 1 T13 171 T57 2
valid_sources[0x69] 4178 1 T13 159 T122 1 T121 5
valid_sources[0x6a] 3678 1 T1 1 T5 1 T13 233
valid_sources[0x6b] 4345 1 T41 13 T27 4 T13 265
valid_sources[0x6c] 3313 1 T120 1 T13 167 T59 1
valid_sources[0x6d] 3589 1 T5 1 T13 286 T57 1
valid_sources[0x6e] 3696 1 T1 1 T36 2 T69 2
valid_sources[0x6f] 3937 1 T8 2 T36 1 T98 1
valid_sources[0x70] 3602 1 T5 1 T36 1 T13 177
valid_sources[0x71] 3736 1 T12 5 T29 11 T13 245
valid_sources[0x72] 4761 1 T5 1 T13 177 T48 2
valid_sources[0x73] 3871 1 T1 1 T8 1 T36 1
valid_sources[0x74] 4526 1 T34 2 T13 204 T22 1
valid_sources[0x75] 4425 1 T1 1 T5 1 T68 2
valid_sources[0x76] 4709 1 T120 2 T13 205 T57 8
valid_sources[0x77] 3302 1 T5 1 T68 1 T13 167
valid_sources[0x78] 3635 1 T5 1 T12 2 T98 1
valid_sources[0x79] 3179 1 T13 197 T58 1 T121 1
valid_sources[0x7a] 3888 1 T5 2 T13 260 T122 1
valid_sources[0x7b] 3914 1 T12 2 T13 234 T47 1
valid_sources[0x7c] 3468 1 T1 2 T13 213 T57 1
valid_sources[0x7d] 3343 1 T5 2 T7 13 T13 180
valid_sources[0x7e] 4150 1 T5 1 T36 2 T13 257
valid_sources[0x7f] 3328 1 T5 1 T98 1 T13 195
valid_sources[0x80] 3916 1 T5 1 T41 28 T98 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 222092 1 T1 53 T2 15 T4 15
values[0x0] all_enables biggest_size 327212 1 T3 3 T34 2 T35 1
values[0x1] all_enables biggest_size 327654 1 T3 1 T34 1 T43 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%