Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2102939

1

T1

184

T2

75

T4

48

full_word

1338802

1

T1

28

T2

11

T4

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3441441	1			T1	212		T2	86		T4	53
auto[TlIntgErrCmd]	102	1			T62	5		T63	3		T64	4
auto[TlIntgErrData]	89	1			T62	7		T63	3		T64	4
auto[TlIntgErrBoth]	109	1			T62	8		T63	4		T64	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

553203

1

T1

212

T2

86

T4

53

auto[1]

2888538

1

T13

159602

T14

161184

T15

184924

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	236081	1			T1	184		T2	75		T4	48
auto[TlIntgErrNone]	partial	auto[1]	1866577	1			T13	102515		T14	106058		T15	118342
auto[TlIntgErrNone]	full_word	auto[0]	316986	1			T1	28		T2	11		T4	5
auto[TlIntgErrNone]	full_word	auto[1]	1021797	1			T13	57087		T14	55126		T15	66582
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T64	2		T109	1		T112	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T62	4		T63	3		T64	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T62	1		T110	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T117	1		T118	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T62	2		T63	2		T64	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T62	4		T64	3		T109	1
auto[TlIntgErrData]	full_word	auto[0]	1	1			T111	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T62	1		T63	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T62	2		T63	1		T64	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T62	2		T63	3		T64	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T62	2		T114	1		T117	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T62	2		T110	1		T117	1