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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.50 96.97 93.01 97.88 100.00 98.37 97.88 98.37


Total test records in report: 449
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T305 /workspace/coverage/default/20.rom_ctrl_stress_all.2358608757 Apr 28 04:54:48 PM PDT 24 Apr 28 04:55:26 PM PDT 24 2152282481 ps
T306 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1046401061 Apr 28 04:54:50 PM PDT 24 Apr 28 04:55:22 PM PDT 24 13568547520 ps
T307 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.903710679 Apr 28 04:56:02 PM PDT 24 Apr 28 05:05:39 PM PDT 24 123391557938 ps
T308 /workspace/coverage/default/3.rom_ctrl_alert_test.4074556787 Apr 28 04:54:19 PM PDT 24 Apr 28 04:54:45 PM PDT 24 3042677066 ps
T309 /workspace/coverage/default/13.rom_ctrl_stress_all.2275193800 Apr 28 04:54:34 PM PDT 24 Apr 28 04:57:12 PM PDT 24 13456960248 ps
T310 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4024454799 Apr 28 04:54:14 PM PDT 24 Apr 28 05:02:00 PM PDT 24 38356062474 ps
T311 /workspace/coverage/default/22.rom_ctrl_smoke.3633019175 Apr 28 04:54:47 PM PDT 24 Apr 28 04:55:14 PM PDT 24 849117083 ps
T32 /workspace/coverage/default/3.rom_ctrl_sec_cm.1004226308 Apr 28 04:54:19 PM PDT 24 Apr 28 04:56:17 PM PDT 24 1459935205 ps
T312 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1784665530 Apr 28 04:54:27 PM PDT 24 Apr 28 04:54:47 PM PDT 24 1570789767 ps
T313 /workspace/coverage/default/21.rom_ctrl_stress_all.3701192501 Apr 28 04:54:45 PM PDT 24 Apr 28 04:55:17 PM PDT 24 595011538 ps
T314 /workspace/coverage/default/45.rom_ctrl_alert_test.3677298722 Apr 28 04:56:03 PM PDT 24 Apr 28 04:56:32 PM PDT 24 31185705982 ps
T315 /workspace/coverage/default/47.rom_ctrl_alert_test.3476356892 Apr 28 04:55:57 PM PDT 24 Apr 28 04:56:27 PM PDT 24 12934916636 ps
T316 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1522309930 Apr 28 04:56:02 PM PDT 24 Apr 28 04:56:41 PM PDT 24 3251491183 ps
T317 /workspace/coverage/default/25.rom_ctrl_alert_test.3904942036 Apr 28 04:54:53 PM PDT 24 Apr 28 04:55:02 PM PDT 24 825844876 ps
T318 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.487545918 Apr 28 04:54:25 PM PDT 24 Apr 28 04:55:35 PM PDT 24 33249171879 ps
T319 /workspace/coverage/default/42.rom_ctrl_smoke.413044459 Apr 28 04:56:02 PM PDT 24 Apr 28 04:56:23 PM PDT 24 709506818 ps
T320 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.724557013 Apr 28 04:54:30 PM PDT 24 Apr 28 04:54:49 PM PDT 24 2197874277 ps
T321 /workspace/coverage/default/28.rom_ctrl_alert_test.1632680320 Apr 28 04:55:02 PM PDT 24 Apr 28 04:55:19 PM PDT 24 7684393588 ps
T322 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2374819562 Apr 28 04:54:45 PM PDT 24 Apr 28 05:01:07 PM PDT 24 62095925587 ps
T323 /workspace/coverage/default/21.rom_ctrl_alert_test.953567093 Apr 28 04:54:46 PM PDT 24 Apr 28 04:54:55 PM PDT 24 689299822 ps
T324 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1898609874 Apr 28 04:54:31 PM PDT 24 Apr 28 04:54:51 PM PDT 24 769193281 ps
T325 /workspace/coverage/default/47.rom_ctrl_smoke.522660120 Apr 28 04:56:06 PM PDT 24 Apr 28 04:57:11 PM PDT 24 7375894964 ps
T326 /workspace/coverage/default/20.rom_ctrl_alert_test.411013706 Apr 28 04:54:50 PM PDT 24 Apr 28 04:55:05 PM PDT 24 847228671 ps
T327 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.427105938 Apr 28 04:55:59 PM PDT 24 Apr 28 05:07:35 PM PDT 24 164546450777 ps
T47 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3812209189 Apr 28 04:55:15 PM PDT 24 Apr 28 05:06:21 PM PDT 24 25546201617 ps
T328 /workspace/coverage/default/36.rom_ctrl_alert_test.4282799268 Apr 28 04:56:27 PM PDT 24 Apr 28 04:56:50 PM PDT 24 4183646989 ps
T329 /workspace/coverage/default/22.rom_ctrl_alert_test.2604586755 Apr 28 04:54:53 PM PDT 24 Apr 28 04:55:18 PM PDT 24 3006938393 ps
T330 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.726472284 Apr 28 04:54:22 PM PDT 24 Apr 28 04:54:38 PM PDT 24 2797321650 ps
T331 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3409568600 Apr 28 04:54:21 PM PDT 24 Apr 28 04:54:50 PM PDT 24 11649539065 ps
T332 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3790083085 Apr 28 04:56:01 PM PDT 24 Apr 28 04:56:32 PM PDT 24 3615744475 ps
T333 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1006777280 Apr 28 04:54:33 PM PDT 24 Apr 28 05:08:59 PM PDT 24 96456775096 ps
T334 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3182741837 Apr 28 04:54:17 PM PDT 24 Apr 28 04:54:37 PM PDT 24 487346202 ps
T335 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2980365541 Apr 28 04:54:26 PM PDT 24 Apr 28 04:55:24 PM PDT 24 6235977522 ps
T336 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.4276266966 Apr 28 04:55:13 PM PDT 24 Apr 28 04:55:51 PM PDT 24 52039737799 ps
T337 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3630316025 Apr 28 04:55:10 PM PDT 24 Apr 28 05:01:40 PM PDT 24 29290722227 ps
T338 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2533920386 Apr 28 04:54:46 PM PDT 24 Apr 28 04:55:20 PM PDT 24 4433663121 ps
T339 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2636847661 Apr 28 04:56:05 PM PDT 24 Apr 28 04:57:13 PM PDT 24 8709646486 ps
T340 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3430078802 Apr 28 04:54:50 PM PDT 24 Apr 28 04:55:11 PM PDT 24 345956804 ps
T341 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3977167368 Apr 28 04:56:07 PM PDT 24 Apr 28 04:56:18 PM PDT 24 176031863 ps
T342 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2469014900 Apr 28 04:55:59 PM PDT 24 Apr 28 04:56:54 PM PDT 24 22541794665 ps
T343 /workspace/coverage/default/2.rom_ctrl_stress_all.3773054659 Apr 28 04:54:15 PM PDT 24 Apr 28 04:54:55 PM PDT 24 856281577 ps
T344 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3119592940 Apr 28 04:54:49 PM PDT 24 Apr 28 04:55:10 PM PDT 24 20011316695 ps
T345 /workspace/coverage/default/25.rom_ctrl_smoke.2404409193 Apr 28 04:54:53 PM PDT 24 Apr 28 04:55:59 PM PDT 24 29694719672 ps
T346 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3475977777 Apr 28 04:56:06 PM PDT 24 Apr 28 05:05:45 PM PDT 24 60729091257 ps
T347 /workspace/coverage/default/32.rom_ctrl_alert_test.3518090981 Apr 28 04:55:13 PM PDT 24 Apr 28 04:55:30 PM PDT 24 4241278607 ps
T348 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3863999213 Apr 28 04:54:22 PM PDT 24 Apr 28 04:57:42 PM PDT 24 3182520287 ps
T349 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.559238134 Apr 28 04:54:23 PM PDT 24 Apr 28 04:59:11 PM PDT 24 22069913309 ps
T350 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3490907313 Apr 28 04:54:33 PM PDT 24 Apr 28 04:55:18 PM PDT 24 4101323354 ps
T351 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4248679434 Apr 28 04:54:13 PM PDT 24 Apr 28 04:54:33 PM PDT 24 690131822 ps
T352 /workspace/coverage/default/5.rom_ctrl_stress_all.3069841703 Apr 28 04:54:21 PM PDT 24 Apr 28 04:54:47 PM PDT 24 2484536429 ps
T353 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.421591411 Apr 28 04:54:54 PM PDT 24 Apr 28 04:55:22 PM PDT 24 990677734 ps
T354 /workspace/coverage/default/13.rom_ctrl_alert_test.3987381973 Apr 28 04:54:33 PM PDT 24 Apr 28 04:55:06 PM PDT 24 7992932625 ps
T355 /workspace/coverage/default/25.rom_ctrl_stress_all.3061899737 Apr 28 04:54:55 PM PDT 24 Apr 28 04:58:24 PM PDT 24 102252473774 ps
T356 /workspace/coverage/default/3.rom_ctrl_stress_all.2784119677 Apr 28 04:54:21 PM PDT 24 Apr 28 04:55:18 PM PDT 24 36044709688 ps
T357 /workspace/coverage/default/45.rom_ctrl_stress_all.3417779576 Apr 28 04:56:07 PM PDT 24 Apr 28 04:56:35 PM PDT 24 8453915778 ps
T48 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2338986885 Apr 28 01:20:35 PM PDT 24 Apr 28 01:21:08 PM PDT 24 18287241333 ps
T358 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2253787871 Apr 28 01:20:12 PM PDT 24 Apr 28 01:20:25 PM PDT 24 602281455 ps
T54 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4095262044 Apr 28 01:20:47 PM PDT 24 Apr 28 01:21:39 PM PDT 24 4004765952 ps
T55 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.572636360 Apr 28 01:20:13 PM PDT 24 Apr 28 01:20:21 PM PDT 24 169173905 ps
T49 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3796733407 Apr 28 01:20:48 PM PDT 24 Apr 28 01:20:57 PM PDT 24 1333050031 ps
T359 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3281818492 Apr 28 01:20:26 PM PDT 24 Apr 28 01:20:50 PM PDT 24 10723869525 ps
T50 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3410867279 Apr 28 01:20:34 PM PDT 24 Apr 28 01:21:54 PM PDT 24 2604891877 ps
T360 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3225310165 Apr 28 01:20:31 PM PDT 24 Apr 28 01:21:02 PM PDT 24 17060878331 ps
T60 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1110940279 Apr 28 01:20:48 PM PDT 24 Apr 28 01:21:09 PM PDT 24 6075206357 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1648711787 Apr 28 01:20:11 PM PDT 24 Apr 28 01:21:14 PM PDT 24 5135098220 ps
T361 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3128733830 Apr 28 01:20:44 PM PDT 24 Apr 28 01:20:59 PM PDT 24 950634563 ps
T88 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.725892906 Apr 28 01:20:23 PM PDT 24 Apr 28 01:20:50 PM PDT 24 5312307760 ps
T52 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2657754011 Apr 28 01:20:36 PM PDT 24 Apr 28 01:21:59 PM PDT 24 3064930836 ps
T53 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2773917904 Apr 28 01:20:30 PM PDT 24 Apr 28 01:23:06 PM PDT 24 4333761353 ps
T362 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2479954284 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:19 PM PDT 24 185585149 ps
T363 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1787688967 Apr 28 01:20:35 PM PDT 24 Apr 28 01:21:07 PM PDT 24 12650752878 ps
T93 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1572293573 Apr 28 01:20:44 PM PDT 24 Apr 28 01:20:53 PM PDT 24 345561906 ps
T364 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.558941023 Apr 28 01:20:45 PM PDT 24 Apr 28 01:20:54 PM PDT 24 682226282 ps
T94 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4164656499 Apr 28 01:20:30 PM PDT 24 Apr 28 01:21:00 PM PDT 24 3105115200 ps
T103 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4122316756 Apr 28 01:20:39 PM PDT 24 Apr 28 01:22:16 PM PDT 24 3200739753 ps
T95 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2237722409 Apr 28 01:20:45 PM PDT 24 Apr 28 01:23:44 PM PDT 24 43312379842 ps
T365 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1334831810 Apr 28 01:20:36 PM PDT 24 Apr 28 01:21:04 PM PDT 24 16805275903 ps
T366 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2655035251 Apr 28 01:20:40 PM PDT 24 Apr 28 01:21:01 PM PDT 24 1452968343 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2396761546 Apr 28 01:20:25 PM PDT 24 Apr 28 01:20:37 PM PDT 24 167545866 ps
T89 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2255338422 Apr 28 01:20:35 PM PDT 24 Apr 28 01:21:07 PM PDT 24 17007562804 ps
T90 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1049788431 Apr 28 01:20:44 PM PDT 24 Apr 28 01:21:08 PM PDT 24 2670498024 ps
T102 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1074226518 Apr 28 01:20:41 PM PDT 24 Apr 28 01:23:32 PM PDT 24 3950927729 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2632880992 Apr 28 01:20:16 PM PDT 24 Apr 28 01:20:24 PM PDT 24 1372639763 ps
T110 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3901272317 Apr 28 01:20:45 PM PDT 24 Apr 28 01:22:22 PM PDT 24 12299462920 ps
T369 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2188466747 Apr 28 01:20:26 PM PDT 24 Apr 28 01:20:39 PM PDT 24 1347421256 ps
T370 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1881349718 Apr 28 01:20:38 PM PDT 24 Apr 28 01:20:48 PM PDT 24 786617972 ps
T371 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3570674679 Apr 28 01:20:44 PM PDT 24 Apr 28 01:20:58 PM PDT 24 688036009 ps
T62 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3874290306 Apr 28 01:20:15 PM PDT 24 Apr 28 01:20:23 PM PDT 24 687923377 ps
T105 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.726550778 Apr 28 01:20:45 PM PDT 24 Apr 28 01:23:36 PM PDT 24 9008507745 ps
T104 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3081059951 Apr 28 01:20:39 PM PDT 24 Apr 28 01:22:17 PM PDT 24 3838554923 ps
T63 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1701437923 Apr 28 01:20:43 PM PDT 24 Apr 28 01:21:17 PM PDT 24 13381508186 ps
T64 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1741323443 Apr 28 01:20:44 PM PDT 24 Apr 28 01:21:00 PM PDT 24 10043579023 ps
T372 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1599763002 Apr 28 01:20:25 PM PDT 24 Apr 28 01:20:42 PM PDT 24 4418906367 ps
T65 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3735070376 Apr 28 01:20:40 PM PDT 24 Apr 28 01:21:11 PM PDT 24 13581262125 ps
T66 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2747245140 Apr 28 01:20:44 PM PDT 24 Apr 28 01:21:17 PM PDT 24 4251748534 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2641200160 Apr 28 01:20:24 PM PDT 24 Apr 28 01:20:36 PM PDT 24 339255987 ps
T374 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.940372869 Apr 28 01:20:32 PM PDT 24 Apr 28 01:20:50 PM PDT 24 3354403115 ps
T100 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3452278712 Apr 28 01:20:23 PM PDT 24 Apr 28 01:22:31 PM PDT 24 36545655132 ps
T375 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.77686106 Apr 28 01:20:25 PM PDT 24 Apr 28 01:20:37 PM PDT 24 348657084 ps
T376 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3093929178 Apr 28 01:20:45 PM PDT 24 Apr 28 01:20:57 PM PDT 24 169299563 ps
T91 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2144288933 Apr 28 01:20:35 PM PDT 24 Apr 28 01:20:53 PM PDT 24 1037573688 ps
T108 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.746294274 Apr 28 01:20:44 PM PDT 24 Apr 28 01:22:28 PM PDT 24 4356987431 ps
T67 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3511537835 Apr 28 01:20:32 PM PDT 24 Apr 28 01:23:51 PM PDT 24 25333880392 ps
T68 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3557392612 Apr 28 01:20:43 PM PDT 24 Apr 28 01:21:13 PM PDT 24 14351539642 ps
T74 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.756331556 Apr 28 01:20:43 PM PDT 24 Apr 28 01:21:07 PM PDT 24 2876093283 ps
T92 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2935139762 Apr 28 01:20:43 PM PDT 24 Apr 28 01:21:14 PM PDT 24 4027737539 ps
T75 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3452222245 Apr 28 01:20:15 PM PDT 24 Apr 28 01:23:11 PM PDT 24 20729673385 ps
T76 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.693616713 Apr 28 01:20:32 PM PDT 24 Apr 28 01:20:48 PM PDT 24 5005703863 ps
T77 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1735308176 Apr 28 01:20:41 PM PDT 24 Apr 28 01:20:50 PM PDT 24 660851237 ps
T377 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3196381215 Apr 28 01:20:37 PM PDT 24 Apr 28 01:20:59 PM PDT 24 19523069511 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.450549758 Apr 28 01:20:31 PM PDT 24 Apr 28 01:22:00 PM PDT 24 5044729500 ps
T379 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.946513531 Apr 28 01:20:43 PM PDT 24 Apr 28 01:21:08 PM PDT 24 11538199675 ps
T380 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2658872161 Apr 28 01:20:44 PM PDT 24 Apr 28 01:21:46 PM PDT 24 15112050843 ps
T101 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.940636154 Apr 28 01:20:44 PM PDT 24 Apr 28 01:23:39 PM PDT 24 80224077145 ps
T78 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.785507703 Apr 28 01:20:42 PM PDT 24 Apr 28 01:20:56 PM PDT 24 687147286 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3328284823 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:24 PM PDT 24 325802242 ps
T382 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3462912902 Apr 28 01:20:14 PM PDT 24 Apr 28 01:20:32 PM PDT 24 4137541664 ps
T383 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2961465344 Apr 28 01:20:47 PM PDT 24 Apr 28 01:22:10 PM PDT 24 7936420661 ps
T384 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2763916147 Apr 28 01:20:35 PM PDT 24 Apr 28 01:20:47 PM PDT 24 605999713 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3619434087 Apr 28 01:20:14 PM PDT 24 Apr 28 01:20:47 PM PDT 24 23168788393 ps
T79 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.835252499 Apr 28 01:20:35 PM PDT 24 Apr 28 01:21:01 PM PDT 24 3028728919 ps
T386 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.600351159 Apr 28 01:20:41 PM PDT 24 Apr 28 01:21:17 PM PDT 24 8036264684 ps
T387 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2520039908 Apr 28 01:20:37 PM PDT 24 Apr 28 01:20:59 PM PDT 24 2294814219 ps
T388 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2479046078 Apr 28 01:20:44 PM PDT 24 Apr 28 01:22:02 PM PDT 24 12468364325 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1639339296 Apr 28 01:20:30 PM PDT 24 Apr 28 01:20:46 PM PDT 24 8289689114 ps
T390 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1784800591 Apr 28 01:20:44 PM PDT 24 Apr 28 01:20:57 PM PDT 24 1007400333 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3428928930 Apr 28 01:20:30 PM PDT 24 Apr 28 01:20:49 PM PDT 24 1628472260 ps
T392 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3142461279 Apr 28 01:20:46 PM PDT 24 Apr 28 01:20:55 PM PDT 24 1446019041 ps
T80 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3828617923 Apr 28 01:20:35 PM PDT 24 Apr 28 01:21:32 PM PDT 24 1083399860 ps
T82 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2212837903 Apr 28 01:20:37 PM PDT 24 Apr 28 01:22:34 PM PDT 24 10676907046 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1662565900 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:30 PM PDT 24 18321689890 ps
T394 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2776577471 Apr 28 01:20:41 PM PDT 24 Apr 28 01:21:11 PM PDT 24 26579140991 ps
T109 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1250132897 Apr 28 01:20:40 PM PDT 24 Apr 28 01:22:17 PM PDT 24 13356617137 ps
T112 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.378670940 Apr 28 01:20:27 PM PDT 24 Apr 28 01:21:57 PM PDT 24 11650857402 ps
T395 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.550699896 Apr 28 01:20:31 PM PDT 24 Apr 28 01:20:59 PM PDT 24 10903504612 ps
T396 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1853047247 Apr 28 01:20:43 PM PDT 24 Apr 28 01:21:39 PM PDT 24 4287922520 ps
T397 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3592096607 Apr 28 01:20:26 PM PDT 24 Apr 28 01:20:39 PM PDT 24 2747208701 ps
T398 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3350234575 Apr 28 01:20:45 PM PDT 24 Apr 28 01:21:20 PM PDT 24 25041729461 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4243272535 Apr 28 01:20:34 PM PDT 24 Apr 28 01:21:03 PM PDT 24 13699218644 ps
T83 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3903663072 Apr 28 01:20:38 PM PDT 24 Apr 28 01:22:25 PM PDT 24 9075031312 ps
T400 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.568442105 Apr 28 01:20:46 PM PDT 24 Apr 28 01:22:30 PM PDT 24 11148062608 ps
T401 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2650780519 Apr 28 01:20:42 PM PDT 24 Apr 28 01:20:52 PM PDT 24 365606873 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.736517586 Apr 28 01:20:35 PM PDT 24 Apr 28 01:20:44 PM PDT 24 167513189 ps
T403 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1777451863 Apr 28 01:20:40 PM PDT 24 Apr 28 01:20:50 PM PDT 24 1388814552 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2622160944 Apr 28 01:20:23 PM PDT 24 Apr 28 01:20:54 PM PDT 24 4104782647 ps
T405 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3656351968 Apr 28 01:20:46 PM PDT 24 Apr 28 01:21:03 PM PDT 24 2940142615 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3442131601 Apr 28 01:20:34 PM PDT 24 Apr 28 01:20:57 PM PDT 24 19781285300 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.277068594 Apr 28 01:20:14 PM PDT 24 Apr 28 01:20:46 PM PDT 24 15738690382 ps
T408 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2240704287 Apr 28 01:20:43 PM PDT 24 Apr 28 01:21:20 PM PDT 24 56180621408 ps
T111 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2833176766 Apr 28 01:20:36 PM PDT 24 Apr 28 01:21:57 PM PDT 24 239815104 ps
T409 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.738627999 Apr 28 01:20:44 PM PDT 24 Apr 28 01:21:14 PM PDT 24 3797340481 ps
T87 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1728150570 Apr 28 01:20:36 PM PDT 24 Apr 28 01:21:01 PM PDT 24 2778354355 ps
T410 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3991163704 Apr 28 01:20:36 PM PDT 24 Apr 28 01:21:08 PM PDT 24 3941404479 ps
T411 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1908846426 Apr 28 01:20:32 PM PDT 24 Apr 28 01:20:53 PM PDT 24 10886135290 ps
T106 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1606772899 Apr 28 01:20:40 PM PDT 24 Apr 28 01:23:26 PM PDT 24 9262261028 ps
T412 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2980094129 Apr 28 01:20:35 PM PDT 24 Apr 28 01:20:59 PM PDT 24 3530438066 ps
T413 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2281596338 Apr 28 01:20:34 PM PDT 24 Apr 28 01:20:48 PM PDT 24 2964304283 ps
T414 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3099008914 Apr 28 01:20:30 PM PDT 24 Apr 28 01:20:59 PM PDT 24 3628383018 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1321360358 Apr 28 01:20:25 PM PDT 24 Apr 28 01:20:34 PM PDT 24 368480083 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2484058199 Apr 28 01:20:27 PM PDT 24 Apr 28 01:20:41 PM PDT 24 835342249 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3038373786 Apr 28 01:20:16 PM PDT 24 Apr 28 01:20:32 PM PDT 24 351133898 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3433824226 Apr 28 01:20:14 PM PDT 24 Apr 28 01:20:28 PM PDT 24 3295857259 ps
T418 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1772190380 Apr 28 01:20:32 PM PDT 24 Apr 28 01:22:13 PM PDT 24 10954289639 ps
T419 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1094056372 Apr 28 01:20:45 PM PDT 24 Apr 28 01:21:09 PM PDT 24 7123794230 ps
T420 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.221731124 Apr 28 01:20:28 PM PDT 24 Apr 28 01:21:43 PM PDT 24 6239959748 ps
T84 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4127148388 Apr 28 01:20:39 PM PDT 24 Apr 28 01:23:59 PM PDT 24 114069726139 ps
T421 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1168794465 Apr 28 01:20:42 PM PDT 24 Apr 28 01:21:08 PM PDT 24 2818187721 ps
T422 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3217107224 Apr 28 01:20:31 PM PDT 24 Apr 28 01:21:11 PM PDT 24 9720603000 ps
T423 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.758290900 Apr 28 01:20:49 PM PDT 24 Apr 28 01:21:05 PM PDT 24 4822719310 ps
T424 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.855546083 Apr 28 01:20:40 PM PDT 24 Apr 28 01:20:53 PM PDT 24 364620771 ps
T425 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3730871432 Apr 28 01:20:45 PM PDT 24 Apr 28 01:20:57 PM PDT 24 169411571 ps
T426 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.34351253 Apr 28 01:20:40 PM PDT 24 Apr 28 01:20:56 PM PDT 24 861893028 ps
T427 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1419872534 Apr 28 01:20:40 PM PDT 24 Apr 28 01:20:54 PM PDT 24 5637961457 ps
T428 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1631973556 Apr 28 01:20:30 PM PDT 24 Apr 28 01:20:39 PM PDT 24 1649374778 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1052454292 Apr 28 01:20:22 PM PDT 24 Apr 28 01:20:30 PM PDT 24 167701003 ps
T107 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3279363396 Apr 28 01:20:34 PM PDT 24 Apr 28 01:23:13 PM PDT 24 3864071331 ps
T430 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3087452621 Apr 28 01:20:26 PM PDT 24 Apr 28 01:20:51 PM PDT 24 3617542752 ps
T431 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1288724815 Apr 28 01:20:25 PM PDT 24 Apr 28 01:20:40 PM PDT 24 4413910428 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1483713041 Apr 28 01:20:29 PM PDT 24 Apr 28 01:20:48 PM PDT 24 11470791972 ps
T433 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2358157437 Apr 28 01:20:30 PM PDT 24 Apr 28 01:20:39 PM PDT 24 201561705 ps
T434 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.800864174 Apr 28 01:20:16 PM PDT 24 Apr 28 01:21:45 PM PDT 24 1987679649 ps
T435 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4196458974 Apr 28 01:20:43 PM PDT 24 Apr 28 01:20:52 PM PDT 24 176110805 ps
T436 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2075431033 Apr 28 01:20:39 PM PDT 24 Apr 28 01:22:29 PM PDT 24 32965162835 ps
T437 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.512580702 Apr 28 01:20:36 PM PDT 24 Apr 28 01:20:58 PM PDT 24 4430713552 ps
T113 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2721932490 Apr 28 01:20:44 PM PDT 24 Apr 28 01:23:23 PM PDT 24 4642982644 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4049530169 Apr 28 01:20:15 PM PDT 24 Apr 28 01:20:42 PM PDT 24 6529645317 ps
T439 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.574538816 Apr 28 01:20:42 PM PDT 24 Apr 28 01:20:58 PM PDT 24 944507930 ps
T440 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.175014553 Apr 28 01:20:41 PM PDT 24 Apr 28 01:21:01 PM PDT 24 4384672726 ps
T441 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1758074764 Apr 28 01:20:39 PM PDT 24 Apr 28 01:22:12 PM PDT 24 9135390508 ps
T442 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4090919046 Apr 28 01:20:31 PM PDT 24 Apr 28 01:22:32 PM PDT 24 45157192313 ps
T443 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3654170060 Apr 28 01:20:11 PM PDT 24 Apr 28 01:21:46 PM PDT 24 9987433002 ps
T85 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.319850248 Apr 28 01:20:31 PM PDT 24 Apr 28 01:20:40 PM PDT 24 196426541 ps
T444 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2214806686 Apr 28 01:20:35 PM PDT 24 Apr 28 01:20:58 PM PDT 24 1541977604 ps
T445 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1536386914 Apr 28 01:20:42 PM PDT 24 Apr 28 01:21:19 PM PDT 24 4204251170 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2603852420 Apr 28 01:20:15 PM PDT 24 Apr 28 01:20:49 PM PDT 24 16972051303 ps
T447 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2217535865 Apr 28 01:20:36 PM PDT 24 Apr 28 01:21:05 PM PDT 24 3450282923 ps
T86 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2138410263 Apr 28 01:20:34 PM PDT 24 Apr 28 01:22:09 PM PDT 24 9804702545 ps
T448 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1177463778 Apr 28 01:20:26 PM PDT 24 Apr 28 01:20:55 PM PDT 24 7298020537 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3370385884 Apr 28 01:20:30 PM PDT 24 Apr 28 01:20:46 PM PDT 24 1161698332 ps

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2733993153
Short name T7
Test name
Test status
Simulation time 30123607974 ps
CPU time 8951.36 seconds
Started Apr 28 04:54:38 PM PDT 24
Finished Apr 28 07:23:52 PM PDT 24
Peak memory 236192 kb
Host smart-97714614-8061-4100-8fbd-5d6182de7065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733993153 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2733993153
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4251691266
Short name T1
Test name
Test status
Simulation time 407383014005 ps
CPU time 483.79 seconds
Started Apr 28 04:54:21 PM PDT 24
Finished Apr 28 05:02:26 PM PDT 24
Peak memory 217012 kb
Host smart-4534a871-b035-4b0d-adb8-b6624af4a26d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251691266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4251691266
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1258341242
Short name T12
Test name
Test status
Simulation time 1489111800 ps
CPU time 24.38 seconds
Started Apr 28 04:54:23 PM PDT 24
Finished Apr 28 04:54:48 PM PDT 24
Peak memory 215520 kb
Host smart-5691958c-c826-42ce-adbc-c393908109bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258341242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1258341242
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2773917904
Short name T53
Test name
Test status
Simulation time 4333761353 ps
CPU time 155.39 seconds
Started Apr 28 01:20:30 PM PDT 24
Finished Apr 28 01:23:06 PM PDT 24
Peak memory 213600 kb
Host smart-d9254768-6715-4394-bbaf-d1089fcb4754
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773917904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2773917904
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2236205353
Short name T24
Test name
Test status
Simulation time 16569152458 ps
CPU time 139 seconds
Started Apr 28 04:54:13 PM PDT 24
Finished Apr 28 04:56:33 PM PDT 24
Peak memory 237148 kb
Host smart-c18ccba9-d26b-4e54-8acc-c2b312f12649
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236205353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2236205353
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1648711787
Short name T61
Test name
Test status
Simulation time 5135098220 ps
CPU time 62.15 seconds
Started Apr 28 01:20:11 PM PDT 24
Finished Apr 28 01:21:14 PM PDT 24
Peak memory 213724 kb
Host smart-9f57f40d-5613-4343-bb33-31882b4c872b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648711787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1648711787
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1506204169
Short name T59
Test name
Test status
Simulation time 10717284348 ps
CPU time 19.76 seconds
Started Apr 28 04:54:47 PM PDT 24
Finished Apr 28 04:55:07 PM PDT 24
Peak memory 211708 kb
Host smart-3f33926c-6e3d-4379-89f9-211d22ff8b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506204169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1506204169
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.726550778
Short name T105
Test name
Test status
Simulation time 9008507745 ps
CPU time 169.94 seconds
Started Apr 28 01:20:45 PM PDT 24
Finished Apr 28 01:23:36 PM PDT 24
Peak memory 213648 kb
Host smart-b4a31fc3-dd27-46c7-a3c5-1157720e37d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726550778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.726550778
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2278853965
Short name T118
Test name
Test status
Simulation time 154885124811 ps
CPU time 796.45 seconds
Started Apr 28 04:54:40 PM PDT 24
Finished Apr 28 05:07:58 PM PDT 24
Peak memory 225992 kb
Host smart-71fba918-dc97-4c95-8630-55e963a20add
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278853965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2278853965
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4120706077
Short name T127
Test name
Test status
Simulation time 1308650112 ps
CPU time 29.07 seconds
Started Apr 28 04:56:04 PM PDT 24
Finished Apr 28 04:56:34 PM PDT 24
Peak memory 214016 kb
Host smart-37135075-4556-4a1e-bec4-37fce87e1d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120706077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4120706077
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2053052845
Short name T194
Test name
Test status
Simulation time 1322132193 ps
CPU time 19.45 seconds
Started Apr 28 04:54:16 PM PDT 24
Finished Apr 28 04:54:36 PM PDT 24
Peak memory 215048 kb
Host smart-778fc0af-3800-408e-a8d4-3dab63941167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053052845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2053052845
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3081059951
Short name T104
Test name
Test status
Simulation time 3838554923 ps
CPU time 97.33 seconds
Started Apr 28 01:20:39 PM PDT 24
Finished Apr 28 01:22:17 PM PDT 24
Peak memory 212600 kb
Host smart-1cc276c3-d8dd-447c-8e21-152259cd2a00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081059951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3081059951
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.248825930
Short name T18
Test name
Test status
Simulation time 267324305983 ps
CPU time 2528.44 seconds
Started Apr 28 04:56:03 PM PDT 24
Finished Apr 28 05:38:13 PM PDT 24
Peak memory 249584 kb
Host smart-d750c039-3d1f-457c-80b5-35a264590b3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248825930 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.248825930
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1201745604
Short name T72
Test name
Test status
Simulation time 5074380315 ps
CPU time 46.29 seconds
Started Apr 28 04:56:22 PM PDT 24
Finished Apr 28 04:57:08 PM PDT 24
Peak memory 220100 kb
Host smart-980477e8-2b7d-4fa3-93bd-59d4b0014e99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201745604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1201745604
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.572636360
Short name T55
Test name
Test status
Simulation time 169173905 ps
CPU time 8.2 seconds
Started Apr 28 01:20:13 PM PDT 24
Finished Apr 28 01:20:21 PM PDT 24
Peak memory 210564 kb
Host smart-0092a3d0-bc03-4f9d-91ff-eafdb5e4f594
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572636360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.572636360
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1074226518
Short name T102
Test name
Test status
Simulation time 3950927729 ps
CPU time 169.91 seconds
Started Apr 28 01:20:41 PM PDT 24
Finished Apr 28 01:23:32 PM PDT 24
Peak memory 214112 kb
Host smart-b100446b-5165-4512-a938-995e77e6bdb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074226518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1074226518
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3410867279
Short name T50
Test name
Test status
Simulation time 2604891877 ps
CPU time 78.88 seconds
Started Apr 28 01:20:34 PM PDT 24
Finished Apr 28 01:21:54 PM PDT 24
Peak memory 212940 kb
Host smart-e323db11-8358-4d86-9a07-a7df114463e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410867279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3410867279
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3416415836
Short name T125
Test name
Test status
Simulation time 2405336001 ps
CPU time 12.86 seconds
Started Apr 28 04:54:14 PM PDT 24
Finished Apr 28 04:54:27 PM PDT 24
Peak memory 211844 kb
Host smart-b7a00ea8-6ba2-427a-aee1-cd770c29b9e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3416415836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3416415836
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3452222245
Short name T75
Test name
Test status
Simulation time 20729673385 ps
CPU time 175.17 seconds
Started Apr 28 01:20:15 PM PDT 24
Finished Apr 28 01:23:11 PM PDT 24
Peak memory 214868 kb
Host smart-a2d0ae66-436a-4533-a1c9-ef1d483f4334
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452222245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3452222245
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4049530169
Short name T438
Test name
Test status
Simulation time 6529645317 ps
CPU time 27.06 seconds
Started Apr 28 01:20:15 PM PDT 24
Finished Apr 28 01:20:42 PM PDT 24
Peak memory 211004 kb
Host smart-e0143949-f358-43b0-b665-36057fc37b36
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049530169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4049530169
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1662565900
Short name T393
Test name
Test status
Simulation time 18321689890 ps
CPU time 18.86 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:30 PM PDT 24
Peak memory 211012 kb
Host smart-0999ff88-6dce-4808-b6bc-30ecab47c9bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662565900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1662565900
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3462912902
Short name T382
Test name
Test status
Simulation time 4137541664 ps
CPU time 17.97 seconds
Started Apr 28 01:20:14 PM PDT 24
Finished Apr 28 01:20:32 PM PDT 24
Peak memory 211300 kb
Host smart-593fa834-3b9a-4549-b086-595328a4aeb2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462912902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3462912902
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.277068594
Short name T407
Test name
Test status
Simulation time 15738690382 ps
CPU time 31.03 seconds
Started Apr 28 01:20:14 PM PDT 24
Finished Apr 28 01:20:46 PM PDT 24
Peak memory 215808 kb
Host smart-88da6e4d-e894-47ba-855b-4e6a6fab5d95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277068594 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.277068594
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2253787871
Short name T358
Test name
Test status
Simulation time 602281455 ps
CPU time 11.85 seconds
Started Apr 28 01:20:12 PM PDT 24
Finished Apr 28 01:20:25 PM PDT 24
Peak memory 210324 kb
Host smart-48bafa71-ed5e-4dc7-9671-47ced0e187b7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253787871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2253787871
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2479954284
Short name T362
Test name
Test status
Simulation time 185585149 ps
CPU time 8.1 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:19 PM PDT 24
Peak memory 210440 kb
Host smart-48b1cc41-8b57-4e0d-9fae-50a35dc859f6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479954284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2479954284
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3619434087
Short name T385
Test name
Test status
Simulation time 23168788393 ps
CPU time 32.3 seconds
Started Apr 28 01:20:14 PM PDT 24
Finished Apr 28 01:20:47 PM PDT 24
Peak memory 212028 kb
Host smart-1478757d-b0db-4e45-9716-d300bca727b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619434087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3619434087
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3328284823
Short name T381
Test name
Test status
Simulation time 325802242 ps
CPU time 12.69 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:24 PM PDT 24
Peak memory 218744 kb
Host smart-2f3d6e80-b83d-4b77-aa72-b6d94eb7d348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328284823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3328284823
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3654170060
Short name T443
Test name
Test status
Simulation time 9987433002 ps
CPU time 93.82 seconds
Started Apr 28 01:20:11 PM PDT 24
Finished Apr 28 01:21:46 PM PDT 24
Peak memory 213164 kb
Host smart-f5232172-9bbe-4a04-89b8-d5d3d163c686
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654170060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3654170060
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1052454292
Short name T429
Test name
Test status
Simulation time 167701003 ps
CPU time 8.17 seconds
Started Apr 28 01:20:22 PM PDT 24
Finished Apr 28 01:20:30 PM PDT 24
Peak memory 210500 kb
Host smart-e1ad850d-2025-438d-9fa1-37efa1479cbe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052454292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1052454292
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1321360358
Short name T415
Test name
Test status
Simulation time 368480083 ps
CPU time 8.43 seconds
Started Apr 28 01:20:25 PM PDT 24
Finished Apr 28 01:20:34 PM PDT 24
Peak memory 210436 kb
Host smart-38925371-8d6a-4331-b39e-f644ddbc2849
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321360358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1321360358
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3038373786
Short name T81
Test name
Test status
Simulation time 351133898 ps
CPU time 15.29 seconds
Started Apr 28 01:20:16 PM PDT 24
Finished Apr 28 01:20:32 PM PDT 24
Peak memory 210828 kb
Host smart-b1073851-c93d-409c-9a8c-3c5b7ceebf82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038373786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3038373786
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2622160944
Short name T404
Test name
Test status
Simulation time 4104782647 ps
CPU time 31 seconds
Started Apr 28 01:20:23 PM PDT 24
Finished Apr 28 01:20:54 PM PDT 24
Peak memory 215972 kb
Host smart-54d5a597-722d-4920-9cc0-1d1a00b5bf41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622160944 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2622160944
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3874290306
Short name T62
Test name
Test status
Simulation time 687923377 ps
CPU time 7.89 seconds
Started Apr 28 01:20:15 PM PDT 24
Finished Apr 28 01:20:23 PM PDT 24
Peak memory 210472 kb
Host smart-d5ec7fe6-434f-40df-98fb-fac2f606ada1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874290306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3874290306
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3433824226
Short name T417
Test name
Test status
Simulation time 3295857259 ps
CPU time 13.32 seconds
Started Apr 28 01:20:14 PM PDT 24
Finished Apr 28 01:20:28 PM PDT 24
Peak memory 210460 kb
Host smart-0c54221f-7b68-41d1-8840-cac453fe087c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433824226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3433824226
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2632880992
Short name T368
Test name
Test status
Simulation time 1372639763 ps
CPU time 8.08 seconds
Started Apr 28 01:20:16 PM PDT 24
Finished Apr 28 01:20:24 PM PDT 24
Peak memory 210352 kb
Host smart-8e8c651b-6a8c-4492-9a39-f5ce64891ca5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632880992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2632880992
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.725892906
Short name T88
Test name
Test status
Simulation time 5312307760 ps
CPU time 27.02 seconds
Started Apr 28 01:20:23 PM PDT 24
Finished Apr 28 01:20:50 PM PDT 24
Peak memory 211880 kb
Host smart-24b51db8-a415-468e-99f2-5c0f8289168d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725892906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.725892906
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2603852420
Short name T446
Test name
Test status
Simulation time 16972051303 ps
CPU time 33.24 seconds
Started Apr 28 01:20:15 PM PDT 24
Finished Apr 28 01:20:49 PM PDT 24
Peak memory 217064 kb
Host smart-5d311566-e664-4cf8-ac6d-4a1fec6a0afc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603852420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2603852420
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.800864174
Short name T434
Test name
Test status
Simulation time 1987679649 ps
CPU time 88.52 seconds
Started Apr 28 01:20:16 PM PDT 24
Finished Apr 28 01:21:45 PM PDT 24
Peak memory 212536 kb
Host smart-753a182d-5e49-4b0e-a44f-0980a162abb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800864174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.800864174
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2650780519
Short name T401
Test name
Test status
Simulation time 365606873 ps
CPU time 8.81 seconds
Started Apr 28 01:20:42 PM PDT 24
Finished Apr 28 01:20:52 PM PDT 24
Peak memory 216112 kb
Host smart-955ba6b3-a085-43ac-8bef-c7fc51134989
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650780519 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2650780519
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1735308176
Short name T77
Test name
Test status
Simulation time 660851237 ps
CPU time 8.25 seconds
Started Apr 28 01:20:41 PM PDT 24
Finished Apr 28 01:20:50 PM PDT 24
Peak memory 210488 kb
Host smart-4293be8f-e72a-40e9-a1a2-a5301c09345a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735308176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1735308176
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2479046078
Short name T388
Test name
Test status
Simulation time 12468364325 ps
CPU time 76.22 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:22:02 PM PDT 24
Peak memory 218804 kb
Host smart-f187f068-5ab2-4edc-86d7-c00937a3bf69
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479046078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2479046078
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3656351968
Short name T405
Test name
Test status
Simulation time 2940142615 ps
CPU time 15.99 seconds
Started Apr 28 01:20:46 PM PDT 24
Finished Apr 28 01:21:03 PM PDT 24
Peak memory 211556 kb
Host smart-6cc2a927-0aaf-4e2c-bb13-eedd9e50cd95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656351968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3656351968
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.600351159
Short name T386
Test name
Test status
Simulation time 8036264684 ps
CPU time 35.09 seconds
Started Apr 28 01:20:41 PM PDT 24
Finished Apr 28 01:21:17 PM PDT 24
Peak memory 216760 kb
Host smart-200aac40-3f48-4466-943a-c355feb9eab0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600351159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.600351159
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1250132897
Short name T109
Test name
Test status
Simulation time 13356617137 ps
CPU time 95.34 seconds
Started Apr 28 01:20:40 PM PDT 24
Finished Apr 28 01:22:17 PM PDT 24
Peak memory 213260 kb
Host smart-8424ffb9-aaef-4059-b9b5-18cb55bbfe0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250132897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1250132897
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4196458974
Short name T435
Test name
Test status
Simulation time 176110805 ps
CPU time 8.55 seconds
Started Apr 28 01:20:43 PM PDT 24
Finished Apr 28 01:20:52 PM PDT 24
Peak memory 214916 kb
Host smart-b0f83bbc-3b33-48c9-a75a-f8b20d42a7bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196458974 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4196458974
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1572293573
Short name T93
Test name
Test status
Simulation time 345561906 ps
CPU time 8.07 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:20:53 PM PDT 24
Peak memory 210484 kb
Host smart-5a104a0f-b267-4cae-bb61-bd9e6ce5d17f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572293573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1572293573
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.568442105
Short name T400
Test name
Test status
Simulation time 11148062608 ps
CPU time 103.21 seconds
Started Apr 28 01:20:46 PM PDT 24
Finished Apr 28 01:22:30 PM PDT 24
Peak memory 213780 kb
Host smart-46e1b3e9-a2f2-4464-9699-9712b8c91e40
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568442105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.568442105
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1094056372
Short name T419
Test name
Test status
Simulation time 7123794230 ps
CPU time 22.01 seconds
Started Apr 28 01:20:45 PM PDT 24
Finished Apr 28 01:21:09 PM PDT 24
Peak memory 211344 kb
Host smart-dbc12147-1674-4d74-b271-fa51f856bd81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094056372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1094056372
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3093929178
Short name T376
Test name
Test status
Simulation time 169299563 ps
CPU time 10.85 seconds
Started Apr 28 01:20:45 PM PDT 24
Finished Apr 28 01:20:57 PM PDT 24
Peak memory 216628 kb
Host smart-3355e144-cd23-4ef1-831c-3790b4c97537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093929178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3093929178
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.574538816
Short name T439
Test name
Test status
Simulation time 944507930 ps
CPU time 14.47 seconds
Started Apr 28 01:20:42 PM PDT 24
Finished Apr 28 01:20:58 PM PDT 24
Peak memory 212804 kb
Host smart-872d90e7-7461-481b-a7e6-dd80bd3fc876
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574538816 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.574538816
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.785507703
Short name T78
Test name
Test status
Simulation time 687147286 ps
CPU time 12.86 seconds
Started Apr 28 01:20:42 PM PDT 24
Finished Apr 28 01:20:56 PM PDT 24
Peak memory 210500 kb
Host smart-cb047610-a411-4493-8038-02cbc6e15941
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785507703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.785507703
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2237722409
Short name T95
Test name
Test status
Simulation time 43312379842 ps
CPU time 177.88 seconds
Started Apr 28 01:20:45 PM PDT 24
Finished Apr 28 01:23:44 PM PDT 24
Peak memory 214816 kb
Host smart-bc27dd4c-eab5-43de-a739-b4bf66cce314
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237722409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2237722409
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2776577471
Short name T394
Test name
Test status
Simulation time 26579140991 ps
CPU time 28.86 seconds
Started Apr 28 01:20:41 PM PDT 24
Finished Apr 28 01:21:11 PM PDT 24
Peak memory 211760 kb
Host smart-ff83569d-ccf1-468d-b920-81045caba1f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776577471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2776577471
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3570674679
Short name T371
Test name
Test status
Simulation time 688036009 ps
CPU time 12.89 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:20:58 PM PDT 24
Peak memory 217912 kb
Host smart-c09c5a55-7523-4367-817c-821bf3995a87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570674679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3570674679
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1168794465
Short name T421
Test name
Test status
Simulation time 2818187721 ps
CPU time 24.48 seconds
Started Apr 28 01:20:42 PM PDT 24
Finished Apr 28 01:21:08 PM PDT 24
Peak memory 216644 kb
Host smart-c5ed63bd-f720-4ba5-98d9-91b5f9a22264
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168794465 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1168794465
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1419872534
Short name T427
Test name
Test status
Simulation time 5637961457 ps
CPU time 13.71 seconds
Started Apr 28 01:20:40 PM PDT 24
Finished Apr 28 01:20:54 PM PDT 24
Peak memory 210712 kb
Host smart-58852538-743c-4e51-9d3f-8590d83d96d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419872534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1419872534
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2075431033
Short name T436
Test name
Test status
Simulation time 32965162835 ps
CPU time 109.25 seconds
Started Apr 28 01:20:39 PM PDT 24
Finished Apr 28 01:22:29 PM PDT 24
Peak memory 214684 kb
Host smart-38b52f53-f002-432e-8c3f-e8bbae9f6ae8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075431033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2075431033
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.855546083
Short name T424
Test name
Test status
Simulation time 364620771 ps
CPU time 11.9 seconds
Started Apr 28 01:20:40 PM PDT 24
Finished Apr 28 01:20:53 PM PDT 24
Peak memory 211572 kb
Host smart-14b6a043-f523-4353-8e32-6c3e703885d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855546083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.855546083
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.34351253
Short name T426
Test name
Test status
Simulation time 861893028 ps
CPU time 15.05 seconds
Started Apr 28 01:20:40 PM PDT 24
Finished Apr 28 01:20:56 PM PDT 24
Peak memory 216580 kb
Host smart-efed9489-2148-4225-8990-d850b38d1f22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34351253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.34351253
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1758074764
Short name T441
Test name
Test status
Simulation time 9135390508 ps
CPU time 92.4 seconds
Started Apr 28 01:20:39 PM PDT 24
Finished Apr 28 01:22:12 PM PDT 24
Peak memory 213160 kb
Host smart-518b1e50-b21b-4f41-b9d4-2e1bdb657311
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758074764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1758074764
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1881349718
Short name T370
Test name
Test status
Simulation time 786617972 ps
CPU time 8.67 seconds
Started Apr 28 01:20:38 PM PDT 24
Finished Apr 28 01:20:48 PM PDT 24
Peak memory 214788 kb
Host smart-239f20ab-dc94-4eae-a781-0e690c1f6339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881349718 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1881349718
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3735070376
Short name T65
Test name
Test status
Simulation time 13581262125 ps
CPU time 30.61 seconds
Started Apr 28 01:20:40 PM PDT 24
Finished Apr 28 01:21:11 PM PDT 24
Peak memory 211612 kb
Host smart-7c6686df-d0c7-4f0e-b597-7d048de0e787
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735070376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3735070376
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1853047247
Short name T396
Test name
Test status
Simulation time 4287922520 ps
CPU time 55.75 seconds
Started Apr 28 01:20:43 PM PDT 24
Finished Apr 28 01:21:39 PM PDT 24
Peak memory 215644 kb
Host smart-a1321bf2-c0ef-41fa-80b6-2f0378c159fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853047247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1853047247
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1701437923
Short name T63
Test name
Test status
Simulation time 13381508186 ps
CPU time 32.58 seconds
Started Apr 28 01:20:43 PM PDT 24
Finished Apr 28 01:21:17 PM PDT 24
Peak memory 211928 kb
Host smart-c046ceb4-b5c2-4b80-b34c-6e7a5f348e05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701437923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1701437923
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1536386914
Short name T445
Test name
Test status
Simulation time 4204251170 ps
CPU time 35.92 seconds
Started Apr 28 01:20:42 PM PDT 24
Finished Apr 28 01:21:19 PM PDT 24
Peak memory 216288 kb
Host smart-ae8d35b7-a529-4795-94a4-356502c69d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536386914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1536386914
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4122316756
Short name T103
Test name
Test status
Simulation time 3200739753 ps
CPU time 96.15 seconds
Started Apr 28 01:20:39 PM PDT 24
Finished Apr 28 01:22:16 PM PDT 24
Peak memory 212784 kb
Host smart-5e341662-f8e0-47c6-bf97-63bed44464bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122316756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.4122316756
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.558941023
Short name T364
Test name
Test status
Simulation time 682226282 ps
CPU time 8.32 seconds
Started Apr 28 01:20:45 PM PDT 24
Finished Apr 28 01:20:54 PM PDT 24
Peak memory 213668 kb
Host smart-7e71a8f4-e8c2-40a4-92e1-204cb5ed89b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558941023 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.558941023
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.175014553
Short name T440
Test name
Test status
Simulation time 4384672726 ps
CPU time 18.88 seconds
Started Apr 28 01:20:41 PM PDT 24
Finished Apr 28 01:21:01 PM PDT 24
Peak memory 211088 kb
Host smart-850c9c8c-a052-4956-94d1-75604996765e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175014553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.175014553
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4127148388
Short name T84
Test name
Test status
Simulation time 114069726139 ps
CPU time 198.83 seconds
Started Apr 28 01:20:39 PM PDT 24
Finished Apr 28 01:23:59 PM PDT 24
Peak memory 214872 kb
Host smart-6fc305d4-1e74-4968-be92-330eeb62a63a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127148388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4127148388
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.946513531
Short name T379
Test name
Test status
Simulation time 11538199675 ps
CPU time 23.36 seconds
Started Apr 28 01:20:43 PM PDT 24
Finished Apr 28 01:21:08 PM PDT 24
Peak memory 212180 kb
Host smart-4e870bcf-9bea-42fe-bda2-ce0d2d77a7e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946513531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.946513531
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2655035251
Short name T366
Test name
Test status
Simulation time 1452968343 ps
CPU time 19.72 seconds
Started Apr 28 01:20:40 PM PDT 24
Finished Apr 28 01:21:01 PM PDT 24
Peak memory 217588 kb
Host smart-2d477d3f-ccba-4b07-8784-3b968599f479
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655035251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2655035251
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1606772899
Short name T106
Test name
Test status
Simulation time 9262261028 ps
CPU time 165.08 seconds
Started Apr 28 01:20:40 PM PDT 24
Finished Apr 28 01:23:26 PM PDT 24
Peak memory 214624 kb
Host smart-45d2a5b2-350f-453e-bdfe-d05a0e0bb3f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606772899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1606772899
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3142461279
Short name T392
Test name
Test status
Simulation time 1446019041 ps
CPU time 8.58 seconds
Started Apr 28 01:20:46 PM PDT 24
Finished Apr 28 01:20:55 PM PDT 24
Peak memory 214888 kb
Host smart-9cfecdab-e337-4859-8972-cc312b438cc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142461279 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3142461279
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2747245140
Short name T66
Test name
Test status
Simulation time 4251748534 ps
CPU time 31.23 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:21:17 PM PDT 24
Peak memory 211308 kb
Host smart-306ad3f7-1209-4335-8eb8-60674875c12e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747245140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2747245140
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2658872161
Short name T380
Test name
Test status
Simulation time 15112050843 ps
CPU time 60.27 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:21:46 PM PDT 24
Peak memory 214020 kb
Host smart-496c8f59-b48c-4ad8-8a67-7779e1a0923f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658872161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2658872161
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.738627999
Short name T409
Test name
Test status
Simulation time 3797340481 ps
CPU time 29.68 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:21:14 PM PDT 24
Peak memory 211228 kb
Host smart-b606db49-0746-4214-8030-d9d14296beef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738627999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.738627999
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2240704287
Short name T408
Test name
Test status
Simulation time 56180621408 ps
CPU time 35.49 seconds
Started Apr 28 01:20:43 PM PDT 24
Finished Apr 28 01:21:20 PM PDT 24
Peak memory 218292 kb
Host smart-00a27136-ed06-4cf0-832c-e442043fd7a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240704287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2240704287
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.746294274
Short name T108
Test name
Test status
Simulation time 4356987431 ps
CPU time 102.16 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:22:28 PM PDT 24
Peak memory 212932 kb
Host smart-d38f7e23-e1c6-4c8a-85ab-37afaa173df9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746294274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.746294274
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3796733407
Short name T49
Test name
Test status
Simulation time 1333050031 ps
CPU time 8.24 seconds
Started Apr 28 01:20:48 PM PDT 24
Finished Apr 28 01:20:57 PM PDT 24
Peak memory 214848 kb
Host smart-4a4451ab-a3e2-4e98-be7a-9623af75b2be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796733407 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3796733407
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1741323443
Short name T64
Test name
Test status
Simulation time 10043579023 ps
CPU time 14.04 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:21:00 PM PDT 24
Peak memory 210616 kb
Host smart-4027bbf6-3ce9-4f2d-ad7f-e9514cac9b62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741323443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1741323443
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4095262044
Short name T54
Test name
Test status
Simulation time 4004765952 ps
CPU time 51.48 seconds
Started Apr 28 01:20:47 PM PDT 24
Finished Apr 28 01:21:39 PM PDT 24
Peak memory 213220 kb
Host smart-0916c463-fb66-41bc-91c3-ce8413467d98
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095262044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4095262044
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3557392612
Short name T68
Test name
Test status
Simulation time 14351539642 ps
CPU time 29.4 seconds
Started Apr 28 01:20:43 PM PDT 24
Finished Apr 28 01:21:13 PM PDT 24
Peak memory 212036 kb
Host smart-09f2fc44-5bda-4706-9ef2-12d611122e0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557392612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3557392612
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3350234575
Short name T398
Test name
Test status
Simulation time 25041729461 ps
CPU time 33.93 seconds
Started Apr 28 01:20:45 PM PDT 24
Finished Apr 28 01:21:20 PM PDT 24
Peak memory 218316 kb
Host smart-959b7be5-0bd7-4247-9a86-922abafe9461
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350234575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3350234575
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3901272317
Short name T110
Test name
Test status
Simulation time 12299462920 ps
CPU time 95.61 seconds
Started Apr 28 01:20:45 PM PDT 24
Finished Apr 28 01:22:22 PM PDT 24
Peak memory 213272 kb
Host smart-f4a77f6d-7b16-4714-ab97-2f3e7cdac07f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901272317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3901272317
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3128733830
Short name T361
Test name
Test status
Simulation time 950634563 ps
CPU time 13.5 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:20:59 PM PDT 24
Peak memory 218756 kb
Host smart-89418456-a87b-4580-bef3-45fb0a67c32d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128733830 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3128733830
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.756331556
Short name T74
Test name
Test status
Simulation time 2876093283 ps
CPU time 23.65 seconds
Started Apr 28 01:20:43 PM PDT 24
Finished Apr 28 01:21:07 PM PDT 24
Peak memory 211284 kb
Host smart-42711ad8-1696-4c26-967c-7c0b2a5926da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756331556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.756331556
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2961465344
Short name T383
Test name
Test status
Simulation time 7936420661 ps
CPU time 81.71 seconds
Started Apr 28 01:20:47 PM PDT 24
Finished Apr 28 01:22:10 PM PDT 24
Peak memory 214676 kb
Host smart-fa1eed82-f062-4b4a-a248-1d5e70941f61
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961465344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2961465344
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1049788431
Short name T90
Test name
Test status
Simulation time 2670498024 ps
CPU time 23.03 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:21:08 PM PDT 24
Peak memory 211652 kb
Host smart-43a854fc-94d2-415e-a9d7-ed527b8e697a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049788431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1049788431
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3730871432
Short name T425
Test name
Test status
Simulation time 169411571 ps
CPU time 11.12 seconds
Started Apr 28 01:20:45 PM PDT 24
Finished Apr 28 01:20:57 PM PDT 24
Peak memory 216260 kb
Host smart-52bcfc43-db08-4753-b84b-f924b3d4779a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730871432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3730871432
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.758290900
Short name T423
Test name
Test status
Simulation time 4822719310 ps
CPU time 16.04 seconds
Started Apr 28 01:20:49 PM PDT 24
Finished Apr 28 01:21:05 PM PDT 24
Peak memory 215904 kb
Host smart-8f9b0c72-f856-4cdb-b589-acb44bab5561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758290900 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.758290900
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2935139762
Short name T92
Test name
Test status
Simulation time 4027737539 ps
CPU time 29.87 seconds
Started Apr 28 01:20:43 PM PDT 24
Finished Apr 28 01:21:14 PM PDT 24
Peak memory 210944 kb
Host smart-9c6624c4-7d88-458f-931f-15d2b3fd1ae6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935139762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2935139762
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.940636154
Short name T101
Test name
Test status
Simulation time 80224077145 ps
CPU time 173.63 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:23:39 PM PDT 24
Peak memory 214772 kb
Host smart-c7fd1207-3d5d-4518-a477-c24e4752e904
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940636154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.940636154
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1784800591
Short name T390
Test name
Test status
Simulation time 1007400333 ps
CPU time 11.36 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:20:57 PM PDT 24
Peak memory 210544 kb
Host smart-f96857fe-37df-4332-813e-e8079c201f53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784800591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1784800591
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1110940279
Short name T60
Test name
Test status
Simulation time 6075206357 ps
CPU time 21.06 seconds
Started Apr 28 01:20:48 PM PDT 24
Finished Apr 28 01:21:09 PM PDT 24
Peak memory 217916 kb
Host smart-77882275-1533-4fff-b41d-f4699ca64f41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110940279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1110940279
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2721932490
Short name T113
Test name
Test status
Simulation time 4642982644 ps
CPU time 156.89 seconds
Started Apr 28 01:20:44 PM PDT 24
Finished Apr 28 01:23:23 PM PDT 24
Peak memory 214544 kb
Host smart-30afd9ec-74d3-4dbf-be03-25ff24b1b0ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721932490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2721932490
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.319850248
Short name T85
Test name
Test status
Simulation time 196426541 ps
CPU time 8.2 seconds
Started Apr 28 01:20:31 PM PDT 24
Finished Apr 28 01:20:40 PM PDT 24
Peak memory 210484 kb
Host smart-2349ba0d-e060-4813-83b0-6055666ce312
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319850248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.319850248
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3281818492
Short name T359
Test name
Test status
Simulation time 10723869525 ps
CPU time 22.79 seconds
Started Apr 28 01:20:26 PM PDT 24
Finished Apr 28 01:20:50 PM PDT 24
Peak memory 211160 kb
Host smart-dc3a4b2d-c075-4757-92d9-aea5f230301c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281818492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3281818492
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4164656499
Short name T94
Test name
Test status
Simulation time 3105115200 ps
CPU time 30.36 seconds
Started Apr 28 01:20:30 PM PDT 24
Finished Apr 28 01:21:00 PM PDT 24
Peak memory 210696 kb
Host smart-8ce5977a-c1ba-40df-9466-b98b87e7e398
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164656499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4164656499
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2188466747
Short name T369
Test name
Test status
Simulation time 1347421256 ps
CPU time 12.58 seconds
Started Apr 28 01:20:26 PM PDT 24
Finished Apr 28 01:20:39 PM PDT 24
Peak memory 214644 kb
Host smart-c98224de-2779-4c0c-af68-5895754326e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188466747 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2188466747
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3592096607
Short name T397
Test name
Test status
Simulation time 2747208701 ps
CPU time 12.47 seconds
Started Apr 28 01:20:26 PM PDT 24
Finished Apr 28 01:20:39 PM PDT 24
Peak memory 210604 kb
Host smart-02a24d0d-706e-4a6d-bfe6-2add1e5705ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592096607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3592096607
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.77686106
Short name T375
Test name
Test status
Simulation time 348657084 ps
CPU time 10.35 seconds
Started Apr 28 01:20:25 PM PDT 24
Finished Apr 28 01:20:37 PM PDT 24
Peak memory 210420 kb
Host smart-4b68a63e-27c8-43e3-9bab-73683d309a28
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77686106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_
mem_partial_access.77686106
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1288724815
Short name T431
Test name
Test status
Simulation time 4413910428 ps
CPU time 14.73 seconds
Started Apr 28 01:20:25 PM PDT 24
Finished Apr 28 01:20:40 PM PDT 24
Peak memory 210396 kb
Host smart-4eebac8b-36d6-4c22-aa0f-5334e840f9ad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288724815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1288724815
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3452278712
Short name T100
Test name
Test status
Simulation time 36545655132 ps
CPU time 127.45 seconds
Started Apr 28 01:20:23 PM PDT 24
Finished Apr 28 01:22:31 PM PDT 24
Peak memory 213784 kb
Host smart-5f50f341-89d4-4b19-af14-46cde1b31ae1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452278712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3452278712
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2484058199
Short name T416
Test name
Test status
Simulation time 835342249 ps
CPU time 13.43 seconds
Started Apr 28 01:20:27 PM PDT 24
Finished Apr 28 01:20:41 PM PDT 24
Peak memory 210516 kb
Host smart-96941cbf-ed34-4b96-8404-e02a9a02403a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484058199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2484058199
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2641200160
Short name T373
Test name
Test status
Simulation time 339255987 ps
CPU time 11.65 seconds
Started Apr 28 01:20:24 PM PDT 24
Finished Apr 28 01:20:36 PM PDT 24
Peak memory 218772 kb
Host smart-8c28429a-3956-4492-8e87-d36fe034c20e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641200160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2641200160
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.378670940
Short name T112
Test name
Test status
Simulation time 11650857402 ps
CPU time 89.1 seconds
Started Apr 28 01:20:27 PM PDT 24
Finished Apr 28 01:21:57 PM PDT 24
Peak memory 213268 kb
Host smart-1c984a3b-1812-4090-a812-47ab42c57beb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378670940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.378670940
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1599763002
Short name T372
Test name
Test status
Simulation time 4418906367 ps
CPU time 15.38 seconds
Started Apr 28 01:20:25 PM PDT 24
Finished Apr 28 01:20:42 PM PDT 24
Peak memory 210628 kb
Host smart-f1c3e982-fc10-4e1f-98de-e938c8d96466
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599763002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1599763002
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1483713041
Short name T432
Test name
Test status
Simulation time 11470791972 ps
CPU time 18.84 seconds
Started Apr 28 01:20:29 PM PDT 24
Finished Apr 28 01:20:48 PM PDT 24
Peak memory 218688 kb
Host smart-2dc280ef-9dd9-4694-87d1-d0b390e90cf0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483713041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1483713041
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3217107224
Short name T422
Test name
Test status
Simulation time 9720603000 ps
CPU time 38.62 seconds
Started Apr 28 01:20:31 PM PDT 24
Finished Apr 28 01:21:11 PM PDT 24
Peak memory 211756 kb
Host smart-7d40650e-b713-4229-ba61-048de09f16ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217107224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3217107224
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1639339296
Short name T389
Test name
Test status
Simulation time 8289689114 ps
CPU time 15.25 seconds
Started Apr 28 01:20:30 PM PDT 24
Finished Apr 28 01:20:46 PM PDT 24
Peak memory 214240 kb
Host smart-237119a7-53b7-4113-bcae-934385749a44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639339296 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1639339296
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1177463778
Short name T448
Test name
Test status
Simulation time 7298020537 ps
CPU time 28.25 seconds
Started Apr 28 01:20:26 PM PDT 24
Finished Apr 28 01:20:55 PM PDT 24
Peak memory 211536 kb
Host smart-3b5ee46d-3e98-463d-a293-461c2790e939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177463778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1177463778
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3225310165
Short name T360
Test name
Test status
Simulation time 17060878331 ps
CPU time 31.1 seconds
Started Apr 28 01:20:31 PM PDT 24
Finished Apr 28 01:21:02 PM PDT 24
Peak memory 210560 kb
Host smart-d7b38304-0226-49f7-92a9-43cd935b4703
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225310165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3225310165
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3099008914
Short name T414
Test name
Test status
Simulation time 3628383018 ps
CPU time 27.52 seconds
Started Apr 28 01:20:30 PM PDT 24
Finished Apr 28 01:20:59 PM PDT 24
Peak memory 210560 kb
Host smart-ebf3a89d-b4ce-41b8-8a0e-40d8d981a914
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099008914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3099008914
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4090919046
Short name T442
Test name
Test status
Simulation time 45157192313 ps
CPU time 120.48 seconds
Started Apr 28 01:20:31 PM PDT 24
Finished Apr 28 01:22:32 PM PDT 24
Peak memory 214820 kb
Host smart-89418826-7fa4-4533-8c85-5439809ebdd7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090919046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.4090919046
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2358157437
Short name T433
Test name
Test status
Simulation time 201561705 ps
CPU time 8.08 seconds
Started Apr 28 01:20:30 PM PDT 24
Finished Apr 28 01:20:39 PM PDT 24
Peak memory 210692 kb
Host smart-91bde69b-9e81-41c0-81b8-2d7cfaae6950
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358157437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2358157437
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3087452621
Short name T430
Test name
Test status
Simulation time 3617542752 ps
CPU time 24.11 seconds
Started Apr 28 01:20:26 PM PDT 24
Finished Apr 28 01:20:51 PM PDT 24
Peak memory 217816 kb
Host smart-51e6d75b-cdfe-4d16-946e-aa9b58da2725
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087452621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3087452621
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.693616713
Short name T76
Test name
Test status
Simulation time 5005703863 ps
CPU time 15.88 seconds
Started Apr 28 01:20:32 PM PDT 24
Finished Apr 28 01:20:48 PM PDT 24
Peak memory 211276 kb
Host smart-15222ac4-19d6-4ae2-9709-a69b718ef621
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693616713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.693616713
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3370385884
Short name T449
Test name
Test status
Simulation time 1161698332 ps
CPU time 15.69 seconds
Started Apr 28 01:20:30 PM PDT 24
Finished Apr 28 01:20:46 PM PDT 24
Peak memory 210500 kb
Host smart-4d4d69f8-edb4-4a6a-9d4f-064914175921
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370385884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3370385884
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2214806686
Short name T444
Test name
Test status
Simulation time 1541977604 ps
CPU time 22.76 seconds
Started Apr 28 01:20:35 PM PDT 24
Finished Apr 28 01:20:58 PM PDT 24
Peak memory 210820 kb
Host smart-e8e8a7a1-011f-4295-8f06-778ce8e6e0d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214806686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2214806686
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3442131601
Short name T406
Test name
Test status
Simulation time 19781285300 ps
CPU time 21.38 seconds
Started Apr 28 01:20:34 PM PDT 24
Finished Apr 28 01:20:57 PM PDT 24
Peak memory 217212 kb
Host smart-afd287c9-586c-4f82-aed7-a5a3afdee85a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442131601 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3442131601
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.736517586
Short name T402
Test name
Test status
Simulation time 167513189 ps
CPU time 8.13 seconds
Started Apr 28 01:20:35 PM PDT 24
Finished Apr 28 01:20:44 PM PDT 24
Peak memory 210388 kb
Host smart-b698405f-1145-49e0-a371-e1e8675a0b51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736517586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.736517586
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4243272535
Short name T399
Test name
Test status
Simulation time 13699218644 ps
CPU time 27.3 seconds
Started Apr 28 01:20:34 PM PDT 24
Finished Apr 28 01:21:03 PM PDT 24
Peak memory 210480 kb
Host smart-2970d755-0700-400f-97b1-d75580189c6c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243272535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.4243272535
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1908846426
Short name T411
Test name
Test status
Simulation time 10886135290 ps
CPU time 20.32 seconds
Started Apr 28 01:20:32 PM PDT 24
Finished Apr 28 01:20:53 PM PDT 24
Peak memory 210484 kb
Host smart-13809e37-ba71-4bd1-87e3-629f2d911ba0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908846426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1908846426
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.221731124
Short name T420
Test name
Test status
Simulation time 6239959748 ps
CPU time 74.45 seconds
Started Apr 28 01:20:28 PM PDT 24
Finished Apr 28 01:21:43 PM PDT 24
Peak memory 214832 kb
Host smart-f45ce301-96ba-46f6-9a41-f9b660e1b7c8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221731124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.221731124
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3428928930
Short name T391
Test name
Test status
Simulation time 1628472260 ps
CPU time 17.84 seconds
Started Apr 28 01:20:30 PM PDT 24
Finished Apr 28 01:20:49 PM PDT 24
Peak memory 210488 kb
Host smart-36360a50-0f74-4efb-8424-a5faad2909f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428928930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3428928930
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2396761546
Short name T367
Test name
Test status
Simulation time 167545866 ps
CPU time 11.25 seconds
Started Apr 28 01:20:25 PM PDT 24
Finished Apr 28 01:20:37 PM PDT 24
Peak memory 218712 kb
Host smart-5f99e864-9387-400b-806a-f6fc78c8d478
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396761546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2396761546
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.450549758
Short name T378
Test name
Test status
Simulation time 5044729500 ps
CPU time 87.98 seconds
Started Apr 28 01:20:31 PM PDT 24
Finished Apr 28 01:22:00 PM PDT 24
Peak memory 213348 kb
Host smart-94619e97-7224-456d-8bd4-90bd57640c05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450549758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.450549758
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2281596338
Short name T413
Test name
Test status
Simulation time 2964304283 ps
CPU time 13.46 seconds
Started Apr 28 01:20:34 PM PDT 24
Finished Apr 28 01:20:48 PM PDT 24
Peak memory 214180 kb
Host smart-03d58c43-0f83-427f-92d8-24d867b6b559
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281596338 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2281596338
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.940372869
Short name T374
Test name
Test status
Simulation time 3354403115 ps
CPU time 17.24 seconds
Started Apr 28 01:20:32 PM PDT 24
Finished Apr 28 01:20:50 PM PDT 24
Peak memory 211148 kb
Host smart-7d5ffddb-bf1f-4409-962f-db42c642f953
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940372869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.940372869
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3511537835
Short name T67
Test name
Test status
Simulation time 25333880392 ps
CPU time 198.2 seconds
Started Apr 28 01:20:32 PM PDT 24
Finished Apr 28 01:23:51 PM PDT 24
Peak memory 214824 kb
Host smart-8fec5ead-085f-4314-958e-6682872801ad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511537835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3511537835
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1631973556
Short name T428
Test name
Test status
Simulation time 1649374778 ps
CPU time 8.2 seconds
Started Apr 28 01:20:30 PM PDT 24
Finished Apr 28 01:20:39 PM PDT 24
Peak memory 210504 kb
Host smart-8bcd18db-86f0-4d2b-a897-3ecc130fc65e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631973556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1631973556
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.550699896
Short name T395
Test name
Test status
Simulation time 10903504612 ps
CPU time 27.26 seconds
Started Apr 28 01:20:31 PM PDT 24
Finished Apr 28 01:20:59 PM PDT 24
Peak memory 217168 kb
Host smart-b0a935f5-0cd2-41e7-91a0-04d509033d34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550699896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.550699896
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1772190380
Short name T418
Test name
Test status
Simulation time 10954289639 ps
CPU time 100.79 seconds
Started Apr 28 01:20:32 PM PDT 24
Finished Apr 28 01:22:13 PM PDT 24
Peak memory 213280 kb
Host smart-44cec19b-e14f-4e42-ac8f-14aa98075df1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772190380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1772190380
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1334831810
Short name T365
Test name
Test status
Simulation time 16805275903 ps
CPU time 27.02 seconds
Started Apr 28 01:20:36 PM PDT 24
Finished Apr 28 01:21:04 PM PDT 24
Peak memory 216740 kb
Host smart-08212f47-605f-425a-8e9c-8d3bd992aeeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334831810 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1334831810
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.835252499
Short name T79
Test name
Test status
Simulation time 3028728919 ps
CPU time 24.66 seconds
Started Apr 28 01:20:35 PM PDT 24
Finished Apr 28 01:21:01 PM PDT 24
Peak memory 210996 kb
Host smart-a7e0c9a3-6cfa-442b-8aa1-f562c42e85ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835252499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.835252499
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2138410263
Short name T86
Test name
Test status
Simulation time 9804702545 ps
CPU time 94.27 seconds
Started Apr 28 01:20:34 PM PDT 24
Finished Apr 28 01:22:09 PM PDT 24
Peak memory 213652 kb
Host smart-c993da5e-086d-4ec3-ab88-8e126f1e57c1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138410263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2138410263
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2255338422
Short name T89
Test name
Test status
Simulation time 17007562804 ps
CPU time 31.25 seconds
Started Apr 28 01:20:35 PM PDT 24
Finished Apr 28 01:21:07 PM PDT 24
Peak memory 218828 kb
Host smart-d338f278-156a-435f-8c73-455facf12312
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255338422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2255338422
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2980094129
Short name T412
Test name
Test status
Simulation time 3530438066 ps
CPU time 23.28 seconds
Started Apr 28 01:20:35 PM PDT 24
Finished Apr 28 01:20:59 PM PDT 24
Peak memory 218868 kb
Host smart-88514eca-45b1-42a9-8787-39b1ddc8d15f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980094129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2980094129
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2657754011
Short name T52
Test name
Test status
Simulation time 3064930836 ps
CPU time 82.02 seconds
Started Apr 28 01:20:36 PM PDT 24
Finished Apr 28 01:21:59 PM PDT 24
Peak memory 212476 kb
Host smart-d9abb05d-f1b7-465b-9052-91341051caaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657754011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2657754011
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2338986885
Short name T48
Test name
Test status
Simulation time 18287241333 ps
CPU time 31.24 seconds
Started Apr 28 01:20:35 PM PDT 24
Finished Apr 28 01:21:08 PM PDT 24
Peak memory 217628 kb
Host smart-2d522d67-388b-405c-aa82-c51335f16c50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338986885 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2338986885
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2217535865
Short name T447
Test name
Test status
Simulation time 3450282923 ps
CPU time 28.01 seconds
Started Apr 28 01:20:36 PM PDT 24
Finished Apr 28 01:21:05 PM PDT 24
Peak memory 210508 kb
Host smart-6bc29103-1553-43d5-84a6-7356a4d08ed7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217535865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2217535865
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2212837903
Short name T82
Test name
Test status
Simulation time 10676907046 ps
CPU time 116.38 seconds
Started Apr 28 01:20:37 PM PDT 24
Finished Apr 28 01:22:34 PM PDT 24
Peak memory 213808 kb
Host smart-0d51d8f1-3887-4331-830f-d62c258b75e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212837903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2212837903
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.512580702
Short name T437
Test name
Test status
Simulation time 4430713552 ps
CPU time 20.7 seconds
Started Apr 28 01:20:36 PM PDT 24
Finished Apr 28 01:20:58 PM PDT 24
Peak memory 211604 kb
Host smart-cdcf326c-ab21-4561-ac23-a2d6e35cb8b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512580702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.512580702
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3279363396
Short name T107
Test name
Test status
Simulation time 3864071331 ps
CPU time 157.76 seconds
Started Apr 28 01:20:34 PM PDT 24
Finished Apr 28 01:23:13 PM PDT 24
Peak memory 218792 kb
Host smart-a5cc8c23-99aa-42bb-a4fa-ccf250eae53e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279363396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3279363396
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3991163704
Short name T410
Test name
Test status
Simulation time 3941404479 ps
CPU time 31.2 seconds
Started Apr 28 01:20:36 PM PDT 24
Finished Apr 28 01:21:08 PM PDT 24
Peak memory 215844 kb
Host smart-acade93e-bfd8-4dda-9085-97478770f962
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991163704 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3991163704
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1728150570
Short name T87
Test name
Test status
Simulation time 2778354355 ps
CPU time 24.31 seconds
Started Apr 28 01:20:36 PM PDT 24
Finished Apr 28 01:21:01 PM PDT 24
Peak memory 211048 kb
Host smart-6e4bb17e-981f-4551-baee-613248949097
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728150570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1728150570
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3903663072
Short name T83
Test name
Test status
Simulation time 9075031312 ps
CPU time 106.06 seconds
Started Apr 28 01:20:38 PM PDT 24
Finished Apr 28 01:22:25 PM PDT 24
Peak memory 215036 kb
Host smart-3fde89da-e41f-4e88-8d6c-8a362643aeca
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903663072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3903663072
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2144288933
Short name T91
Test name
Test status
Simulation time 1037573688 ps
CPU time 18.06 seconds
Started Apr 28 01:20:35 PM PDT 24
Finished Apr 28 01:20:53 PM PDT 24
Peak memory 211784 kb
Host smart-f2b4e79e-55e4-47db-8471-307e3259b219
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144288933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2144288933
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1787688967
Short name T363
Test name
Test status
Simulation time 12650752878 ps
CPU time 30.7 seconds
Started Apr 28 01:20:35 PM PDT 24
Finished Apr 28 01:21:07 PM PDT 24
Peak memory 218264 kb
Host smart-6715a2ac-0500-4e33-9ab6-29e9e9840b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787688967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1787688967
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1777451863
Short name T403
Test name
Test status
Simulation time 1388814552 ps
CPU time 9.29 seconds
Started Apr 28 01:20:40 PM PDT 24
Finished Apr 28 01:20:50 PM PDT 24
Peak memory 218808 kb
Host smart-a551022e-c819-457a-86f3-1e68129940db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777451863 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1777451863
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2763916147
Short name T384
Test name
Test status
Simulation time 605999713 ps
CPU time 11.98 seconds
Started Apr 28 01:20:35 PM PDT 24
Finished Apr 28 01:20:47 PM PDT 24
Peak memory 210556 kb
Host smart-7c50ecdd-0808-45d3-8f01-0fe0bb678575
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763916147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2763916147
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3828617923
Short name T80
Test name
Test status
Simulation time 1083399860 ps
CPU time 56.4 seconds
Started Apr 28 01:20:35 PM PDT 24
Finished Apr 28 01:21:32 PM PDT 24
Peak memory 213656 kb
Host smart-cd0e8b26-90cd-43c3-b251-55cfdcf2b0da
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828617923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3828617923
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2520039908
Short name T387
Test name
Test status
Simulation time 2294814219 ps
CPU time 21.47 seconds
Started Apr 28 01:20:37 PM PDT 24
Finished Apr 28 01:20:59 PM PDT 24
Peak memory 211272 kb
Host smart-399e2439-d878-4e6f-9140-bb711e59ebc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520039908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2520039908
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3196381215
Short name T377
Test name
Test status
Simulation time 19523069511 ps
CPU time 21.36 seconds
Started Apr 28 01:20:37 PM PDT 24
Finished Apr 28 01:20:59 PM PDT 24
Peak memory 218116 kb
Host smart-4ec889bd-744c-4fd6-86ed-cdf53fefe78d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196381215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3196381215
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2833176766
Short name T111
Test name
Test status
Simulation time 239815104 ps
CPU time 80.73 seconds
Started Apr 28 01:20:36 PM PDT 24
Finished Apr 28 01:21:57 PM PDT 24
Peak memory 212996 kb
Host smart-94b3eb58-ec69-4845-a81c-4817a357ebf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833176766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2833176766
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.775725588
Short name T281
Test name
Test status
Simulation time 2854599962 ps
CPU time 17.78 seconds
Started Apr 28 04:54:13 PM PDT 24
Finished Apr 28 04:54:32 PM PDT 24
Peak memory 212184 kb
Host smart-1fdf39f9-fd16-4ac1-a7a7-c9c831031d06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775725588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.775725588
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1702016503
Short name T262
Test name
Test status
Simulation time 280215608456 ps
CPU time 384.62 seconds
Started Apr 28 04:54:13 PM PDT 24
Finished Apr 28 05:00:38 PM PDT 24
Peak memory 224980 kb
Host smart-22b39187-615c-4fea-b4e1-a6b3b95bf365
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702016503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1702016503
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4248679434
Short name T351
Test name
Test status
Simulation time 690131822 ps
CPU time 19.72 seconds
Started Apr 28 04:54:13 PM PDT 24
Finished Apr 28 04:54:33 PM PDT 24
Peak memory 215008 kb
Host smart-48928758-fd11-468f-afcd-d55d737b1b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248679434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4248679434
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2889593270
Short name T235
Test name
Test status
Simulation time 1661321218 ps
CPU time 13.67 seconds
Started Apr 28 04:54:14 PM PDT 24
Finished Apr 28 04:54:28 PM PDT 24
Peak memory 211540 kb
Host smart-a5845599-a117-4f26-a132-cf114ca944c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2889593270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2889593270
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3117555313
Short name T116
Test name
Test status
Simulation time 4949229318 ps
CPU time 56.26 seconds
Started Apr 28 04:54:17 PM PDT 24
Finished Apr 28 04:55:14 PM PDT 24
Peak memory 217144 kb
Host smart-77cec123-d450-4e26-a68f-fc88731920eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117555313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3117555313
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2471493783
Short name T275
Test name
Test status
Simulation time 13853010608 ps
CPU time 94.58 seconds
Started Apr 28 04:54:16 PM PDT 24
Finished Apr 28 04:55:51 PM PDT 24
Peak memory 217816 kb
Host smart-613ba913-6f86-4530-9887-b62f7ca70732
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471493783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2471493783
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2742046212
Short name T193
Test name
Test status
Simulation time 19814354144 ps
CPU time 34.66 seconds
Started Apr 28 04:54:17 PM PDT 24
Finished Apr 28 04:54:52 PM PDT 24
Peak memory 212492 kb
Host smart-c80706ea-9f17-43a2-8461-2bc952db96e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742046212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2742046212
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4024454799
Short name T310
Test name
Test status
Simulation time 38356062474 ps
CPU time 464.97 seconds
Started Apr 28 04:54:14 PM PDT 24
Finished Apr 28 05:02:00 PM PDT 24
Peak memory 240728 kb
Host smart-bf50d2ed-8db4-4125-ac85-7739357ce71e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024454799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4024454799
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1830671788
Short name T31
Test name
Test status
Simulation time 632674181 ps
CPU time 233.22 seconds
Started Apr 28 04:54:15 PM PDT 24
Finished Apr 28 04:58:09 PM PDT 24
Peak memory 239256 kb
Host smart-bad287c0-6d64-426b-8db6-e07eacc2c713
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830671788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1830671788
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.308899236
Short name T241
Test name
Test status
Simulation time 1435120698 ps
CPU time 21.09 seconds
Started Apr 28 04:54:14 PM PDT 24
Finished Apr 28 04:54:36 PM PDT 24
Peak memory 216980 kb
Host smart-d01c8786-5d91-44ef-90df-b2734816b2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308899236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.308899236
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4269679950
Short name T302
Test name
Test status
Simulation time 16017076101 ps
CPU time 152.03 seconds
Started Apr 28 04:54:15 PM PDT 24
Finished Apr 28 04:56:48 PM PDT 24
Peak memory 228268 kb
Host smart-c902794d-c916-403d-8a7f-8ad159e1ed78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269679950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4269679950
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.761568230
Short name T300
Test name
Test status
Simulation time 10753653842 ps
CPU time 25.01 seconds
Started Apr 28 04:54:29 PM PDT 24
Finished Apr 28 04:54:54 PM PDT 24
Peak memory 212572 kb
Host smart-addb2ad3-7547-4e59-9826-7e81f4aa6e00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761568230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.761568230
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3298018348
Short name T153
Test name
Test status
Simulation time 43410081545 ps
CPU time 167.84 seconds
Started Apr 28 04:54:37 PM PDT 24
Finished Apr 28 04:57:25 PM PDT 24
Peak memory 237156 kb
Host smart-cc903dcb-c4f7-4359-8473-775bd4052869
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298018348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3298018348
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1898609874
Short name T324
Test name
Test status
Simulation time 769193281 ps
CPU time 19.55 seconds
Started Apr 28 04:54:31 PM PDT 24
Finished Apr 28 04:54:51 PM PDT 24
Peak memory 215004 kb
Host smart-3f8250f8-05fa-46fe-acd7-8b3ef6aa33d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898609874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1898609874
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1838717156
Short name T115
Test name
Test status
Simulation time 33017529156 ps
CPU time 22.2 seconds
Started Apr 28 04:54:29 PM PDT 24
Finished Apr 28 04:54:51 PM PDT 24
Peak memory 211596 kb
Host smart-5fbaa046-4f78-465d-bc48-debc8ce74713
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1838717156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1838717156
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2815631888
Short name T138
Test name
Test status
Simulation time 710234885 ps
CPU time 20.26 seconds
Started Apr 28 04:54:27 PM PDT 24
Finished Apr 28 04:54:48 PM PDT 24
Peak memory 216740 kb
Host smart-19a495f8-f130-4629-9fd7-792d24a07490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815631888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2815631888
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1038177864
Short name T270
Test name
Test status
Simulation time 4499965713 ps
CPU time 45.28 seconds
Started Apr 28 04:54:31 PM PDT 24
Finished Apr 28 04:55:17 PM PDT 24
Peak memory 217212 kb
Host smart-b6f834e2-5693-4aaf-ba59-d86216a50aee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038177864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1038177864
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.4010338977
Short name T215
Test name
Test status
Simulation time 176269587 ps
CPU time 8.3 seconds
Started Apr 28 04:54:32 PM PDT 24
Finished Apr 28 04:54:41 PM PDT 24
Peak memory 211604 kb
Host smart-710cb5de-6792-424a-adfb-fe765939d4d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010338977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.4010338977
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.724557013
Short name T320
Test name
Test status
Simulation time 2197874277 ps
CPU time 19.1 seconds
Started Apr 28 04:54:30 PM PDT 24
Finished Apr 28 04:54:49 PM PDT 24
Peak memory 215080 kb
Host smart-474ef843-44ba-468a-a181-f844e2ff28d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724557013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.724557013
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4065460813
Short name T98
Test name
Test status
Simulation time 13824288651 ps
CPU time 24.51 seconds
Started Apr 28 04:54:30 PM PDT 24
Finished Apr 28 04:54:54 PM PDT 24
Peak memory 212092 kb
Host smart-c871910d-d5b6-4f4d-a96e-3dffe2912113
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4065460813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.4065460813
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1997987879
Short name T269
Test name
Test status
Simulation time 2152005909 ps
CPU time 35.14 seconds
Started Apr 28 04:54:30 PM PDT 24
Finished Apr 28 04:55:05 PM PDT 24
Peak memory 215968 kb
Host smart-8aae5e24-a3ef-4522-8754-cfdf0c5372c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997987879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1997987879
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3312757431
Short name T130
Test name
Test status
Simulation time 7179985163 ps
CPU time 80.7 seconds
Started Apr 28 04:54:30 PM PDT 24
Finished Apr 28 04:55:51 PM PDT 24
Peak memory 218704 kb
Host smart-d80ae50d-b22e-4077-a2f9-624f0d81cf06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312757431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3312757431
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3724891787
Short name T213
Test name
Test status
Simulation time 1500016117 ps
CPU time 8.37 seconds
Started Apr 28 04:54:32 PM PDT 24
Finished Apr 28 04:54:41 PM PDT 24
Peak memory 211604 kb
Host smart-d7cd3ef2-210b-4efc-8292-f21672c3db2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724891787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3724891787
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4185726296
Short name T143
Test name
Test status
Simulation time 24073866733 ps
CPU time 283.13 seconds
Started Apr 28 04:54:34 PM PDT 24
Finished Apr 28 04:59:18 PM PDT 24
Peak memory 240312 kb
Host smart-f1059628-468c-40db-9f42-899f31b4e9ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185726296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.4185726296
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2074780548
Short name T16
Test name
Test status
Simulation time 1320991925 ps
CPU time 19.77 seconds
Started Apr 28 04:54:32 PM PDT 24
Finished Apr 28 04:54:52 PM PDT 24
Peak memory 214924 kb
Host smart-58066ced-054e-4aef-a318-23e3a3f32a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074780548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2074780548
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.208435609
Short name T197
Test name
Test status
Simulation time 3242111255 ps
CPU time 25.84 seconds
Started Apr 28 04:54:32 PM PDT 24
Finished Apr 28 04:54:58 PM PDT 24
Peak memory 212856 kb
Host smart-8e4aca3f-eea4-4a0e-8599-fbbbb4680bdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=208435609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.208435609
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3797403992
Short name T40
Test name
Test status
Simulation time 7016284951 ps
CPU time 67.11 seconds
Started Apr 28 04:54:30 PM PDT 24
Finished Apr 28 04:55:38 PM PDT 24
Peak memory 217780 kb
Host smart-0867f7ba-b117-4c11-9775-fc952e328115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797403992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3797403992
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.849323979
Short name T119
Test name
Test status
Simulation time 11804787113 ps
CPU time 123.66 seconds
Started Apr 28 04:54:31 PM PDT 24
Finished Apr 28 04:56:35 PM PDT 24
Peak memory 216060 kb
Host smart-d786e394-03c2-4812-8758-fdf9f2251d86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849323979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.849323979
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3987381973
Short name T354
Test name
Test status
Simulation time 7992932625 ps
CPU time 32.87 seconds
Started Apr 28 04:54:33 PM PDT 24
Finished Apr 28 04:55:06 PM PDT 24
Peak memory 212428 kb
Host smart-ace77ab0-78f3-4789-b4f3-94c8bfc64d37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987381973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3987381973
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1006777280
Short name T333
Test name
Test status
Simulation time 96456775096 ps
CPU time 865.27 seconds
Started Apr 28 04:54:33 PM PDT 24
Finished Apr 28 05:08:59 PM PDT 24
Peak memory 228144 kb
Host smart-6ff4e845-51bc-440b-8b25-7b9ea6fcd4a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006777280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1006777280
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3490907313
Short name T350
Test name
Test status
Simulation time 4101323354 ps
CPU time 44.35 seconds
Started Apr 28 04:54:33 PM PDT 24
Finished Apr 28 04:55:18 PM PDT 24
Peak memory 215192 kb
Host smart-d6388e0d-5d6a-4faa-b03b-b5fcbbfd032e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490907313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3490907313
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4083368791
Short name T151
Test name
Test status
Simulation time 2233633473 ps
CPU time 23.79 seconds
Started Apr 28 04:54:34 PM PDT 24
Finished Apr 28 04:54:58 PM PDT 24
Peak memory 211580 kb
Host smart-0df1a487-8605-4c39-82cd-ad274a14db7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4083368791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4083368791
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3389385181
Short name T70
Test name
Test status
Simulation time 1367039601 ps
CPU time 21.15 seconds
Started Apr 28 04:54:32 PM PDT 24
Finished Apr 28 04:54:53 PM PDT 24
Peak memory 216176 kb
Host smart-b6fe8961-e44a-42bd-b085-3a9d9023cb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389385181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3389385181
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2275193800
Short name T309
Test name
Test status
Simulation time 13456960248 ps
CPU time 157.47 seconds
Started Apr 28 04:54:34 PM PDT 24
Finished Apr 28 04:57:12 PM PDT 24
Peak memory 221836 kb
Host smart-35af1e95-b60e-4ddd-851c-400a415e3c41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275193800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2275193800
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2335843160
Short name T253
Test name
Test status
Simulation time 4250551853 ps
CPU time 20.59 seconds
Started Apr 28 04:54:38 PM PDT 24
Finished Apr 28 04:54:59 PM PDT 24
Peak memory 212172 kb
Host smart-8dcab030-d1b8-43a4-8747-b3f838e401af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335843160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2335843160
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3353381199
Short name T211
Test name
Test status
Simulation time 150815218799 ps
CPU time 387.1 seconds
Started Apr 28 04:54:35 PM PDT 24
Finished Apr 28 05:01:02 PM PDT 24
Peak memory 238280 kb
Host smart-43d072bb-de29-462c-99bf-c3619054b2ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353381199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3353381199
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2394414443
Short name T4
Test name
Test status
Simulation time 9839835850 ps
CPU time 48.02 seconds
Started Apr 28 04:54:38 PM PDT 24
Finished Apr 28 04:55:27 PM PDT 24
Peak memory 215336 kb
Host smart-6e8b775f-f4e1-4009-95a2-778bb9c1e688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394414443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2394414443
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2367085485
Short name T126
Test name
Test status
Simulation time 15430104471 ps
CPU time 34.58 seconds
Started Apr 28 04:54:33 PM PDT 24
Finished Apr 28 04:55:08 PM PDT 24
Peak memory 212084 kb
Host smart-c62ac8bd-4dfe-4c14-b912-e4cdda466eb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2367085485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2367085485
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3420081096
Short name T182
Test name
Test status
Simulation time 1356939795 ps
CPU time 28.31 seconds
Started Apr 28 04:54:34 PM PDT 24
Finished Apr 28 04:55:03 PM PDT 24
Peak memory 217556 kb
Host smart-af2b693c-ec59-4022-97aa-daa1957a41eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420081096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3420081096
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.4233005547
Short name T214
Test name
Test status
Simulation time 2640533316 ps
CPU time 28.83 seconds
Started Apr 28 04:54:34 PM PDT 24
Finished Apr 28 04:55:03 PM PDT 24
Peak memory 213736 kb
Host smart-c7a7943f-a101-4a23-ae3d-be24d159fde1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233005547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.4233005547
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1726564289
Short name T29
Test name
Test status
Simulation time 1988634864 ps
CPU time 15.69 seconds
Started Apr 28 04:54:38 PM PDT 24
Finished Apr 28 04:54:55 PM PDT 24
Peak memory 211564 kb
Host smart-55dac497-ab36-45be-9d11-4c675c927602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726564289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1726564289
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.684558097
Short name T223
Test name
Test status
Simulation time 33264798648 ps
CPU time 379.86 seconds
Started Apr 28 04:54:39 PM PDT 24
Finished Apr 28 05:01:00 PM PDT 24
Peak memory 235172 kb
Host smart-5d287d80-1a5b-4749-8131-88dabd9540be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684558097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.684558097
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3763631135
Short name T278
Test name
Test status
Simulation time 14389155809 ps
CPU time 41.74 seconds
Started Apr 28 04:54:38 PM PDT 24
Finished Apr 28 04:55:21 PM PDT 24
Peak memory 215380 kb
Host smart-5f00cdce-5ce2-44ee-944e-7853117d52cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763631135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3763631135
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1721235197
Short name T140
Test name
Test status
Simulation time 15722737854 ps
CPU time 32.35 seconds
Started Apr 28 04:54:38 PM PDT 24
Finished Apr 28 04:55:12 PM PDT 24
Peak memory 212032 kb
Host smart-556ee2ac-2c60-4154-a186-1ddabfa1be7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1721235197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1721235197
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2802322901
Short name T199
Test name
Test status
Simulation time 43368634742 ps
CPU time 61.49 seconds
Started Apr 28 04:54:40 PM PDT 24
Finished Apr 28 04:55:42 PM PDT 24
Peak memory 218332 kb
Host smart-243ea310-7bac-4220-b96d-d587144d7d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802322901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2802322901
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.880057850
Short name T11
Test name
Test status
Simulation time 21591322192 ps
CPU time 186.81 seconds
Started Apr 28 04:54:38 PM PDT 24
Finished Apr 28 04:57:46 PM PDT 24
Peak memory 227872 kb
Host smart-53273bee-208d-4bae-98f1-f36fb232a032
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880057850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.880057850
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.660730027
Short name T239
Test name
Test status
Simulation time 15688898925 ps
CPU time 32.54 seconds
Started Apr 28 04:54:38 PM PDT 24
Finished Apr 28 04:55:12 PM PDT 24
Peak memory 212180 kb
Host smart-7aea51b6-805e-4ec3-9234-9c702f05fe7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660730027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.660730027
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2630131130
Short name T9
Test name
Test status
Simulation time 560960593640 ps
CPU time 963.87 seconds
Started Apr 28 04:54:39 PM PDT 24
Finished Apr 28 05:10:44 PM PDT 24
Peak memory 229076 kb
Host smart-b26cc09a-859c-437f-970d-e3689285d8a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630131130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2630131130
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1617505490
Short name T250
Test name
Test status
Simulation time 332133146 ps
CPU time 19.04 seconds
Started Apr 28 04:54:38 PM PDT 24
Finished Apr 28 04:54:58 PM PDT 24
Peak memory 214972 kb
Host smart-ed873638-d05c-4952-948e-9279e8575514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617505490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1617505490
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1994114270
Short name T264
Test name
Test status
Simulation time 182489047 ps
CPU time 10.46 seconds
Started Apr 28 04:54:38 PM PDT 24
Finished Apr 28 04:54:50 PM PDT 24
Peak memory 212484 kb
Host smart-a2c45944-9794-4b30-816e-008fa8e63436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1994114270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1994114270
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.305234991
Short name T221
Test name
Test status
Simulation time 361709509 ps
CPU time 21.21 seconds
Started Apr 28 04:54:39 PM PDT 24
Finished Apr 28 04:55:01 PM PDT 24
Peak memory 217080 kb
Host smart-54a51b3e-dad7-434c-a99e-ac316d3cfcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305234991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.305234991
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.95639308
Short name T2
Test name
Test status
Simulation time 2959802170 ps
CPU time 48.1 seconds
Started Apr 28 04:54:36 PM PDT 24
Finished Apr 28 04:55:25 PM PDT 24
Peak memory 219704 kb
Host smart-77bcc33c-4422-4677-a1ae-61d11b400a1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95639308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 16.rom_ctrl_stress_all.95639308
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.406432866
Short name T291
Test name
Test status
Simulation time 169421297 ps
CPU time 8.66 seconds
Started Apr 28 04:54:46 PM PDT 24
Finished Apr 28 04:54:55 PM PDT 24
Peak memory 211692 kb
Host smart-634fa50a-e927-41d9-b1a4-a3d28416a076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406432866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.406432866
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2374819562
Short name T322
Test name
Test status
Simulation time 62095925587 ps
CPU time 381.98 seconds
Started Apr 28 04:54:45 PM PDT 24
Finished Apr 28 05:01:07 PM PDT 24
Peak memory 217312 kb
Host smart-552450bb-fd41-4325-b84a-0ad01b32b056
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374819562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2374819562
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.508173272
Short name T299
Test name
Test status
Simulation time 29585109876 ps
CPU time 65.59 seconds
Started Apr 28 04:54:45 PM PDT 24
Finished Apr 28 04:55:51 PM PDT 24
Peak memory 215252 kb
Host smart-76839740-7307-42f6-a81c-9c45a804ed98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508173272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.508173272
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2177939745
Short name T124
Test name
Test status
Simulation time 22422580591 ps
CPU time 34.97 seconds
Started Apr 28 04:54:43 PM PDT 24
Finished Apr 28 04:55:18 PM PDT 24
Peak memory 213180 kb
Host smart-b9226a04-70ba-44c4-a6a9-ccbb662bb87e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177939745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2177939745
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.150663057
Short name T229
Test name
Test status
Simulation time 351282439 ps
CPU time 20.96 seconds
Started Apr 28 04:54:38 PM PDT 24
Finished Apr 28 04:55:01 PM PDT 24
Peak memory 217484 kb
Host smart-d5fdf052-ad61-4f2a-977d-e491c1b7c662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150663057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.150663057
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3492480520
Short name T35
Test name
Test status
Simulation time 27714506186 ps
CPU time 80.41 seconds
Started Apr 28 04:54:37 PM PDT 24
Finished Apr 28 04:55:58 PM PDT 24
Peak memory 216036 kb
Host smart-397b605f-94e6-4fc6-8f93-7f9327f83139
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492480520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3492480520
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1528061339
Short name T248
Test name
Test status
Simulation time 4237674646 ps
CPU time 32.75 seconds
Started Apr 28 04:54:42 PM PDT 24
Finished Apr 28 04:55:15 PM PDT 24
Peak memory 212212 kb
Host smart-f98294c6-7473-4172-8ec0-619aa2445ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528061339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1528061339
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.707005251
Short name T38
Test name
Test status
Simulation time 7555205700 ps
CPU time 65.8 seconds
Started Apr 28 04:54:43 PM PDT 24
Finished Apr 28 04:55:49 PM PDT 24
Peak memory 215264 kb
Host smart-d74402a4-e999-4eaa-9033-181a1b95bfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707005251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.707005251
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.206400509
Short name T220
Test name
Test status
Simulation time 184347290 ps
CPU time 10.8 seconds
Started Apr 28 04:54:44 PM PDT 24
Finished Apr 28 04:54:55 PM PDT 24
Peak memory 212736 kb
Host smart-e6f0929b-a79b-409b-9d2a-e8640bd48de9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=206400509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.206400509
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.384427599
Short name T157
Test name
Test status
Simulation time 28225986651 ps
CPU time 31.56 seconds
Started Apr 28 04:54:45 PM PDT 24
Finished Apr 28 04:55:17 PM PDT 24
Peak memory 217592 kb
Host smart-0d89d099-0c2d-4aa0-90ab-56e5c43425d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384427599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.384427599
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1733034929
Short name T288
Test name
Test status
Simulation time 2159587738 ps
CPU time 31.01 seconds
Started Apr 28 04:54:44 PM PDT 24
Finished Apr 28 04:55:15 PM PDT 24
Peak memory 219716 kb
Host smart-a7717c68-9f8c-4b29-a4b9-341b3f063fd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733034929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1733034929
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3165899737
Short name T290
Test name
Test status
Simulation time 268567541374 ps
CPU time 675.91 seconds
Started Apr 28 04:54:50 PM PDT 24
Finished Apr 28 05:06:07 PM PDT 24
Peak memory 251332 kb
Host smart-566ad3b4-3932-4228-a5a3-e20eec6255db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165899737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3165899737
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2641072119
Short name T255
Test name
Test status
Simulation time 4620163679 ps
CPU time 46.61 seconds
Started Apr 28 04:54:46 PM PDT 24
Finished Apr 28 04:55:33 PM PDT 24
Peak memory 215592 kb
Host smart-629b2d91-66bb-4b14-9e65-8865e23b362a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641072119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2641072119
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3578187976
Short name T276
Test name
Test status
Simulation time 22341549112 ps
CPU time 25.86 seconds
Started Apr 28 04:54:43 PM PDT 24
Finished Apr 28 04:55:09 PM PDT 24
Peak memory 212164 kb
Host smart-c2488920-bf5b-4d7c-990f-f54592767c28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3578187976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3578187976
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3579284545
Short name T6
Test name
Test status
Simulation time 13329394617 ps
CPU time 58.54 seconds
Started Apr 28 04:54:42 PM PDT 24
Finished Apr 28 04:55:41 PM PDT 24
Peak memory 217372 kb
Host smart-5a319c20-2ecc-44c7-becb-672f8bcf906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579284545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3579284545
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4053731594
Short name T176
Test name
Test status
Simulation time 3257583575 ps
CPU time 60.98 seconds
Started Apr 28 04:54:45 PM PDT 24
Finished Apr 28 04:55:47 PM PDT 24
Peak memory 219272 kb
Host smart-53e5f10d-58eb-4989-b270-0342d1a58b20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053731594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4053731594
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3816545849
Short name T146
Test name
Test status
Simulation time 3298619879 ps
CPU time 8.32 seconds
Started Apr 28 04:54:25 PM PDT 24
Finished Apr 28 04:54:34 PM PDT 24
Peak memory 211704 kb
Host smart-f8dace2c-c0fa-4fc6-a85c-17f161e9b14c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816545849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3816545849
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.713640381
Short name T15
Test name
Test status
Simulation time 8454779077 ps
CPU time 349.34 seconds
Started Apr 28 04:54:14 PM PDT 24
Finished Apr 28 05:00:04 PM PDT 24
Peak memory 219652 kb
Host smart-9c70bc51-a4f6-4e05-afc9-407339b0f8c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713640381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.713640381
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3182741837
Short name T334
Test name
Test status
Simulation time 487346202 ps
CPU time 18.96 seconds
Started Apr 28 04:54:17 PM PDT 24
Finished Apr 28 04:54:37 PM PDT 24
Peak memory 214896 kb
Host smart-1791b97a-b4a2-453a-98d4-5e23b2bc4ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182741837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3182741837
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.704293530
Short name T249
Test name
Test status
Simulation time 11491768085 ps
CPU time 30.31 seconds
Started Apr 28 04:54:13 PM PDT 24
Finished Apr 28 04:54:44 PM PDT 24
Peak memory 211968 kb
Host smart-5e3d288d-1c7f-4528-a3b3-f9d9257858db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704293530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.704293530
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3687277845
Short name T26
Test name
Test status
Simulation time 11008696521 ps
CPU time 239.82 seconds
Started Apr 28 04:54:24 PM PDT 24
Finished Apr 28 04:58:25 PM PDT 24
Peak memory 238800 kb
Host smart-3e7d8468-498c-4a78-a7fa-d96bbde7936b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687277845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3687277845
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2588584186
Short name T37
Test name
Test status
Simulation time 5503277185 ps
CPU time 30.26 seconds
Started Apr 28 04:54:14 PM PDT 24
Finished Apr 28 04:54:45 PM PDT 24
Peak memory 217528 kb
Host smart-dc056065-ec3b-475f-be20-cdbef17e8d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588584186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2588584186
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3773054659
Short name T343
Test name
Test status
Simulation time 856281577 ps
CPU time 38.71 seconds
Started Apr 28 04:54:15 PM PDT 24
Finished Apr 28 04:54:55 PM PDT 24
Peak memory 219564 kb
Host smart-578373f6-93ab-429a-8e97-b86e8f55a71b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773054659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3773054659
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1520339752
Short name T36
Test name
Test status
Simulation time 164704876580 ps
CPU time 3452.38 seconds
Started Apr 28 04:54:24 PM PDT 24
Finished Apr 28 05:51:58 PM PDT 24
Peak memory 260784 kb
Host smart-07b29f08-980f-49c7-8596-9cde19650e2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520339752 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1520339752
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.411013706
Short name T326
Test name
Test status
Simulation time 847228671 ps
CPU time 14.19 seconds
Started Apr 28 04:54:50 PM PDT 24
Finished Apr 28 04:55:05 PM PDT 24
Peak memory 211692 kb
Host smart-732879f4-d488-4a7e-81d6-6d93f86c66ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411013706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.411013706
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1155971323
Short name T41
Test name
Test status
Simulation time 2374404410 ps
CPU time 163.07 seconds
Started Apr 28 04:54:46 PM PDT 24
Finished Apr 28 04:57:30 PM PDT 24
Peak memory 237632 kb
Host smart-1c6a700a-3556-4e5a-a446-2ea55d66708e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155971323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1155971323
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1119920753
Short name T218
Test name
Test status
Simulation time 30697867334 ps
CPU time 60.97 seconds
Started Apr 28 04:54:47 PM PDT 24
Finished Apr 28 04:55:48 PM PDT 24
Peak memory 215452 kb
Host smart-0bf835f4-1310-46d2-af38-1ea9ef3309a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119920753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1119920753
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2533920386
Short name T338
Test name
Test status
Simulation time 4433663121 ps
CPU time 33.77 seconds
Started Apr 28 04:54:46 PM PDT 24
Finished Apr 28 04:55:20 PM PDT 24
Peak memory 212884 kb
Host smart-699afba6-97bf-4855-9e9f-0a3a3f4a17d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533920386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2533920386
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3198254089
Short name T154
Test name
Test status
Simulation time 1435446989 ps
CPU time 20.43 seconds
Started Apr 28 04:54:45 PM PDT 24
Finished Apr 28 04:55:06 PM PDT 24
Peak memory 217920 kb
Host smart-e134288e-5c59-4623-9568-bf14b1323e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198254089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3198254089
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2358608757
Short name T305
Test name
Test status
Simulation time 2152282481 ps
CPU time 37.28 seconds
Started Apr 28 04:54:48 PM PDT 24
Finished Apr 28 04:55:26 PM PDT 24
Peak memory 219052 kb
Host smart-ecc17f70-7c9a-4ddd-9757-3cc22bb0b738
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358608757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2358608757
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.953567093
Short name T323
Test name
Test status
Simulation time 689299822 ps
CPU time 8.57 seconds
Started Apr 28 04:54:46 PM PDT 24
Finished Apr 28 04:54:55 PM PDT 24
Peak memory 211624 kb
Host smart-0c0947cd-7c7f-4fc3-95f9-1d308c3ddbd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953567093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.953567093
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2908346484
Short name T168
Test name
Test status
Simulation time 72478586358 ps
CPU time 734.46 seconds
Started Apr 28 04:55:04 PM PDT 24
Finished Apr 28 05:07:19 PM PDT 24
Peak memory 234324 kb
Host smart-461e5c9a-9fe7-46f4-8777-320bd59284d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908346484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2908346484
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1504523715
Short name T34
Test name
Test status
Simulation time 28096340562 ps
CPU time 60.36 seconds
Started Apr 28 04:54:48 PM PDT 24
Finished Apr 28 04:55:48 PM PDT 24
Peak memory 215460 kb
Host smart-e889ba04-0165-4ed5-9548-26f0abc33813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504523715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1504523715
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1289004398
Short name T225
Test name
Test status
Simulation time 11656695532 ps
CPU time 27.12 seconds
Started Apr 28 04:54:45 PM PDT 24
Finished Apr 28 04:55:13 PM PDT 24
Peak memory 212188 kb
Host smart-c8dbabf6-a000-46a6-bb9c-95115585888e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289004398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1289004398
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.216325642
Short name T263
Test name
Test status
Simulation time 8668196481 ps
CPU time 93.88 seconds
Started Apr 28 04:54:48 PM PDT 24
Finished Apr 28 04:56:22 PM PDT 24
Peak memory 217208 kb
Host smart-f78081d4-960e-4077-a41a-a5c522a7a616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216325642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.216325642
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3701192501
Short name T313
Test name
Test status
Simulation time 595011538 ps
CPU time 31.48 seconds
Started Apr 28 04:54:45 PM PDT 24
Finished Apr 28 04:55:17 PM PDT 24
Peak memory 219636 kb
Host smart-01044ca3-dc6a-4540-82fe-7c5bdba4f068
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701192501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3701192501
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2604586755
Short name T329
Test name
Test status
Simulation time 3006938393 ps
CPU time 24.96 seconds
Started Apr 28 04:54:53 PM PDT 24
Finished Apr 28 04:55:18 PM PDT 24
Peak memory 212240 kb
Host smart-6798ddcd-0e9e-4a8a-a4dd-dc4f6f5dfc30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604586755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2604586755
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3851977472
Short name T222
Test name
Test status
Simulation time 73405015155 ps
CPU time 218.48 seconds
Started Apr 28 04:54:51 PM PDT 24
Finished Apr 28 04:58:30 PM PDT 24
Peak memory 216964 kb
Host smart-b599798a-a11c-4b47-8805-89a1051881f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851977472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3851977472
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3430078802
Short name T340
Test name
Test status
Simulation time 345956804 ps
CPU time 19.37 seconds
Started Apr 28 04:54:50 PM PDT 24
Finished Apr 28 04:55:11 PM PDT 24
Peak memory 214908 kb
Host smart-6c84277c-f79a-4faa-858f-21b917421ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430078802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3430078802
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3119592940
Short name T344
Test name
Test status
Simulation time 20011316695 ps
CPU time 19.76 seconds
Started Apr 28 04:54:49 PM PDT 24
Finished Apr 28 04:55:10 PM PDT 24
Peak memory 212088 kb
Host smart-33abcd88-9ba9-4fe7-a187-bff3c9d81760
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3119592940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3119592940
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3633019175
Short name T311
Test name
Test status
Simulation time 849117083 ps
CPU time 26.48 seconds
Started Apr 28 04:54:47 PM PDT 24
Finished Apr 28 04:55:14 PM PDT 24
Peak memory 217588 kb
Host smart-642a73ae-6a5a-45c6-867b-63aa4973dbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633019175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3633019175
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1908568065
Short name T200
Test name
Test status
Simulation time 15483045168 ps
CPU time 37.02 seconds
Started Apr 28 04:54:50 PM PDT 24
Finished Apr 28 04:55:28 PM PDT 24
Peak memory 213260 kb
Host smart-94c2280c-6f58-4a13-8718-cc6a6bcbcfa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908568065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1908568065
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.957069057
Short name T188
Test name
Test status
Simulation time 10923931148 ps
CPU time 24.33 seconds
Started Apr 28 04:54:50 PM PDT 24
Finished Apr 28 04:55:15 PM PDT 24
Peak memory 212436 kb
Host smart-18d113cb-714d-4b1b-9d20-26ac4e511be9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957069057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.957069057
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3894381672
Short name T228
Test name
Test status
Simulation time 71091026881 ps
CPU time 511.24 seconds
Started Apr 28 04:54:51 PM PDT 24
Finished Apr 28 05:03:23 PM PDT 24
Peak memory 240068 kb
Host smart-af195e01-0ac3-4cdf-9d56-3e44e15352d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894381672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3894381672
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.4030347292
Short name T170
Test name
Test status
Simulation time 32739817313 ps
CPU time 34.28 seconds
Started Apr 28 04:54:51 PM PDT 24
Finished Apr 28 04:55:26 PM PDT 24
Peak memory 215428 kb
Host smart-f032ce6d-f8cb-410b-b95b-cbe9a71d3643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030347292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.4030347292
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1046401061
Short name T306
Test name
Test status
Simulation time 13568547520 ps
CPU time 30.25 seconds
Started Apr 28 04:54:50 PM PDT 24
Finished Apr 28 04:55:22 PM PDT 24
Peak memory 212056 kb
Host smart-cac8c80a-9fa1-4a47-b85c-2975effa58e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046401061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1046401061
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.894278852
Short name T180
Test name
Test status
Simulation time 71593997462 ps
CPU time 56.82 seconds
Started Apr 28 04:54:50 PM PDT 24
Finished Apr 28 04:55:47 PM PDT 24
Peak memory 217900 kb
Host smart-55e23f59-55ac-4f20-94b7-fd9f287354c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894278852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.894278852
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2751563562
Short name T149
Test name
Test status
Simulation time 715700175 ps
CPU time 44.16 seconds
Started Apr 28 04:54:50 PM PDT 24
Finished Apr 28 04:55:35 PM PDT 24
Peak memory 219616 kb
Host smart-51bb2b5f-4a04-4f47-b241-13953c3ad561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751563562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2751563562
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.635105335
Short name T273
Test name
Test status
Simulation time 591181346 ps
CPU time 8.5 seconds
Started Apr 28 04:54:54 PM PDT 24
Finished Apr 28 04:55:03 PM PDT 24
Peak memory 211560 kb
Host smart-f2306c6a-2ce5-408c-ae40-65c21e273aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635105335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.635105335
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.892644872
Short name T44
Test name
Test status
Simulation time 235568587404 ps
CPU time 540.38 seconds
Started Apr 28 04:54:53 PM PDT 24
Finished Apr 28 05:03:55 PM PDT 24
Peak memory 241184 kb
Host smart-bb4c21f4-51d6-4ed4-938e-079ec5ce2fe6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892644872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.892644872
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1316813266
Short name T186
Test name
Test status
Simulation time 7116501203 ps
CPU time 61.34 seconds
Started Apr 28 04:54:55 PM PDT 24
Finished Apr 28 04:55:57 PM PDT 24
Peak memory 215360 kb
Host smart-7725642d-dcf1-4db2-ac95-30a80d03b2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316813266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1316813266
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1653231123
Short name T128
Test name
Test status
Simulation time 9062467438 ps
CPU time 30.38 seconds
Started Apr 28 04:54:56 PM PDT 24
Finished Apr 28 04:55:27 PM PDT 24
Peak memory 211624 kb
Host smart-28ebb3d3-a557-497d-a97e-ebbc7d88d470
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653231123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1653231123
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3103693764
Short name T261
Test name
Test status
Simulation time 1433738518 ps
CPU time 20.46 seconds
Started Apr 28 04:54:51 PM PDT 24
Finished Apr 28 04:55:12 PM PDT 24
Peak memory 218200 kb
Host smart-86fd46ad-c267-4ab9-adfd-2bf146a89c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103693764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3103693764
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4185342224
Short name T163
Test name
Test status
Simulation time 7089987178 ps
CPU time 67.11 seconds
Started Apr 28 04:54:52 PM PDT 24
Finished Apr 28 04:55:59 PM PDT 24
Peak memory 217288 kb
Host smart-05ee512d-1909-42b7-8da3-49d1573f2f47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185342224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4185342224
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3904942036
Short name T317
Test name
Test status
Simulation time 825844876 ps
CPU time 8.51 seconds
Started Apr 28 04:54:53 PM PDT 24
Finished Apr 28 04:55:02 PM PDT 24
Peak memory 211644 kb
Host smart-bbf12021-5bec-4f2b-85e2-3efcfe8eadef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904942036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3904942036
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2595720415
Short name T5
Test name
Test status
Simulation time 17968884111 ps
CPU time 356.65 seconds
Started Apr 28 04:54:54 PM PDT 24
Finished Apr 28 05:00:51 PM PDT 24
Peak memory 241216 kb
Host smart-c4271021-4a88-458f-9fcc-d018dac90723
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595720415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2595720415
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.421591411
Short name T353
Test name
Test status
Simulation time 990677734 ps
CPU time 27.11 seconds
Started Apr 28 04:54:54 PM PDT 24
Finished Apr 28 04:55:22 PM PDT 24
Peak memory 214948 kb
Host smart-e04b6c19-9b0c-4c18-b67f-7655d24c7475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421591411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.421591411
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.383967838
Short name T209
Test name
Test status
Simulation time 3541820850 ps
CPU time 28.98 seconds
Started Apr 28 04:54:53 PM PDT 24
Finished Apr 28 04:55:22 PM PDT 24
Peak memory 211536 kb
Host smart-30b14ff1-388c-473c-a60b-32b145c92103
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=383967838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.383967838
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2404409193
Short name T345
Test name
Test status
Simulation time 29694719672 ps
CPU time 65.39 seconds
Started Apr 28 04:54:53 PM PDT 24
Finished Apr 28 04:55:59 PM PDT 24
Peak memory 218248 kb
Host smart-4f27687c-b80c-4c21-a5d8-a2008e7eee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404409193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2404409193
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3061899737
Short name T355
Test name
Test status
Simulation time 102252473774 ps
CPU time 208.19 seconds
Started Apr 28 04:54:55 PM PDT 24
Finished Apr 28 04:58:24 PM PDT 24
Peak memory 222832 kb
Host smart-33fee4b8-910d-4f79-abf3-64ddce34c643
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061899737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3061899737
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3614652519
Short name T13
Test name
Test status
Simulation time 246595073262 ps
CPU time 2677.34 seconds
Started Apr 28 04:54:55 PM PDT 24
Finished Apr 28 05:39:33 PM PDT 24
Peak memory 232168 kb
Host smart-9e43fbfc-9fbb-4dcc-bc44-920c2b72d93c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614652519 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3614652519
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2954408691
Short name T134
Test name
Test status
Simulation time 169191036 ps
CPU time 8.47 seconds
Started Apr 28 04:54:57 PM PDT 24
Finished Apr 28 04:55:05 PM PDT 24
Peak memory 211600 kb
Host smart-05056ed9-a65a-40a1-8c44-1a3e31d0717d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954408691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2954408691
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3557256956
Short name T129
Test name
Test status
Simulation time 9740826008 ps
CPU time 206.87 seconds
Started Apr 28 04:54:57 PM PDT 24
Finished Apr 28 04:58:25 PM PDT 24
Peak memory 219140 kb
Host smart-9e907f3f-299e-4c74-b4ca-79ef26129201
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557256956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3557256956
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3497957528
Short name T191
Test name
Test status
Simulation time 8317105409 ps
CPU time 63.82 seconds
Started Apr 28 04:54:57 PM PDT 24
Finished Apr 28 04:56:02 PM PDT 24
Peak memory 215696 kb
Host smart-8cec6051-7881-4b3f-bc57-97307a80f48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497957528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3497957528
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2531883846
Short name T258
Test name
Test status
Simulation time 1799948802 ps
CPU time 20.7 seconds
Started Apr 28 04:54:56 PM PDT 24
Finished Apr 28 04:55:17 PM PDT 24
Peak memory 211676 kb
Host smart-86484b89-81ae-4f0f-8d03-0a12fd037d60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531883846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2531883846
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2290983080
Short name T137
Test name
Test status
Simulation time 6155556530 ps
CPU time 62.95 seconds
Started Apr 28 04:54:55 PM PDT 24
Finished Apr 28 04:55:58 PM PDT 24
Peak memory 218460 kb
Host smart-f6a4a4db-6386-4d6c-b5a4-2c6750d5c309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290983080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2290983080
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1545391743
Short name T14
Test name
Test status
Simulation time 27217563864 ps
CPU time 71.98 seconds
Started Apr 28 04:54:56 PM PDT 24
Finished Apr 28 04:56:08 PM PDT 24
Peak memory 219644 kb
Host smart-b10642e6-49db-49eb-9441-b8706c809aca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545391743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1545391743
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1854270421
Short name T181
Test name
Test status
Simulation time 507310225 ps
CPU time 10.4 seconds
Started Apr 28 04:55:01 PM PDT 24
Finished Apr 28 04:55:12 PM PDT 24
Peak memory 211584 kb
Host smart-d1a169bd-2d2c-47ef-9fe7-e7a6437628d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854270421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1854270421
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2069047298
Short name T141
Test name
Test status
Simulation time 188829490155 ps
CPU time 843.62 seconds
Started Apr 28 04:54:59 PM PDT 24
Finished Apr 28 05:09:03 PM PDT 24
Peak memory 240496 kb
Host smart-7a9f590b-6111-4c66-85ca-9dce5969923f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069047298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2069047298
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3511247766
Short name T172
Test name
Test status
Simulation time 3415090520 ps
CPU time 26.3 seconds
Started Apr 28 04:54:58 PM PDT 24
Finished Apr 28 04:55:24 PM PDT 24
Peak memory 213928 kb
Host smart-d4ecd367-240c-483b-bc47-ab205fc70f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511247766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3511247766
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2480381657
Short name T277
Test name
Test status
Simulation time 7816140763 ps
CPU time 31.12 seconds
Started Apr 28 04:54:57 PM PDT 24
Finished Apr 28 04:55:29 PM PDT 24
Peak memory 212804 kb
Host smart-06367a9b-873b-49d7-9be8-13c0971684ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2480381657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2480381657
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.620336177
Short name T230
Test name
Test status
Simulation time 353466792 ps
CPU time 20.37 seconds
Started Apr 28 04:54:59 PM PDT 24
Finished Apr 28 04:55:19 PM PDT 24
Peak memory 217872 kb
Host smart-df9a9082-5f1e-4da0-b26b-a5e035edd51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620336177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.620336177
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3777780959
Short name T174
Test name
Test status
Simulation time 6840258527 ps
CPU time 63.82 seconds
Started Apr 28 04:54:58 PM PDT 24
Finished Apr 28 04:56:02 PM PDT 24
Peak memory 218592 kb
Host smart-63f0dd24-2d69-4bc4-86fb-655b4712353c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777780959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3777780959
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1632680320
Short name T321
Test name
Test status
Simulation time 7684393588 ps
CPU time 16.48 seconds
Started Apr 28 04:55:02 PM PDT 24
Finished Apr 28 04:55:19 PM PDT 24
Peak memory 212484 kb
Host smart-08e87ae3-180a-4ee9-b0fd-325441f4e226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632680320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1632680320
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.531474184
Short name T139
Test name
Test status
Simulation time 1471117238 ps
CPU time 105.5 seconds
Started Apr 28 04:55:02 PM PDT 24
Finished Apr 28 04:56:48 PM PDT 24
Peak memory 240456 kb
Host smart-e63d79b5-e98c-4f84-b3ab-066080f73aa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531474184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.531474184
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3369965186
Short name T247
Test name
Test status
Simulation time 15781415500 ps
CPU time 44.52 seconds
Started Apr 28 04:55:01 PM PDT 24
Finished Apr 28 04:55:46 PM PDT 24
Peak memory 215276 kb
Host smart-55c41b33-4838-4f2c-90e7-a763cebe578c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369965186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3369965186
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3823209810
Short name T294
Test name
Test status
Simulation time 696738143 ps
CPU time 10.58 seconds
Started Apr 28 04:55:04 PM PDT 24
Finished Apr 28 04:55:14 PM PDT 24
Peak memory 211920 kb
Host smart-7b75bdaf-21e6-43cb-9e42-196a50ccc0b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823209810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3823209810
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2547406422
Short name T192
Test name
Test status
Simulation time 15119701384 ps
CPU time 42.28 seconds
Started Apr 28 04:55:03 PM PDT 24
Finished Apr 28 04:55:46 PM PDT 24
Peak memory 216004 kb
Host smart-b20e57fc-a909-4521-9f2d-eafe6d4f9046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547406422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2547406422
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3905591270
Short name T224
Test name
Test status
Simulation time 876479085 ps
CPU time 55.11 seconds
Started Apr 28 04:55:02 PM PDT 24
Finished Apr 28 04:55:57 PM PDT 24
Peak memory 219612 kb
Host smart-2c73ac04-38cb-4894-886b-d842fe4bec17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905591270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3905591270
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2939399884
Short name T178
Test name
Test status
Simulation time 3005978094 ps
CPU time 26.42 seconds
Started Apr 28 04:55:07 PM PDT 24
Finished Apr 28 04:55:34 PM PDT 24
Peak memory 211596 kb
Host smart-9015a7e4-5858-46ce-a81d-773d093eb434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939399884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2939399884
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.215989240
Short name T22
Test name
Test status
Simulation time 2471592788 ps
CPU time 29.74 seconds
Started Apr 28 04:55:03 PM PDT 24
Finished Apr 28 04:55:33 PM PDT 24
Peak memory 215212 kb
Host smart-079fb1a8-7603-4458-bc69-b4bcbaaf107f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215989240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.215989240
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1874768970
Short name T97
Test name
Test status
Simulation time 1546440889 ps
CPU time 19.45 seconds
Started Apr 28 04:55:03 PM PDT 24
Finished Apr 28 04:55:23 PM PDT 24
Peak memory 211588 kb
Host smart-1bf5802e-f178-414a-9359-d56eb3639e50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1874768970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1874768970
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1906049045
Short name T201
Test name
Test status
Simulation time 2871388401 ps
CPU time 20.55 seconds
Started Apr 28 04:55:02 PM PDT 24
Finished Apr 28 04:55:23 PM PDT 24
Peak memory 217860 kb
Host smart-fe60e08d-e702-4e08-8236-9b2788b29eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906049045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1906049045
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2606403067
Short name T183
Test name
Test status
Simulation time 32893975786 ps
CPU time 100.13 seconds
Started Apr 28 04:55:02 PM PDT 24
Finished Apr 28 04:56:42 PM PDT 24
Peak memory 219680 kb
Host smart-9b132683-f2de-4393-8025-e1c067ec284e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606403067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2606403067
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4074556787
Short name T308
Test name
Test status
Simulation time 3042677066 ps
CPU time 25.86 seconds
Started Apr 28 04:54:19 PM PDT 24
Finished Apr 28 04:54:45 PM PDT 24
Peak memory 212252 kb
Host smart-c12461d0-f679-45f7-8e10-f24a05602bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074556787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4074556787
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3863999213
Short name T348
Test name
Test status
Simulation time 3182520287 ps
CPU time 199.48 seconds
Started Apr 28 04:54:22 PM PDT 24
Finished Apr 28 04:57:42 PM PDT 24
Peak memory 238288 kb
Host smart-391610c4-98b9-44b0-b8a3-e5e4fdce4ac3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863999213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3863999213
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2167993593
Short name T271
Test name
Test status
Simulation time 1815229215 ps
CPU time 31.47 seconds
Started Apr 28 04:54:24 PM PDT 24
Finished Apr 28 04:54:56 PM PDT 24
Peak memory 215480 kb
Host smart-7842e126-2e71-4cdd-9255-db5bd3644871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167993593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2167993593
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2225457166
Short name T297
Test name
Test status
Simulation time 185102854 ps
CPU time 10.56 seconds
Started Apr 28 04:54:18 PM PDT 24
Finished Apr 28 04:54:29 PM PDT 24
Peak memory 212836 kb
Host smart-15fd2a82-1b6a-4be6-a059-42e4cb8885d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2225457166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2225457166
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1004226308
Short name T32
Test name
Test status
Simulation time 1459935205 ps
CPU time 117.96 seconds
Started Apr 28 04:54:19 PM PDT 24
Finished Apr 28 04:56:17 PM PDT 24
Peak memory 239856 kb
Host smart-1d59e03f-801c-4bfd-bfc2-1b9a998ce620
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004226308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1004226308
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1662290152
Short name T3
Test name
Test status
Simulation time 3069261974 ps
CPU time 20.16 seconds
Started Apr 28 04:54:19 PM PDT 24
Finished Apr 28 04:54:40 PM PDT 24
Peak memory 218456 kb
Host smart-f2b0f667-7006-40b4-b0b6-cf5fbdd92adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662290152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1662290152
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2784119677
Short name T356
Test name
Test status
Simulation time 36044709688 ps
CPU time 56.29 seconds
Started Apr 28 04:54:21 PM PDT 24
Finished Apr 28 04:55:18 PM PDT 24
Peak memory 217792 kb
Host smart-d6b89b2a-98c6-4bdf-a72b-121f4b2f3a1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784119677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2784119677
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2000999991
Short name T27
Test name
Test status
Simulation time 44352269884 ps
CPU time 33.73 seconds
Started Apr 28 04:55:08 PM PDT 24
Finished Apr 28 04:55:42 PM PDT 24
Peak memory 212428 kb
Host smart-b35bff72-adc2-4794-b4e9-43db86151bdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000999991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2000999991
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2901494838
Short name T175
Test name
Test status
Simulation time 111515149495 ps
CPU time 403.82 seconds
Started Apr 28 04:55:06 PM PDT 24
Finished Apr 28 05:01:50 PM PDT 24
Peak memory 217296 kb
Host smart-37cd0f0a-69f0-4d01-8862-c926b4207d10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901494838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2901494838
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4021342089
Short name T133
Test name
Test status
Simulation time 1222198203 ps
CPU time 27.51 seconds
Started Apr 28 04:55:07 PM PDT 24
Finished Apr 28 04:55:34 PM PDT 24
Peak memory 214892 kb
Host smart-2c9b4fb8-7975-4e2e-b41f-914fd829a0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021342089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4021342089
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1060959036
Short name T187
Test name
Test status
Simulation time 913743182 ps
CPU time 16.15 seconds
Started Apr 28 04:55:07 PM PDT 24
Finished Apr 28 04:55:23 PM PDT 24
Peak memory 212456 kb
Host smart-1e81e599-f7f5-4080-a134-aacfda6216f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1060959036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1060959036
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1904674143
Short name T205
Test name
Test status
Simulation time 13966036522 ps
CPU time 41.55 seconds
Started Apr 28 04:55:06 PM PDT 24
Finished Apr 28 04:55:48 PM PDT 24
Peak memory 218440 kb
Host smart-f4c2f158-350e-4e8d-9067-89a8f8e8b000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904674143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1904674143
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.401180962
Short name T96
Test name
Test status
Simulation time 2017383176 ps
CPU time 53.95 seconds
Started Apr 28 04:55:09 PM PDT 24
Finished Apr 28 04:56:03 PM PDT 24
Peak memory 219624 kb
Host smart-498943bd-1a58-4521-8f0d-a46c9c30f2e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401180962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.401180962
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.326051389
Short name T169
Test name
Test status
Simulation time 174483151 ps
CPU time 8.49 seconds
Started Apr 28 04:55:10 PM PDT 24
Finished Apr 28 04:55:19 PM PDT 24
Peak memory 211584 kb
Host smart-9a0c95d6-bbb4-4538-b633-012500bd39dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326051389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.326051389
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1960930001
Short name T244
Test name
Test status
Simulation time 193326580617 ps
CPU time 948.08 seconds
Started Apr 28 04:55:10 PM PDT 24
Finished Apr 28 05:10:59 PM PDT 24
Peak memory 234476 kb
Host smart-797d79b9-311c-4ce5-b082-d94ac0638566
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960930001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1960930001
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1157741341
Short name T231
Test name
Test status
Simulation time 27227092667 ps
CPU time 59.9 seconds
Started Apr 28 04:55:11 PM PDT 24
Finished Apr 28 04:56:11 PM PDT 24
Peak memory 215352 kb
Host smart-e0908426-c901-411e-ad88-f0a6f5873285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157741341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1157741341
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1991189387
Short name T196
Test name
Test status
Simulation time 412118437 ps
CPU time 10.64 seconds
Started Apr 28 04:55:10 PM PDT 24
Finished Apr 28 04:55:21 PM PDT 24
Peak memory 212896 kb
Host smart-6d7f7223-9038-4486-ae70-7bb36137a50d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991189387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1991189387
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1113587911
Short name T51
Test name
Test status
Simulation time 14218084362 ps
CPU time 50.7 seconds
Started Apr 28 04:55:10 PM PDT 24
Finished Apr 28 04:56:02 PM PDT 24
Peak memory 218200 kb
Host smart-e20a82ca-a2ed-4a89-80ce-07c581900c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113587911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1113587911
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1469325669
Short name T237
Test name
Test status
Simulation time 3868819391 ps
CPU time 31.12 seconds
Started Apr 28 04:55:09 PM PDT 24
Finished Apr 28 04:55:41 PM PDT 24
Peak memory 217852 kb
Host smart-8e50f97c-3bfe-41fc-a819-d6af09c7ef5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469325669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1469325669
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3518090981
Short name T347
Test name
Test status
Simulation time 4241278607 ps
CPU time 16.05 seconds
Started Apr 28 04:55:13 PM PDT 24
Finished Apr 28 04:55:30 PM PDT 24
Peak memory 211708 kb
Host smart-d2f483b8-441d-43b6-a071-c7dc48f6c0a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518090981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3518090981
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3630316025
Short name T337
Test name
Test status
Simulation time 29290722227 ps
CPU time 389.45 seconds
Started Apr 28 04:55:10 PM PDT 24
Finished Apr 28 05:01:40 PM PDT 24
Peak memory 229776 kb
Host smart-d0201326-cedd-4b03-833a-23a60452102b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630316025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3630316025
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2897555300
Short name T287
Test name
Test status
Simulation time 17043158929 ps
CPU time 68.79 seconds
Started Apr 28 04:55:10 PM PDT 24
Finished Apr 28 04:56:19 PM PDT 24
Peak memory 215436 kb
Host smart-dd6bb34d-9f79-4af8-9062-85aca5c70b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897555300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2897555300
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.440435924
Short name T123
Test name
Test status
Simulation time 2460462226 ps
CPU time 23.46 seconds
Started Apr 28 04:55:10 PM PDT 24
Finished Apr 28 04:55:34 PM PDT 24
Peak memory 211664 kb
Host smart-14e04f94-6fd1-4ee5-8535-6adb9c1ad4bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440435924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.440435924
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.122923074
Short name T73
Test name
Test status
Simulation time 356815080 ps
CPU time 20.05 seconds
Started Apr 28 04:55:10 PM PDT 24
Finished Apr 28 04:55:30 PM PDT 24
Peak memory 213772 kb
Host smart-2f710b20-bdb5-4b30-9512-8ed7c00a4e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122923074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.122923074
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.686727920
Short name T160
Test name
Test status
Simulation time 2682989232 ps
CPU time 43.17 seconds
Started Apr 28 04:55:08 PM PDT 24
Finished Apr 28 04:55:51 PM PDT 24
Peak memory 219668 kb
Host smart-675dca53-5a25-4b3f-934c-7aaac3d49672
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686727920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.686727920
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3812209189
Short name T47
Test name
Test status
Simulation time 25546201617 ps
CPU time 665.73 seconds
Started Apr 28 04:55:15 PM PDT 24
Finished Apr 28 05:06:21 PM PDT 24
Peak memory 234504 kb
Host smart-23ff1035-268a-483e-9095-f200d0370e65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812209189 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3812209189
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.883235633
Short name T162
Test name
Test status
Simulation time 10821411129 ps
CPU time 24.85 seconds
Started Apr 28 04:55:14 PM PDT 24
Finished Apr 28 04:55:39 PM PDT 24
Peak memory 212484 kb
Host smart-f64b8151-4c5e-40f9-91f9-702a6107fbdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883235633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.883235633
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3454027874
Short name T296
Test name
Test status
Simulation time 246680531655 ps
CPU time 591.06 seconds
Started Apr 28 04:55:13 PM PDT 24
Finished Apr 28 05:05:04 PM PDT 24
Peak memory 238260 kb
Host smart-4b2dd762-dc7e-459b-ae5e-c9cbf6524ecd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454027874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3454027874
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1336666947
Short name T165
Test name
Test status
Simulation time 5249529522 ps
CPU time 35.91 seconds
Started Apr 28 04:55:13 PM PDT 24
Finished Apr 28 04:55:50 PM PDT 24
Peak memory 214728 kb
Host smart-71e01ef1-7303-430b-a9a8-495b74067535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336666947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1336666947
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.4276266966
Short name T336
Test name
Test status
Simulation time 52039737799 ps
CPU time 36.66 seconds
Started Apr 28 04:55:13 PM PDT 24
Finished Apr 28 04:55:51 PM PDT 24
Peak memory 213156 kb
Host smart-fd009276-ba05-4ed5-8eda-3d11beef3537
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4276266966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.4276266966
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2929265124
Short name T198
Test name
Test status
Simulation time 3667263762 ps
CPU time 43.14 seconds
Started Apr 28 04:55:15 PM PDT 24
Finished Apr 28 04:55:58 PM PDT 24
Peak memory 217320 kb
Host smart-17155834-cd7b-4bec-82a3-7b6a7ebfc904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929265124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2929265124
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3653253431
Short name T236
Test name
Test status
Simulation time 55155163350 ps
CPU time 132.07 seconds
Started Apr 28 04:55:15 PM PDT 24
Finished Apr 28 04:57:28 PM PDT 24
Peak memory 227892 kb
Host smart-85dc6b21-534e-4579-987e-711ca3afb452
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653253431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3653253431
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2812342733
Short name T173
Test name
Test status
Simulation time 4404157441 ps
CPU time 31.93 seconds
Started Apr 28 04:55:59 PM PDT 24
Finished Apr 28 04:56:32 PM PDT 24
Peak memory 212520 kb
Host smart-f21e2996-8800-419e-b6c0-c5f3f495ae5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812342733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2812342733
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.379694648
Short name T8
Test name
Test status
Simulation time 3045474862 ps
CPU time 180.57 seconds
Started Apr 28 04:56:07 PM PDT 24
Finished Apr 28 04:59:08 PM PDT 24
Peak memory 236660 kb
Host smart-1de56fe1-e570-471e-89d3-98ca9a3ceb5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379694648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.379694648
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.6765592
Short name T292
Test name
Test status
Simulation time 5289837647 ps
CPU time 41.37 seconds
Started Apr 28 04:56:03 PM PDT 24
Finished Apr 28 04:56:46 PM PDT 24
Peak memory 215256 kb
Host smart-afb28e20-f838-4e04-b0e8-97288c86f4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6765592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.6765592
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.335040142
Short name T122
Test name
Test status
Simulation time 1404096846 ps
CPU time 12.64 seconds
Started Apr 28 04:56:07 PM PDT 24
Finished Apr 28 04:56:20 PM PDT 24
Peak memory 211560 kb
Host smart-3c032764-7be0-42c2-8735-842c6e624214
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335040142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.335040142
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.87623352
Short name T17
Test name
Test status
Simulation time 9901584306 ps
CPU time 37.53 seconds
Started Apr 28 04:55:13 PM PDT 24
Finished Apr 28 04:55:51 PM PDT 24
Peak memory 218388 kb
Host smart-587aa790-3def-4812-81f7-22705cc329e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87623352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.87623352
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2221494309
Short name T184
Test name
Test status
Simulation time 24051018851 ps
CPU time 158.26 seconds
Started Apr 28 04:56:05 PM PDT 24
Finished Apr 28 04:58:44 PM PDT 24
Peak memory 227880 kb
Host smart-1b59d91f-3092-4b41-baf5-ae0588d3189c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221494309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2221494309
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.164811368
Short name T166
Test name
Test status
Simulation time 52953969403 ps
CPU time 426.45 seconds
Started Apr 28 04:56:05 PM PDT 24
Finished Apr 28 05:03:12 PM PDT 24
Peak memory 230944 kb
Host smart-19697750-06a0-46dd-a9b2-a08cd6568715
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164811368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.164811368
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1432242129
Short name T265
Test name
Test status
Simulation time 2864598726 ps
CPU time 34.62 seconds
Started Apr 28 04:56:08 PM PDT 24
Finished Apr 28 04:56:44 PM PDT 24
Peak memory 215068 kb
Host smart-4ea93335-ca27-4213-af21-b5e5784ec550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432242129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1432242129
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3574698721
Short name T251
Test name
Test status
Simulation time 17526514081 ps
CPU time 35.63 seconds
Started Apr 28 04:55:59 PM PDT 24
Finished Apr 28 04:56:35 PM PDT 24
Peak memory 211992 kb
Host smart-bd3e57cd-cf8a-41a0-a9d5-91222ee26c19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3574698721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3574698721
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.69219032
Short name T207
Test name
Test status
Simulation time 869377362 ps
CPU time 26.98 seconds
Started Apr 28 04:56:31 PM PDT 24
Finished Apr 28 04:56:59 PM PDT 24
Peak memory 217516 kb
Host smart-878cd79a-b57c-40aa-b7a5-c41121266924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69219032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.69219032
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1980418272
Short name T216
Test name
Test status
Simulation time 3309061668 ps
CPU time 42.16 seconds
Started Apr 28 04:56:04 PM PDT 24
Finished Apr 28 04:56:47 PM PDT 24
Peak memory 218312 kb
Host smart-08d26cd5-362b-4b3a-bf29-0f53cf877269
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980418272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1980418272
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4282799268
Short name T328
Test name
Test status
Simulation time 4183646989 ps
CPU time 22.5 seconds
Started Apr 28 04:56:27 PM PDT 24
Finished Apr 28 04:56:50 PM PDT 24
Peak memory 212172 kb
Host smart-ed127428-87ac-45c2-bce1-6557e5a52069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282799268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4282799268
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.427105938
Short name T327
Test name
Test status
Simulation time 164546450777 ps
CPU time 695.3 seconds
Started Apr 28 04:55:59 PM PDT 24
Finished Apr 28 05:07:35 PM PDT 24
Peak memory 230072 kb
Host smart-a87f4b6f-7492-4b32-8c1e-ad5c1980edf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427105938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.427105938
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3771768236
Short name T283
Test name
Test status
Simulation time 10949036722 ps
CPU time 52.35 seconds
Started Apr 28 04:55:59 PM PDT 24
Finished Apr 28 04:56:52 PM PDT 24
Peak memory 215268 kb
Host smart-f27cdada-e659-4e11-9890-0b85755648fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771768236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3771768236
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2721233122
Short name T272
Test name
Test status
Simulation time 254226324 ps
CPU time 11.02 seconds
Started Apr 28 04:56:06 PM PDT 24
Finished Apr 28 04:56:18 PM PDT 24
Peak memory 212576 kb
Host smart-18e66da5-9da9-4ffb-838e-ece20b529c50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721233122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2721233122
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.388199297
Short name T114
Test name
Test status
Simulation time 4211639740 ps
CPU time 33.62 seconds
Started Apr 28 04:55:59 PM PDT 24
Finished Apr 28 04:56:33 PM PDT 24
Peak memory 218140 kb
Host smart-df3e08d7-9e13-4436-85e0-3e54dfe0cd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388199297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.388199297
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1573042935
Short name T245
Test name
Test status
Simulation time 3518394124 ps
CPU time 30.53 seconds
Started Apr 28 04:56:05 PM PDT 24
Finished Apr 28 04:56:36 PM PDT 24
Peak memory 211668 kb
Host smart-5b0359cc-8866-4dbb-9bbe-0b4ba7ea3353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573042935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1573042935
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3064099762
Short name T155
Test name
Test status
Simulation time 9467867361 ps
CPU time 170.79 seconds
Started Apr 28 04:56:10 PM PDT 24
Finished Apr 28 04:59:01 PM PDT 24
Peak memory 237252 kb
Host smart-c153ac83-5d13-47af-86a0-33649a18a93b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064099762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3064099762
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1894875132
Short name T246
Test name
Test status
Simulation time 4869661043 ps
CPU time 47.8 seconds
Started Apr 28 04:56:28 PM PDT 24
Finished Apr 28 04:57:17 PM PDT 24
Peak memory 215464 kb
Host smart-d60ac740-fd47-4848-bb26-d7f543884fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894875132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1894875132
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2178544860
Short name T145
Test name
Test status
Simulation time 2346846961 ps
CPU time 15.12 seconds
Started Apr 28 04:56:03 PM PDT 24
Finished Apr 28 04:56:19 PM PDT 24
Peak memory 213016 kb
Host smart-154d78cf-ae51-46ef-a520-22082ac1b1b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178544860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2178544860
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.473485401
Short name T256
Test name
Test status
Simulation time 568635701 ps
CPU time 19.82 seconds
Started Apr 28 04:56:07 PM PDT 24
Finished Apr 28 04:56:28 PM PDT 24
Peak memory 217820 kb
Host smart-f653d0be-30f5-4fa7-ac89-4878683e9189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473485401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.473485401
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.4042005235
Short name T252
Test name
Test status
Simulation time 12563387610 ps
CPU time 71.09 seconds
Started Apr 28 04:56:26 PM PDT 24
Finished Apr 28 04:57:37 PM PDT 24
Peak memory 220240 kb
Host smart-8df4a5b2-1ed0-4af6-ac70-0dd4a133c63a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042005235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.4042005235
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.646262135
Short name T58
Test name
Test status
Simulation time 1711513980 ps
CPU time 11.61 seconds
Started Apr 28 04:56:02 PM PDT 24
Finished Apr 28 04:56:14 PM PDT 24
Peak memory 211544 kb
Host smart-911868f6-0c36-45a7-b17c-350fb79ca61c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646262135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.646262135
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1162286808
Short name T144
Test name
Test status
Simulation time 334234051132 ps
CPU time 557.79 seconds
Started Apr 28 04:56:06 PM PDT 24
Finished Apr 28 05:05:24 PM PDT 24
Peak memory 238680 kb
Host smart-a2a33169-e947-4c97-85d0-06734b265077
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162286808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1162286808
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3028113750
Short name T274
Test name
Test status
Simulation time 28608698763 ps
CPU time 48.55 seconds
Started Apr 28 04:56:10 PM PDT 24
Finished Apr 28 04:56:59 PM PDT 24
Peak memory 215372 kb
Host smart-19c9ec83-6c18-45cb-84fa-e62531bfbce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028113750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3028113750
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3392398728
Short name T267
Test name
Test status
Simulation time 4363132720 ps
CPU time 24.14 seconds
Started Apr 28 04:56:01 PM PDT 24
Finished Apr 28 04:56:25 PM PDT 24
Peak memory 213052 kb
Host smart-3bc20336-296c-478d-900a-d2ae2a7e1dfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3392398728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3392398728
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3947326830
Short name T142
Test name
Test status
Simulation time 7513617388 ps
CPU time 63 seconds
Started Apr 28 04:56:26 PM PDT 24
Finished Apr 28 04:57:30 PM PDT 24
Peak memory 217320 kb
Host smart-d128d750-f63f-4d5a-b2d0-9d3b7e635732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947326830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3947326830
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3382695752
Short name T298
Test name
Test status
Simulation time 26329883547 ps
CPU time 80.77 seconds
Started Apr 28 04:56:06 PM PDT 24
Finished Apr 28 04:57:28 PM PDT 24
Peak memory 216440 kb
Host smart-0d244c27-adac-439c-b805-9296f03b736a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382695752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3382695752
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1300304847
Short name T33
Test name
Test status
Simulation time 2762804545 ps
CPU time 13.22 seconds
Started Apr 28 04:56:04 PM PDT 24
Finished Apr 28 04:56:18 PM PDT 24
Peak memory 212248 kb
Host smart-4dd83c22-530c-45fb-af6b-279191c17a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300304847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1300304847
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.903710679
Short name T307
Test name
Test status
Simulation time 123391557938 ps
CPU time 576.16 seconds
Started Apr 28 04:56:02 PM PDT 24
Finished Apr 28 05:05:39 PM PDT 24
Peak memory 240872 kb
Host smart-a10b0d14-4229-4fbe-ae9d-cd8974d96a6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903710679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.903710679
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2240343563
Short name T240
Test name
Test status
Simulation time 22635790374 ps
CPU time 56.86 seconds
Started Apr 28 04:56:08 PM PDT 24
Finished Apr 28 04:57:05 PM PDT 24
Peak memory 215356 kb
Host smart-cd832dc2-5373-472e-984c-a79659abfd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240343563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2240343563
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4217244075
Short name T136
Test name
Test status
Simulation time 5337717653 ps
CPU time 26.12 seconds
Started Apr 28 04:55:58 PM PDT 24
Finished Apr 28 04:56:24 PM PDT 24
Peak memory 212840 kb
Host smart-2a0075ff-6ed9-408c-8ca9-42e94ca1e2b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4217244075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4217244075
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2541937854
Short name T30
Test name
Test status
Simulation time 4026495168 ps
CPU time 31.3 seconds
Started Apr 28 04:54:23 PM PDT 24
Finished Apr 28 04:54:55 PM PDT 24
Peak memory 212224 kb
Host smart-e3ca31c9-823b-4d69-b74f-5a485a56ac3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541937854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2541937854
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2812052549
Short name T42
Test name
Test status
Simulation time 60420976451 ps
CPU time 321.06 seconds
Started Apr 28 04:54:19 PM PDT 24
Finished Apr 28 04:59:41 PM PDT 24
Peak memory 219620 kb
Host smart-24ebb25a-b6eb-4ce1-bc65-a8d8497c0f11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812052549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2812052549
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3827481376
Short name T161
Test name
Test status
Simulation time 7004358524 ps
CPU time 40.5 seconds
Started Apr 28 04:54:19 PM PDT 24
Finished Apr 28 04:55:00 PM PDT 24
Peak memory 215488 kb
Host smart-1caf95cd-ad88-48a1-b879-867dca7b4960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827481376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3827481376
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1733518781
Short name T39
Test name
Test status
Simulation time 8260289495 ps
CPU time 21.17 seconds
Started Apr 28 04:54:24 PM PDT 24
Finished Apr 28 04:54:46 PM PDT 24
Peak memory 213112 kb
Host smart-53461363-ef5c-425c-87ac-14ebc8d349b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1733518781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1733518781
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2561801395
Short name T25
Test name
Test status
Simulation time 13195306103 ps
CPU time 241.09 seconds
Started Apr 28 04:54:19 PM PDT 24
Finished Apr 28 04:58:21 PM PDT 24
Peak memory 238708 kb
Host smart-992ea0a2-e05d-41fd-b6f5-1889daf8a4eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561801395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2561801395
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.635286483
Short name T147
Test name
Test status
Simulation time 6318581606 ps
CPU time 65.89 seconds
Started Apr 28 04:54:18 PM PDT 24
Finished Apr 28 04:55:24 PM PDT 24
Peak memory 218132 kb
Host smart-1bdb3150-2403-42e0-9b7c-490b2822b1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635286483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.635286483
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3867629021
Short name T202
Test name
Test status
Simulation time 9617737212 ps
CPU time 283.39 seconds
Started Apr 28 04:56:00 PM PDT 24
Finished Apr 28 05:00:44 PM PDT 24
Peak memory 226068 kb
Host smart-29ac3d6c-0d27-4e7b-acae-cb8f7c12d814
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867629021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3867629021
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1522309930
Short name T316
Test name
Test status
Simulation time 3251491183 ps
CPU time 38.22 seconds
Started Apr 28 04:56:02 PM PDT 24
Finished Apr 28 04:56:41 PM PDT 24
Peak memory 215472 kb
Host smart-00777730-4f90-4e51-aaf1-748ebb0508ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522309930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1522309930
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.580662924
Short name T212
Test name
Test status
Simulation time 695684760 ps
CPU time 10.91 seconds
Started Apr 28 04:56:02 PM PDT 24
Finished Apr 28 04:56:14 PM PDT 24
Peak memory 212612 kb
Host smart-4f48be28-e991-402e-8ea9-ee1f2f42adc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=580662924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.580662924
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.186396244
Short name T204
Test name
Test status
Simulation time 14527818640 ps
CPU time 69.48 seconds
Started Apr 28 04:56:01 PM PDT 24
Finished Apr 28 04:57:11 PM PDT 24
Peak memory 215760 kb
Host smart-29819d9b-450e-496e-9c22-d47ca78424fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186396244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.186396244
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.60057126
Short name T177
Test name
Test status
Simulation time 6008392295 ps
CPU time 24.42 seconds
Started Apr 28 04:56:02 PM PDT 24
Finished Apr 28 04:56:27 PM PDT 24
Peak memory 213496 kb
Host smart-9f35e043-e9bc-46d9-b929-68cc4f935b77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60057126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 40.rom_ctrl_stress_all.60057126
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1006666079
Short name T189
Test name
Test status
Simulation time 7798710134 ps
CPU time 20.29 seconds
Started Apr 28 04:56:01 PM PDT 24
Finished Apr 28 04:56:22 PM PDT 24
Peak memory 211644 kb
Host smart-4cc979ae-9a45-4fee-a62c-ab87178320f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006666079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1006666079
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1633508150
Short name T268
Test name
Test status
Simulation time 33527122868 ps
CPU time 371.89 seconds
Started Apr 28 04:56:08 PM PDT 24
Finished Apr 28 05:02:21 PM PDT 24
Peak memory 239304 kb
Host smart-961d7a39-ec29-4321-a535-cf57ac8d978a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633508150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1633508150
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3509344543
Short name T185
Test name
Test status
Simulation time 1320124792 ps
CPU time 19.47 seconds
Started Apr 28 04:56:06 PM PDT 24
Finished Apr 28 04:56:26 PM PDT 24
Peak memory 215064 kb
Host smart-bd8adfe4-bd89-4eb9-92dc-0c29b79e3a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509344543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3509344543
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3790083085
Short name T332
Test name
Test status
Simulation time 3615744475 ps
CPU time 30.29 seconds
Started Apr 28 04:56:01 PM PDT 24
Finished Apr 28 04:56:32 PM PDT 24
Peak memory 211632 kb
Host smart-5c18126d-f4f1-4cd7-a25d-30ee50ba7f81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790083085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3790083085
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3612479004
Short name T266
Test name
Test status
Simulation time 48104385233 ps
CPU time 58.65 seconds
Started Apr 28 04:56:00 PM PDT 24
Finished Apr 28 04:56:59 PM PDT 24
Peak memory 218628 kb
Host smart-0c15856c-47fc-4554-83c6-7449264f7967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612479004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3612479004
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3072657218
Short name T232
Test name
Test status
Simulation time 5637794513 ps
CPU time 53.2 seconds
Started Apr 28 04:56:00 PM PDT 24
Finished Apr 28 04:56:54 PM PDT 24
Peak memory 216416 kb
Host smart-38febc9f-ce3a-4ecf-8626-e5d8c9478912
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072657218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3072657218
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3018769881
Short name T45
Test name
Test status
Simulation time 107031324875 ps
CPU time 5882.16 seconds
Started Apr 28 04:56:01 PM PDT 24
Finished Apr 28 06:34:04 PM PDT 24
Peak memory 236192 kb
Host smart-ac04cdac-4d68-4d67-9621-b37bf70a1907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018769881 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3018769881
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2223841561
Short name T28
Test name
Test status
Simulation time 10663368371 ps
CPU time 23.94 seconds
Started Apr 28 04:55:59 PM PDT 24
Finished Apr 28 04:56:23 PM PDT 24
Peak memory 211708 kb
Host smart-53b2c1b8-d33c-4726-98a2-abdef6ab765a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223841561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2223841561
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1306231000
Short name T159
Test name
Test status
Simulation time 172867117120 ps
CPU time 562.49 seconds
Started Apr 28 04:56:02 PM PDT 24
Finished Apr 28 05:05:25 PM PDT 24
Peak memory 229752 kb
Host smart-feee8028-d74e-4c83-87f2-23279991c9b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306231000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1306231000
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2469014900
Short name T342
Test name
Test status
Simulation time 22541794665 ps
CPU time 54.38 seconds
Started Apr 28 04:55:59 PM PDT 24
Finished Apr 28 04:56:54 PM PDT 24
Peak memory 215288 kb
Host smart-85561893-3a07-4a9c-8bbb-918f6b298c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469014900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2469014900
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3999622509
Short name T158
Test name
Test status
Simulation time 9209067370 ps
CPU time 24.67 seconds
Started Apr 28 04:56:08 PM PDT 24
Finished Apr 28 04:56:34 PM PDT 24
Peak memory 212116 kb
Host smart-8ee35ff9-b51e-465b-a7d6-2887391e147d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999622509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3999622509
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.413044459
Short name T319
Test name
Test status
Simulation time 709506818 ps
CPU time 20.04 seconds
Started Apr 28 04:56:02 PM PDT 24
Finished Apr 28 04:56:23 PM PDT 24
Peak memory 218040 kb
Host smart-d8c6358f-4f45-4472-b313-3b7a841f2130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413044459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.413044459
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.588675296
Short name T164
Test name
Test status
Simulation time 21181257325 ps
CPU time 62.8 seconds
Started Apr 28 04:56:25 PM PDT 24
Finished Apr 28 04:57:28 PM PDT 24
Peak memory 216928 kb
Host smart-9a29efb1-963e-4d93-bce9-15eeee2c794e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588675296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.588675296
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2695902112
Short name T206
Test name
Test status
Simulation time 22291649866 ps
CPU time 327.35 seconds
Started Apr 28 04:56:08 PM PDT 24
Finished Apr 28 05:01:36 PM PDT 24
Peak memory 228964 kb
Host smart-a673537c-10b1-4fdb-8f39-5f47bd516704
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695902112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2695902112
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3940886087
Short name T132
Test name
Test status
Simulation time 3181974556 ps
CPU time 29.46 seconds
Started Apr 28 04:55:59 PM PDT 24
Finished Apr 28 04:56:29 PM PDT 24
Peak memory 212848 kb
Host smart-84e1e001-3c23-42ba-9d7e-bbeb6504dfcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940886087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3940886087
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2545640332
Short name T179
Test name
Test status
Simulation time 13654462701 ps
CPU time 41.56 seconds
Started Apr 28 04:56:07 PM PDT 24
Finished Apr 28 04:56:49 PM PDT 24
Peak memory 218324 kb
Host smart-bddef03d-dcf3-480a-a4fc-9f3d262a2cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545640332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2545640332
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3538659058
Short name T293
Test name
Test status
Simulation time 5698736034 ps
CPU time 37.65 seconds
Started Apr 28 04:56:06 PM PDT 24
Finished Apr 28 04:56:44 PM PDT 24
Peak memory 214768 kb
Host smart-d50777b5-661d-4cea-b0ab-2afa91a7c456
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538659058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3538659058
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3350610568
Short name T46
Test name
Test status
Simulation time 116329196255 ps
CPU time 2190.28 seconds
Started Apr 28 04:56:07 PM PDT 24
Finished Apr 28 05:32:38 PM PDT 24
Peak memory 244252 kb
Host smart-68a66a4a-6de8-46bf-9b3a-e3b8a60e2ed4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350610568 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3350610568
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1401414445
Short name T171
Test name
Test status
Simulation time 15049337722 ps
CPU time 29.57 seconds
Started Apr 28 04:56:35 PM PDT 24
Finished Apr 28 04:57:05 PM PDT 24
Peak memory 212500 kb
Host smart-e93b1fa7-ac49-4e13-8892-292fa3d16864
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401414445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1401414445
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.246740778
Short name T254
Test name
Test status
Simulation time 427894854033 ps
CPU time 1028.57 seconds
Started Apr 28 04:56:05 PM PDT 24
Finished Apr 28 05:13:14 PM PDT 24
Peak memory 238172 kb
Host smart-3a444ae2-1ec5-4d92-9377-21515fbd8129
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246740778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.246740778
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2305142364
Short name T167
Test name
Test status
Simulation time 870626829 ps
CPU time 19.59 seconds
Started Apr 28 04:56:10 PM PDT 24
Finished Apr 28 04:56:30 PM PDT 24
Peak memory 214984 kb
Host smart-395663ee-ee8c-47e2-8c02-0fbfa8d40653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305142364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2305142364
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.4242319803
Short name T295
Test name
Test status
Simulation time 5974474034 ps
CPU time 17.54 seconds
Started Apr 28 04:56:08 PM PDT 24
Finished Apr 28 04:56:27 PM PDT 24
Peak memory 212028 kb
Host smart-1b6a063c-9573-4752-9eaa-0ea7b449dd09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4242319803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.4242319803
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2405891749
Short name T217
Test name
Test status
Simulation time 1349691363 ps
CPU time 24.97 seconds
Started Apr 28 04:56:01 PM PDT 24
Finished Apr 28 04:56:27 PM PDT 24
Peak memory 217112 kb
Host smart-a452750f-66eb-416e-accf-c14b1099d853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405891749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2405891749
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.574143916
Short name T210
Test name
Test status
Simulation time 1234397647 ps
CPU time 79.85 seconds
Started Apr 28 04:56:08 PM PDT 24
Finished Apr 28 04:57:29 PM PDT 24
Peak memory 219592 kb
Host smart-80a4d643-f988-470f-9eda-34ef95916a9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574143916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.574143916
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3677298722
Short name T314
Test name
Test status
Simulation time 31185705982 ps
CPU time 27.91 seconds
Started Apr 28 04:56:03 PM PDT 24
Finished Apr 28 04:56:32 PM PDT 24
Peak memory 212520 kb
Host smart-95f134f2-5193-4f2d-af79-8f49983b90f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677298722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3677298722
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3475977777
Short name T346
Test name
Test status
Simulation time 60729091257 ps
CPU time 578.82 seconds
Started Apr 28 04:56:06 PM PDT 24
Finished Apr 28 05:05:45 PM PDT 24
Peak memory 238084 kb
Host smart-a0aed569-0d99-490e-9d68-76ed343508fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475977777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3475977777
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1567754882
Short name T20
Test name
Test status
Simulation time 17731188012 ps
CPU time 47.14 seconds
Started Apr 28 04:56:03 PM PDT 24
Finished Apr 28 04:56:51 PM PDT 24
Peak memory 215248 kb
Host smart-98598638-33cd-4822-9be0-68a762fb19f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567754882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1567754882
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4228923573
Short name T227
Test name
Test status
Simulation time 1079057424 ps
CPU time 17.33 seconds
Started Apr 28 04:56:24 PM PDT 24
Finished Apr 28 04:56:42 PM PDT 24
Peak memory 211520 kb
Host smart-02d2c6af-fa46-460a-b667-ed57cf751f8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228923573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4228923573
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.722286552
Short name T238
Test name
Test status
Simulation time 8562005711 ps
CPU time 78.83 seconds
Started Apr 28 04:56:00 PM PDT 24
Finished Apr 28 04:57:20 PM PDT 24
Peak memory 215744 kb
Host smart-4f7b1b6a-768c-4f24-835a-492efdab9f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722286552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.722286552
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3417779576
Short name T357
Test name
Test status
Simulation time 8453915778 ps
CPU time 26.82 seconds
Started Apr 28 04:56:07 PM PDT 24
Finished Apr 28 04:56:35 PM PDT 24
Peak memory 214540 kb
Host smart-3030616d-740a-4e0a-87ac-239dcabceb0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417779576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3417779576
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1195649730
Short name T303
Test name
Test status
Simulation time 2210022996 ps
CPU time 21.39 seconds
Started Apr 28 04:56:09 PM PDT 24
Finished Apr 28 04:56:32 PM PDT 24
Peak memory 211684 kb
Host smart-e2b80d2f-4345-48ec-8bf6-a29d0135366a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195649730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1195649730
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.575290886
Short name T234
Test name
Test status
Simulation time 35502547848 ps
CPU time 395.53 seconds
Started Apr 28 04:56:08 PM PDT 24
Finished Apr 28 05:02:44 PM PDT 24
Peak memory 240096 kb
Host smart-8b8dc91b-c777-4dca-91a8-24bf0bf1a6c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575290886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.575290886
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.142540414
Short name T23
Test name
Test status
Simulation time 16004087580 ps
CPU time 61.31 seconds
Started Apr 28 04:55:58 PM PDT 24
Finished Apr 28 04:57:00 PM PDT 24
Peak memory 214152 kb
Host smart-ae846be2-2918-4fd8-891c-e6dbce101787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142540414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.142540414
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1640381662
Short name T260
Test name
Test status
Simulation time 16038093390 ps
CPU time 28.75 seconds
Started Apr 28 04:56:28 PM PDT 24
Finished Apr 28 04:56:58 PM PDT 24
Peak memory 212116 kb
Host smart-c7056d3b-a5cb-41ff-914f-572e1abc4c07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640381662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1640381662
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3513920545
Short name T121
Test name
Test status
Simulation time 71707957245 ps
CPU time 55.83 seconds
Started Apr 28 04:56:22 PM PDT 24
Finished Apr 28 04:57:18 PM PDT 24
Peak memory 218148 kb
Host smart-901656c5-69bf-4c24-90ef-4a6657ccf63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513920545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3513920545
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1714979336
Short name T208
Test name
Test status
Simulation time 4061638504 ps
CPU time 56.29 seconds
Started Apr 28 04:56:38 PM PDT 24
Finished Apr 28 04:57:34 PM PDT 24
Peak memory 219680 kb
Host smart-c45e9966-1d65-4c04-aa78-fb0d54c99fc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714979336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1714979336
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3476356892
Short name T315
Test name
Test status
Simulation time 12934916636 ps
CPU time 30.06 seconds
Started Apr 28 04:55:57 PM PDT 24
Finished Apr 28 04:56:27 PM PDT 24
Peak memory 212488 kb
Host smart-87b968eb-6f40-4595-9821-66c85aed9bea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476356892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3476356892
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.992805109
Short name T43
Test name
Test status
Simulation time 50543925125 ps
CPU time 352.59 seconds
Started Apr 28 04:56:04 PM PDT 24
Finished Apr 28 05:01:57 PM PDT 24
Peak memory 224980 kb
Host smart-23b34217-a3a7-4c2b-92e8-ab6b7f00ce7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992805109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.992805109
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.303801231
Short name T279
Test name
Test status
Simulation time 21393941422 ps
CPU time 49.59 seconds
Started Apr 28 04:56:03 PM PDT 24
Finished Apr 28 04:56:54 PM PDT 24
Peak memory 215332 kb
Host smart-a8bd9534-9ebe-449b-be73-f1b90b9e3105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303801231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.303801231
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1402205010
Short name T99
Test name
Test status
Simulation time 83810966905 ps
CPU time 34.1 seconds
Started Apr 28 04:56:27 PM PDT 24
Finished Apr 28 04:57:02 PM PDT 24
Peak memory 213152 kb
Host smart-48c65a15-6edb-4803-958b-b2fec78040bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1402205010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1402205010
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.522660120
Short name T325
Test name
Test status
Simulation time 7375894964 ps
CPU time 64.07 seconds
Started Apr 28 04:56:06 PM PDT 24
Finished Apr 28 04:57:11 PM PDT 24
Peak memory 218240 kb
Host smart-93400dec-5170-4d87-aee4-eb6bacbce8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522660120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.522660120
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1410072743
Short name T242
Test name
Test status
Simulation time 7802257090 ps
CPU time 72.6 seconds
Started Apr 28 04:56:27 PM PDT 24
Finished Apr 28 04:57:41 PM PDT 24
Peak memory 221504 kb
Host smart-afc385a7-dc8d-419f-9d0f-e5d65c5272c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410072743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1410072743
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.412262556
Short name T57
Test name
Test status
Simulation time 15635962214 ps
CPU time 33.14 seconds
Started Apr 28 04:56:03 PM PDT 24
Finished Apr 28 04:56:37 PM PDT 24
Peak memory 212524 kb
Host smart-103b40a9-9f3f-413d-850b-8642fbbb0333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412262556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.412262556
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3578215654
Short name T257
Test name
Test status
Simulation time 4483492376 ps
CPU time 229.03 seconds
Started Apr 28 04:55:58 PM PDT 24
Finished Apr 28 04:59:47 PM PDT 24
Peak memory 216492 kb
Host smart-d2d2b289-bb10-47fe-9054-8049f66ad4ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578215654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3578215654
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1691437033
Short name T282
Test name
Test status
Simulation time 2080391742 ps
CPU time 30.46 seconds
Started Apr 28 04:56:00 PM PDT 24
Finished Apr 28 04:56:31 PM PDT 24
Peak memory 215292 kb
Host smart-874a05d7-5cdb-46ba-b75a-d0df0da73ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691437033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1691437033
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3822040047
Short name T135
Test name
Test status
Simulation time 3511567526 ps
CPU time 30.19 seconds
Started Apr 28 04:56:03 PM PDT 24
Finished Apr 28 04:56:34 PM PDT 24
Peak memory 211648 kb
Host smart-8b9fcf7b-8bbb-4bcb-9861-2f4623b06f9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3822040047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3822040047
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2730995090
Short name T71
Test name
Test status
Simulation time 20382963941 ps
CPU time 49.56 seconds
Started Apr 28 04:56:09 PM PDT 24
Finished Apr 28 04:57:00 PM PDT 24
Peak memory 218104 kb
Host smart-d132e8df-556b-4b02-83f2-8590b8833700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730995090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2730995090
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2448391045
Short name T280
Test name
Test status
Simulation time 10124543848 ps
CPU time 79.54 seconds
Started Apr 28 04:56:07 PM PDT 24
Finished Apr 28 04:57:27 PM PDT 24
Peak memory 222860 kb
Host smart-e54dbd24-6866-4d6c-92fa-f8c4058afc8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448391045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2448391045
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3169801
Short name T285
Test name
Test status
Simulation time 472969767 ps
CPU time 8.51 seconds
Started Apr 28 04:56:09 PM PDT 24
Finished Apr 28 04:56:19 PM PDT 24
Peak memory 211652 kb
Host smart-a3e5ed9b-dfff-4a90-8754-6b30554b1347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3169801
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3551680128
Short name T21
Test name
Test status
Simulation time 129048446469 ps
CPU time 343.73 seconds
Started Apr 28 04:56:02 PM PDT 24
Finished Apr 28 05:01:47 PM PDT 24
Peak memory 228820 kb
Host smart-39577997-3daa-402b-996e-9a46f8b84e2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551680128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3551680128
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2636847661
Short name T339
Test name
Test status
Simulation time 8709646486 ps
CPU time 67.57 seconds
Started Apr 28 04:56:05 PM PDT 24
Finished Apr 28 04:57:13 PM PDT 24
Peak memory 215484 kb
Host smart-aa62c2ef-82f0-4243-bcb4-ccda83d1517e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636847661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2636847661
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3977167368
Short name T341
Test name
Test status
Simulation time 176031863 ps
CPU time 10.4 seconds
Started Apr 28 04:56:07 PM PDT 24
Finished Apr 28 04:56:18 PM PDT 24
Peak memory 212440 kb
Host smart-6787f5eb-f95a-40f0-bf53-d87285ba49f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3977167368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3977167368
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2384451442
Short name T120
Test name
Test status
Simulation time 19110411518 ps
CPU time 48.5 seconds
Started Apr 28 04:56:08 PM PDT 24
Finished Apr 28 04:56:57 PM PDT 24
Peak memory 218464 kb
Host smart-5ff4d0ef-6804-4728-bbf0-8211e1cf78a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384451442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2384451442
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3247206170
Short name T152
Test name
Test status
Simulation time 1585831666 ps
CPU time 21.91 seconds
Started Apr 28 04:56:22 PM PDT 24
Finished Apr 28 04:56:44 PM PDT 24
Peak memory 218504 kb
Host smart-6c8ca4aa-2ee1-4506-90e5-7c1a048deb14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247206170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3247206170
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3523515666
Short name T284
Test name
Test status
Simulation time 4128028509 ps
CPU time 20.54 seconds
Started Apr 28 04:54:24 PM PDT 24
Finished Apr 28 04:54:45 PM PDT 24
Peak memory 212200 kb
Host smart-545008f6-7203-451a-adff-e16cb92986eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523515666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3523515666
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3902524077
Short name T19
Test name
Test status
Simulation time 22334388911 ps
CPU time 53.59 seconds
Started Apr 28 04:54:21 PM PDT 24
Finished Apr 28 04:55:15 PM PDT 24
Peak memory 215340 kb
Host smart-7a50a9e8-e825-405f-be56-e27f4be29578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902524077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3902524077
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3652908582
Short name T219
Test name
Test status
Simulation time 358290864 ps
CPU time 11.1 seconds
Started Apr 28 04:54:21 PM PDT 24
Finished Apr 28 04:54:33 PM PDT 24
Peak memory 212816 kb
Host smart-f8f08a6e-9e41-46cf-bd98-9d83fef44210
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652908582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3652908582
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2754050122
Short name T69
Test name
Test status
Simulation time 1815198951 ps
CPU time 34.95 seconds
Started Apr 28 04:54:19 PM PDT 24
Finished Apr 28 04:54:55 PM PDT 24
Peak memory 217708 kb
Host smart-0956b410-19b2-4ca7-96e8-e7920c51e5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754050122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2754050122
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3069841703
Short name T352
Test name
Test status
Simulation time 2484536429 ps
CPU time 24.8 seconds
Started Apr 28 04:54:21 PM PDT 24
Finished Apr 28 04:54:47 PM PDT 24
Peak memory 217460 kb
Host smart-a40fef9f-3086-426e-a01a-b8d717ec759e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069841703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3069841703
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3404099135
Short name T226
Test name
Test status
Simulation time 345954907 ps
CPU time 8.42 seconds
Started Apr 28 04:54:20 PM PDT 24
Finished Apr 28 04:54:29 PM PDT 24
Peak memory 211620 kb
Host smart-c50ea368-a237-45a2-9d65-ee7ad796af57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404099135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3404099135
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.559238134
Short name T349
Test name
Test status
Simulation time 22069913309 ps
CPU time 287.66 seconds
Started Apr 28 04:54:23 PM PDT 24
Finished Apr 28 04:59:11 PM PDT 24
Peak memory 238316 kb
Host smart-9453afba-51c2-4553-b3aa-376284124825
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559238134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.559238134
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2188576193
Short name T304
Test name
Test status
Simulation time 869915460 ps
CPU time 19.06 seconds
Started Apr 28 04:54:21 PM PDT 24
Finished Apr 28 04:54:41 PM PDT 24
Peak memory 215016 kb
Host smart-831d858b-c757-4a65-99c4-fc6d4437f9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188576193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2188576193
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.726472284
Short name T330
Test name
Test status
Simulation time 2797321650 ps
CPU time 15.42 seconds
Started Apr 28 04:54:22 PM PDT 24
Finished Apr 28 04:54:38 PM PDT 24
Peak memory 211660 kb
Host smart-6d1789c8-9593-4f11-9e27-e846a705cd7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726472284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.726472284
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.968950926
Short name T150
Test name
Test status
Simulation time 23000902096 ps
CPU time 65.73 seconds
Started Apr 28 04:54:22 PM PDT 24
Finished Apr 28 04:55:29 PM PDT 24
Peak memory 218156 kb
Host smart-e05e1548-508b-4ab4-ae88-9300558a159c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968950926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.968950926
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4005787443
Short name T243
Test name
Test status
Simulation time 317886101 ps
CPU time 21.1 seconds
Started Apr 28 04:54:22 PM PDT 24
Finished Apr 28 04:54:44 PM PDT 24
Peak memory 211916 kb
Host smart-d720b289-6578-41bc-b423-935419cda127
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005787443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4005787443
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3275656498
Short name T131
Test name
Test status
Simulation time 176379890 ps
CPU time 8.55 seconds
Started Apr 28 04:54:28 PM PDT 24
Finished Apr 28 04:54:37 PM PDT 24
Peak memory 211624 kb
Host smart-c89d6f4a-185b-41b9-9a3f-d52ad3ea48eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275656498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3275656498
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4291928646
Short name T301
Test name
Test status
Simulation time 11506526850 ps
CPU time 209.47 seconds
Started Apr 28 04:54:25 PM PDT 24
Finished Apr 28 04:57:55 PM PDT 24
Peak memory 238204 kb
Host smart-c76c533a-0035-42c0-bbcd-f1d44629810b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291928646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.4291928646
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.487545918
Short name T318
Test name
Test status
Simulation time 33249171879 ps
CPU time 69.62 seconds
Started Apr 28 04:54:25 PM PDT 24
Finished Apr 28 04:55:35 PM PDT 24
Peak memory 214336 kb
Host smart-e2f03631-d1c8-4622-beea-ee98550486d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487545918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.487545918
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3409568600
Short name T331
Test name
Test status
Simulation time 11649539065 ps
CPU time 27.6 seconds
Started Apr 28 04:54:21 PM PDT 24
Finished Apr 28 04:54:50 PM PDT 24
Peak memory 211780 kb
Host smart-804bddd8-2ac8-40fc-9045-22d1e043b9e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409568600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3409568600
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3620463154
Short name T203
Test name
Test status
Simulation time 2631080953 ps
CPU time 21.01 seconds
Started Apr 28 04:54:21 PM PDT 24
Finished Apr 28 04:54:42 PM PDT 24
Peak memory 217052 kb
Host smart-e0d3e257-7b34-417d-ae9f-dd88544b4d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620463154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3620463154
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.761112995
Short name T286
Test name
Test status
Simulation time 11448401996 ps
CPU time 67.63 seconds
Started Apr 28 04:54:21 PM PDT 24
Finished Apr 28 04:55:29 PM PDT 24
Peak memory 219884 kb
Host smart-429abee1-47dc-4d42-ab8b-298d24fdbc83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761112995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.761112995
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2267314315
Short name T289
Test name
Test status
Simulation time 3753110475 ps
CPU time 14.87 seconds
Started Apr 28 04:54:26 PM PDT 24
Finished Apr 28 04:54:42 PM PDT 24
Peak memory 211660 kb
Host smart-fb4fab56-d01d-47e8-9f1a-1d778c185546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267314315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2267314315
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4285680721
Short name T148
Test name
Test status
Simulation time 57374091283 ps
CPU time 284.27 seconds
Started Apr 28 04:54:27 PM PDT 24
Finished Apr 28 04:59:12 PM PDT 24
Peak memory 241440 kb
Host smart-38121728-7fef-4077-a3ec-255f288fac80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285680721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.4285680721
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1784665530
Short name T312
Test name
Test status
Simulation time 1570789767 ps
CPU time 19.4 seconds
Started Apr 28 04:54:27 PM PDT 24
Finished Apr 28 04:54:47 PM PDT 24
Peak memory 215008 kb
Host smart-25414a00-cd0d-4bb2-b4de-b18d69884696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784665530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1784665530
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1893962308
Short name T195
Test name
Test status
Simulation time 182515619 ps
CPU time 10.54 seconds
Started Apr 28 04:54:25 PM PDT 24
Finished Apr 28 04:54:36 PM PDT 24
Peak memory 212512 kb
Host smart-be382f5c-bd2a-4e3a-bb3b-8f0177d2d50d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893962308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1893962308
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1568833339
Short name T259
Test name
Test status
Simulation time 34319647878 ps
CPU time 76.09 seconds
Started Apr 28 04:54:31 PM PDT 24
Finished Apr 28 04:55:47 PM PDT 24
Peak memory 214748 kb
Host smart-7ce95760-4d3b-49a6-8612-c9c6ec89a856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568833339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1568833339
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.55138061
Short name T233
Test name
Test status
Simulation time 85343981584 ps
CPU time 140.31 seconds
Started Apr 28 04:54:26 PM PDT 24
Finished Apr 28 04:56:47 PM PDT 24
Peak memory 220692 kb
Host smart-03256ee9-5b87-4075-9059-6de5d92d553f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55138061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.rom_ctrl_stress_all.55138061
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3704847012
Short name T56
Test name
Test status
Simulation time 2945409886 ps
CPU time 13.96 seconds
Started Apr 28 04:54:28 PM PDT 24
Finished Apr 28 04:54:42 PM PDT 24
Peak memory 211684 kb
Host smart-f0bb16ec-9a10-43b9-937d-a01a2bf14af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704847012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3704847012
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3577926468
Short name T190
Test name
Test status
Simulation time 162967609461 ps
CPU time 554.87 seconds
Started Apr 28 04:54:24 PM PDT 24
Finished Apr 28 05:03:40 PM PDT 24
Peak memory 218144 kb
Host smart-bf6196fb-6a78-456c-810e-504f00f7f3fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577926468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3577926468
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2980365541
Short name T335
Test name
Test status
Simulation time 6235977522 ps
CPU time 56.99 seconds
Started Apr 28 04:54:26 PM PDT 24
Finished Apr 28 04:55:24 PM PDT 24
Peak memory 215380 kb
Host smart-e0894e0f-b483-4151-9097-092803d15f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980365541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2980365541
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2601407927
Short name T156
Test name
Test status
Simulation time 14914744694 ps
CPU time 33.6 seconds
Started Apr 28 04:54:28 PM PDT 24
Finished Apr 28 04:55:02 PM PDT 24
Peak memory 212132 kb
Host smart-96f53096-cbbd-4760-8fe9-f58eafaeae3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2601407927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2601407927
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2450112000
Short name T10
Test name
Test status
Simulation time 13694357754 ps
CPU time 39.28 seconds
Started Apr 28 04:54:28 PM PDT 24
Finished Apr 28 04:55:07 PM PDT 24
Peak memory 218340 kb
Host smart-8b5cc49e-748f-4342-9af1-df60c1478529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450112000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2450112000
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.451400399
Short name T117
Test name
Test status
Simulation time 7383872608 ps
CPU time 33.41 seconds
Started Apr 28 04:54:28 PM PDT 24
Finished Apr 28 04:55:02 PM PDT 24
Peak memory 219472 kb
Host smart-b00e7220-9a66-41bc-8215-629ff4a761d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451400399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.451400399
Directory /workspace/9.rom_ctrl_stress_all/latest
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