Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2317944

1

T1

84

T2

51

T3

184736

full_word

1501323

1

T1

10

T2

7

T3

118629

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3818977	1			T1	94		T2	58		T3	303365
auto[TlIntgErrCmd]	88	1			T54	3		T55	6		T56	6
auto[TlIntgErrData]	99	1			T54	6		T55	9		T56	6
auto[TlIntgErrBoth]	103	1			T54	1		T55	5		T56	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

616068

1

T1

94

T2

58

T3

47024

auto[1]

3203199

1

T3

256341

T11

316057

T14

97129

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	260377	1			T1	84		T2	51		T3	18964
auto[TlIntgErrNone]	partial	auto[1]	2057308	1			T3	165772		T11	202062		T14	61573
auto[TlIntgErrNone]	full_word	auto[0]	355561	1			T1	10		T2	7		T3	28060
auto[TlIntgErrNone]	full_word	auto[1]	1145731	1			T3	90569		T11	113995		T14	35556
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T54	1		T55	2		T56	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T54	2		T55	4		T56	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T105	3		T113	1		T114	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T56	2		T110	1		-	-
auto[TlIntgErrData]	partial	auto[0]	43	1			T54	1		T55	4		T56	4
auto[TlIntgErrData]	partial	auto[1]	43	1			T54	4		T55	5		T56	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T105	1		T108	1		T107	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T54	1		T105	1		T108	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T55	3		T56	4		T111	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T54	1		T55	2		T56	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T106	1		T112	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T105	1		T106	1		T109	1