Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34953	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

401595

1

T3

8

T4

3

T5

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	129745	1			T3	93		T4	3		T5	3
values[0x0]	151151	1			T20	13928		T21	14045		T22	51828
values[0x1]	155652	1			T20	14383		T21	14293		T22	53448

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16586	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

419962

1

T3

55

T4

3

T5

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1851	1			T18	7		T131	1		T132	1
valid_sources[0x01]	1368	1			T37	2		T133	2		T93	1
valid_sources[0x02]	3206	1			T16	2		T134	1		T135	2
valid_sources[0x03]	1589	1			T3	1		T12	3		T134	2
valid_sources[0x04]	1131	1			T3	2		T136	2		T134	1
valid_sources[0x05]	3206	1			T18	2		T131	1		T135	2
valid_sources[0x06]	1340	1			T6	4		T16	1		T17	35
valid_sources[0x07]	1514	1			T14	1		T37	2		T134	2
valid_sources[0x08]	2005	1			T16	1		T18	1		T28	1
valid_sources[0x09]	1956	1			T3	3		T16	2		T13	5
valid_sources[0x0a]	1191	1			T16	1		T17	73		T37	2
valid_sources[0x0b]	2498	1			T137	2		T131	1		T135	1
valid_sources[0x0c]	2209	1			T3	1		T18	2		T37	1
valid_sources[0x0d]	1814	1			T3	3		T16	2		T18	10
valid_sources[0x0e]	1592	1			T3	3		T134	2		T131	1
valid_sources[0x0f]	2811	1			T6	1		T16	1		T37	4
valid_sources[0x10]	2842	1			T16	2		T15	1		T18	4
valid_sources[0x11]	3267	1			T12	2		T136	1		T138	6
valid_sources[0x12]	2327	1			T5	1		T14	3		T18	2
valid_sources[0x13]	1600	1			T3	4		T18	12		T37	1
valid_sources[0x14]	2198	1			T6	1		T14	2		T37	1
valid_sources[0x15]	1179	1			T14	1		T18	6		T131	1
valid_sources[0x16]	1218	1			T16	1		T37	1		T11	1
valid_sources[0x17]	1568	1			T6	1		T37	3		T11	14
valid_sources[0x18]	1216	1			T37	4		T76	17		T131	1
valid_sources[0x19]	2857	1			T28	1		T12	7		T136	3
valid_sources[0x1a]	1941	1			T18	3		T37	1		T136	2
valid_sources[0x1b]	1812	1			T136	3		T131	1		T135	1
valid_sources[0x1c]	1488	1			T16	3		T18	1		T134	4
valid_sources[0x1d]	2345	1			T6	1		T132	2		T139	2
valid_sources[0x1e]	1795	1			T13	1		T134	1		T137	1
valid_sources[0x1f]	2153	1			T3	1		T14	1		T37	1
valid_sources[0x20]	1583	1			T18	3		T37	1		T12	3
valid_sources[0x21]	1584	1			T37	1		T19	2		T13	4
valid_sources[0x22]	1896	1			T14	2		T11	5		T131	1
valid_sources[0x23]	1851	1			T37	1		T134	1		T131	1
valid_sources[0x24]	1143	1			T16	1		T37	1		T19	10
valid_sources[0x25]	1269	1			T14	3		T17	19		T37	1
valid_sources[0x26]	1199	1			T3	3		T14	1		T37	2
valid_sources[0x27]	1693	1			T16	1		T14	1		T37	1
valid_sources[0x28]	1481	1			T76	24		T134	4		T133	1
valid_sources[0x29]	1133	1			T37	1		T137	1		T131	1
valid_sources[0x2a]	1699	1			T131	1		T91	2		T135	1
valid_sources[0x2b]	1086	1			T18	3		T137	1		T131	1
valid_sources[0x2c]	1194	1			T28	1		T19	2		T140	6
valid_sources[0x2d]	1459	1			T131	2		T132	1		T141	1
valid_sources[0x2e]	1343	1			T134	4		T137	1		T135	2
valid_sources[0x2f]	1535	1			T19	2		T131	1		T132	1
valid_sources[0x30]	1885	1			T13	2		T76	51		T136	1
valid_sources[0x31]	2271	1			T140	1		T132	1		T93	2
valid_sources[0x32]	1495	1			T18	1		T12	13		T136	1
valid_sources[0x33]	1801	1			T37	3		T136	3		T137	1
valid_sources[0x34]	2623	1			T6	1		T12	3		T131	1
valid_sources[0x35]	1584	1			T37	2		T19	5		T135	2
valid_sources[0x36]	1435	1			T18	2		T19	2		T140	7
valid_sources[0x37]	1529	1			T6	5		T11	15		T136	4
valid_sources[0x38]	1480	1			T17	18		T37	1		T136	1
valid_sources[0x39]	2884	1			T37	2		T137	1		T131	2
valid_sources[0x3a]	2341	1			T18	2		T19	1		T140	2
valid_sources[0x3b]	1659	1			T16	1		T134	3		T137	1
valid_sources[0x3c]	1367	1			T6	1		T14	1		T15	1
valid_sources[0x3d]	2198	1			T37	1		T11	1		T12	1
valid_sources[0x3e]	1500	1			T13	11		T138	2		T132	1
valid_sources[0x3f]	1847	1			T14	1		T18	11		T13	4
valid_sources[0x40]	1033	1			T3	3		T14	3		T37	4
valid_sources[0x41]	1080	1			T16	1		T37	1		T12	1
valid_sources[0x42]	2815	1			T14	1		T137	1		T131	1
valid_sources[0x43]	1605	1			T18	14		T37	3		T12	3
valid_sources[0x44]	1267	1			T3	3		T93	7		T142	1
valid_sources[0x45]	1605	1			T16	5		T37	2		T131	2
valid_sources[0x46]	2610	1			T37	2		T134	2		T132	1
valid_sources[0x47]	1240	1			T17	45		T136	1		T134	1
valid_sources[0x48]	1503	1			T3	3		T8	17		T17	68
valid_sources[0x49]	1388	1			T18	3		T37	2		T136	1
valid_sources[0x4a]	2156	1			T15	1		T37	3		T12	1
valid_sources[0x4b]	1719	1			T6	2		T18	2		T37	3
valid_sources[0x4c]	2116	1			T4	1		T6	1		T8	41
valid_sources[0x4d]	1403	1			T14	1		T37	2		T11	7
valid_sources[0x4e]	1755	1			T3	1		T37	1		T134	1
valid_sources[0x4f]	1578	1			T3	2		T18	8		T37	1
valid_sources[0x50]	1434	1			T4	1		T14	1		T12	3
valid_sources[0x51]	1341	1			T12	5		T137	1		T131	2
valid_sources[0x52]	1730	1			T18	5		T13	1		T132	2
valid_sources[0x53]	1857	1			T14	1		T37	1		T75	2
valid_sources[0x54]	2202	1			T14	2		T18	9		T134	3
valid_sources[0x55]	1600	1			T3	8		T37	1		T134	4
valid_sources[0x56]	1178	1			T6	1		T37	1		T12	7
valid_sources[0x57]	2539	1			T18	8		T37	2		T136	1
valid_sources[0x58]	1398	1			T12	5		T13	1		T134	8
valid_sources[0x59]	1439	1			T14	2		T37	1		T131	2
valid_sources[0x5a]	1290	1			T3	1		T37	1		T136	1
valid_sources[0x5b]	1993	1			T6	1		T37	2		T134	2
valid_sources[0x5c]	1430	1			T134	3		T131	2		T135	4
valid_sources[0x5d]	1297	1			T14	2		T37	3		T137	1
valid_sources[0x5e]	1407	1			T134	2		T137	1		T131	1
valid_sources[0x5f]	1435	1			T14	2		T18	3		T12	1
valid_sources[0x60]	1774	1			T16	1		T131	2		T135	3
valid_sources[0x61]	1134	1			T14	1		T18	2		T37	4
valid_sources[0x62]	1838	1			T16	6		T18	1		T37	1
valid_sources[0x63]	2261	1			T6	3		T37	2		T13	8
valid_sources[0x64]	1680	1			T13	7		T134	1		T137	2
valid_sources[0x65]	1966	1			T14	1		T131	2		T135	2
valid_sources[0x66]	2178	1			T37	1		T19	5		T136	1
valid_sources[0x67]	1526	1			T16	1		T14	1		T140	1
valid_sources[0x68]	1181	1			T37	1		T134	3		T135	3
valid_sources[0x69]	1197	1			T14	4		T18	5		T37	1
valid_sources[0x6a]	2622	1			T37	2		T134	1		T137	3
valid_sources[0x6b]	2983	1			T6	1		T37	1		T12	2
valid_sources[0x6c]	1281	1			T3	1		T37	4		T134	6
valid_sources[0x6d]	2154	1			T3	4		T16	1		T14	4
valid_sources[0x6e]	2153	1			T16	1		T18	3		T12	2
valid_sources[0x6f]	1727	1			T16	1		T37	2		T12	6
valid_sources[0x70]	1648	1			T131	1		T132	2		T133	4
valid_sources[0x71]	1789	1			T18	1		T11	5		T13	1
valid_sources[0x72]	2174	1			T6	1		T16	1		T18	5
valid_sources[0x73]	1301	1			T37	2		T11	1		T131	1
valid_sources[0x74]	1676	1			T37	6		T19	1		T13	1
valid_sources[0x75]	2066	1			T16	3		T131	1		T135	1
valid_sources[0x76]	1212	1			T13	8		T134	1		T137	1
valid_sources[0x77]	1159	1			T6	1		T37	2		T143	1
valid_sources[0x78]	1587	1			T3	1		T14	1		T50	6
valid_sources[0x79]	1546	1			T16	1		T18	4		T136	1
valid_sources[0x7a]	1161	1			T11	5		T136	2		T137	1
valid_sources[0x7b]	3078	1			T3	2		T14	1		T133	6
valid_sources[0x7c]	2313	1			T16	1		T14	2		T37	1
valid_sources[0x7d]	1900	1			T6	1		T18	8		T140	2
valid_sources[0x7e]	1327	1			T134	2		T144	1		T48	1
valid_sources[0x7f]	1316	1			T14	6		T15	1		T37	4
valid_sources[0x80]	1167	1			T6	3		T14	1		T18	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

103030

1

T3

8

T4

3

T5

3

values[0x0]

all_enables

biggest_size

149844

1

T20

13828

T21

13916

T22

51353

values[0x1]

all_enables

biggest_size

148721

1

T20

13807

T21

13653

T22

51076

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36308	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

314383

1

T3

19

T4

15

T5

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	91480	1			T1	1		T3	32		T4	34
values[0x0]	120238	1			T33	1		T34	6		T35	10
values[0x1]	138973	1			T34	5		T36	1		T35	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18407	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

332284

1

T3

21

T4

19

T5

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1417	1			T132	2		T30	2		T20	101
valid_sources[0x01]	1364	1			T12	1		T69	1		T138	1
valid_sources[0x02]	1082	1			T6	9		T145	1		T146	1
valid_sources[0x03]	1778	1			T92	1		T93	2		T147	1
valid_sources[0x04]	1674	1			T145	1		T20	134		T148	3
valid_sources[0x05]	1731	1			T15	2		T12	1		T20	119
valid_sources[0x06]	1878	1			T93	4		T145	1		T95	2
valid_sources[0x07]	1659	1			T7	1		T149	1		T150	1
valid_sources[0x08]	1557	1			T151	1		T20	128		T25	2
valid_sources[0x09]	1609	1			T12	2		T93	1		T94	1
valid_sources[0x0a]	1114	1			T152	1		T92	1		T93	2
valid_sources[0x0b]	1929	1			T18	8		T132	1		T24	1
valid_sources[0x0c]	1404	1			T12	1		T137	1		T93	1
valid_sources[0x0d]	1178	1			T149	1		T153	1		T145	1
valid_sources[0x0e]	966	1			T12	1		T20	114		T154	4
valid_sources[0x0f]	1612	1			T12	1		T41	12		T155	5
valid_sources[0x10]	1636	1			T132	2		T156	2		T157	1
valid_sources[0x11]	1449	1			T16	1		T93	1		T20	125
valid_sources[0x12]	1531	1			T158	1		T153	1		T130	2
valid_sources[0x13]	1331	1			T12	1		T42	33		T159	1
valid_sources[0x14]	1297	1			T146	1		T151	1		T20	106
valid_sources[0x15]	1406	1			T29	1		T92	1		T93	1
valid_sources[0x16]	1150	1			T3	1		T12	3		T136	2
valid_sources[0x17]	2077	1			T20	104		T25	1		T160	1
valid_sources[0x18]	805	1			T138	2		T52	4		T92	1
valid_sources[0x19]	1727	1			T9	3		T69	1		T92	1
valid_sources[0x1a]	1631	1			T9	5		T35	1		T136	1
valid_sources[0x1b]	1144	1			T51	5		T158	2		T149	1
valid_sources[0x1c]	1172	1			T3	1		T12	2		T129	1
valid_sources[0x1d]	1361	1			T12	2		T152	1		T161	1
valid_sources[0x1e]	936	1			T149	1		T93	2		T157	3
valid_sources[0x1f]	1825	1			T16	1		T20	123		T162	14
valid_sources[0x20]	1461	1			T12	1		T163	1		T146	1
valid_sources[0x21]	1293	1			T149	1		T93	1		T20	87
valid_sources[0x22]	1230	1			T95	2		T20	110		T61	3
valid_sources[0x23]	1385	1			T35	3		T29	7		T163	1
valid_sources[0x24]	1480	1			T10	1		T132	1		T149	1
valid_sources[0x25]	1362	1			T69	1		T145	2		T95	1
valid_sources[0x26]	1278	1			T92	1		T149	1		T93	2
valid_sources[0x27]	1622	1			T12	1		T158	1		T74	1
valid_sources[0x28]	1439	1			T92	1		T145	1		T95	1
valid_sources[0x29]	1180	1			T3	1		T33	1		T163	1
valid_sources[0x2a]	1086	1			T3	1		T137	1		T158	1
valid_sources[0x2b]	1836	1			T3	1		T43	1		T20	103
valid_sources[0x2c]	1049	1			T16	1		T15	3		T11	8
valid_sources[0x2d]	1035	1			T129	1		T132	1		T158	1
valid_sources[0x2e]	1810	1			T12	1		T73	1		T161	1
valid_sources[0x2f]	1326	1			T129	1		T163	2		T149	1
valid_sources[0x30]	1321	1			T70	1		T158	1		T73	1
valid_sources[0x31]	1277	1			T163	1		T145	1		T156	1
valid_sources[0x32]	1108	1			T161	1		T151	2		T159	1
valid_sources[0x33]	1499	1			T129	2		T149	1		T20	134
valid_sources[0x34]	1555	1			T138	1		T92	1		T20	109
valid_sources[0x35]	1243	1			T12	1		T92	1		T153	1
valid_sources[0x36]	1630	1			T6	1		T137	1		T52	3
valid_sources[0x37]	1188	1			T3	1		T129	2		T92	1
valid_sources[0x38]	1791	1			T16	2		T12	1		T153	2
valid_sources[0x39]	1321	1			T34	1		T149	1		T150	1
valid_sources[0x3a]	1062	1			T137	1		T93	5		T145	2
valid_sources[0x3b]	1307	1			T158	2		T145	1		T43	1
valid_sources[0x3c]	1302	1			T3	2		T15	3		T152	1
valid_sources[0x3d]	1338	1			T158	2		T149	2		T145	1
valid_sources[0x3e]	1738	1			T9	3		T34	1		T163	1
valid_sources[0x3f]	1156	1			T152	1		T47	1		T150	6
valid_sources[0x40]	1196	1			T16	1		T149	1		T145	1
valid_sources[0x41]	1089	1			T157	3		T20	102		T164	3
valid_sources[0x42]	1413	1			T12	1		T149	3		T151	1
valid_sources[0x43]	930	1			T145	1		T20	136		T61	1
valid_sources[0x44]	1651	1			T29	2		T163	1		T138	2
valid_sources[0x45]	1054	1			T15	2		T163	1		T137	1
valid_sources[0x46]	1686	1			T12	2		T165	1		T152	1
valid_sources[0x47]	1418	1			T145	1		T43	1		T20	125
valid_sources[0x48]	1706	1			T132	1		T91	64		T92	1
valid_sources[0x49]	956	1			T43	1		T130	1		T159	1
valid_sources[0x4a]	1295	1			T69	1		T152	2		T149	1
valid_sources[0x4b]	1351	1			T132	2		T93	4		T156	1
valid_sources[0x4c]	1495	1			T158	1		T92	1		T145	2
valid_sources[0x4d]	1301	1			T92	1		T93	1		T94	2
valid_sources[0x4e]	1757	1			T15	1		T149	1		T93	2
valid_sources[0x4f]	1513	1			T158	1		T166	4		T95	3
valid_sources[0x50]	1081	1			T12	1		T94	2		T20	110
valid_sources[0x51]	963	1			T15	5		T145	3		T95	8
valid_sources[0x52]	1553	1			T137	1		T161	1		T47	1
valid_sources[0x53]	2142	1			T12	1		T93	1		T130	2
valid_sources[0x54]	1783	1			T4	34		T163	1		T132	1
valid_sources[0x55]	1225	1			T16	1		T74	1		T130	1
valid_sources[0x56]	1296	1			T73	1		T149	1		T167	32
valid_sources[0x57]	1171	1			T163	1		T137	1		T146	1
valid_sources[0x58]	1493	1			T137	1		T95	1		T156	2
valid_sources[0x59]	1527	1			T14	32		T138	1		T137	2
valid_sources[0x5a]	1464	1			T16	1		T15	1		T18	10
valid_sources[0x5b]	1489	1			T16	1		T20	121		T25	1
valid_sources[0x5c]	1435	1			T18	14		T153	1		T156	1
valid_sources[0x5d]	1566	1			T16	1		T93	1		T166	5
valid_sources[0x5e]	1241	1			T3	1		T93	1		T145	1
valid_sources[0x5f]	1178	1			T35	2		T136	1		T163	1
valid_sources[0x60]	1393	1			T18	6		T93	3		T145	3
valid_sources[0x61]	1449	1			T12	2		T163	1		T158	2
valid_sources[0x62]	1246	1			T13	29		T151	1		T159	2
valid_sources[0x63]	1137	1			T15	1		T12	2		T132	3
valid_sources[0x64]	1488	1			T94	2		T168	1		T20	117
valid_sources[0x65]	1054	1			T129	3		T137	1		T149	1
valid_sources[0x66]	898	1			T3	1		T136	1		T132	1
valid_sources[0x67]	1941	1			T136	1		T158	1		T93	1
valid_sources[0x68]	1125	1			T3	1		T12	1		T34	1
valid_sources[0x69]	1244	1			T9	3		T163	1		T92	1
valid_sources[0x6a]	1276	1			T3	2		T153	1		T95	4
valid_sources[0x6b]	1851	1			T169	1		T146	1		T20	110
valid_sources[0x6c]	925	1			T149	1		T153	1		T20	107
valid_sources[0x6d]	1130	1			T136	5		T138	1		T130	1
valid_sources[0x6e]	1582	1			T153	1		T157	1		T20	131
valid_sources[0x6f]	986	1			T3	1		T16	1		T30	1
valid_sources[0x70]	1260	1			T145	1		T150	1		T20	119
valid_sources[0x71]	1181	1			T15	1		T18	7		T12	1
valid_sources[0x72]	1569	1			T137	2		T149	1		T93	2
valid_sources[0x73]	1390	1			T29	4		T170	1		T132	2
valid_sources[0x74]	1434	1			T92	1		T93	4		T145	1
valid_sources[0x75]	1261	1			T12	2		T158	1		T145	1
valid_sources[0x76]	1193	1			T6	5		T12	2		T132	1
valid_sources[0x77]	1319	1			T12	1		T163	1		T20	126
valid_sources[0x78]	947	1			T75	32		T35	1		T92	1
valid_sources[0x79]	945	1			T93	2		T30	1		T159	1
valid_sources[0x7a]	1265	1			T163	1		T149	1		T93	1
valid_sources[0x7b]	823	1			T18	11		T136	1		T149	1
valid_sources[0x7c]	1193	1			T69	1		T158	1		T95	13
valid_sources[0x7d]	1186	1			T18	12		T163	1		T132	1
valid_sources[0x7e]	1695	1			T136	7		T150	1		T151	1
valid_sources[0x7f]	1160	1			T3	1		T16	1		T136	1
valid_sources[0x80]	1173	1			T93	1		T157	2		T20	120

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

79920

1

T3

19

T4

15

T5

10

values[0x0]

all_enables

biggest_size

117202

1

T33

1

T34

2

T35

2

values[0x1]

all_enables

biggest_size

117261

1

T34

1

T69

1

T70

1