Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

739682

1

T3

85

T6

55

T8

74

full_word

466960

1

T3

8

T4

2

T5

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1206362	1			T3	93		T4	2		T5	2
auto[TlIntgErrCmd]	102	1			T56	6		T58	3		T59	7
auto[TlIntgErrData]	83	1			T56	3		T58	5		T59	5
auto[TlIntgErrBoth]	95	1			T56	1		T58	2		T59	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

209505

1

T3

93

T4

2

T5

2

auto[1]

997137

1

T20

88083

T21

91781

T22

343597

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	96834	1			T3	85		T6	55		T8	74
auto[TlIntgErrNone]	partial	auto[1]	642592	1			T20	55654		T21	59062		T22	221965
auto[TlIntgErrNone]	full_word	auto[0]	112549	1			T3	8		T4	2		T5	2
auto[TlIntgErrNone]	full_word	auto[1]	354387	1			T20	32429		T21	32719		T22	121632
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T56	4		T58	1		T59	3
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T56	1		T58	1		T59	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T56	1		T58	1		T59	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T59	1		T125	1		T122	1
auto[TlIntgErrData]	partial	auto[0]	32	1			T56	1		T58	1		T59	4
auto[TlIntgErrData]	partial	auto[1]	44	1			T56	2		T58	4		T59	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T77	1		T126	1		T124	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T79	1		T120	1		T126	2
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T58	1		T59	1		T121	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T56	1		T58	1		T59	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T59	1		T79	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T79	1		T128	1		T127	1