Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1079989

1

T1

128

T3

216

T4

63

full_word

671995

1

T1

11

T3

24

T4

11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1751654	1			T1	139		T3	240		T4	74
auto[TlIntgErrCmd]	112	1			T50	3		T51	8		T60	9
auto[TlIntgErrData]	117	1			T50	2		T51	8		T60	7
auto[TlIntgErrBoth]	101	1			T50	5		T51	4		T60	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

292509

1

T1

139

T3

240

T4

74

auto[1]

1459475

1

T14

41021

T15

361238

T16

357018

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	132272	1			T1	128		T3	216		T4	63
auto[TlIntgErrNone]	partial	auto[1]	947413	1			T14	26029		T15	236397		T16	232114
auto[TlIntgErrNone]	full_word	auto[0]	160068	1			T1	11		T3	24		T4	11
auto[TlIntgErrNone]	full_word	auto[1]	511901	1			T14	14992		T15	124841		T16	124904
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T50	1		T51	3		T60	6
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T50	2		T51	5		T60	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T111	1		T112	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T106	1		T110	1		T113	1
auto[TlIntgErrData]	partial	auto[0]	67	1			T50	2		T51	6		T60	5
auto[TlIntgErrData]	partial	auto[1]	44	1			T51	1		T60	2		T106	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T51	1		T114	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T106	1		T114	1		T109	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T50	3		T51	1		T60	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T50	2		T51	2		T60	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T51	1		T110	1		T112	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T115	1		T108	1		T116	1