Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39583	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

682242

1

T1

10

T3

30

T4

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	198435	1			T1	98		T3	307		T4	386
values[0x0]	256609	1			T13	23019		T14	12086		T15	36403
values[0x1]	266781	1			T13	24171		T14	12575		T15	37722

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19656	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

702169

1

T1

61

T3

178

T4

216

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2213	1			T4	5		T8	1		T10	1
valid_sources[0x01]	2586	1			T3	2		T4	2		T10	2
valid_sources[0x02]	3127	1			T3	3		T7	3		T10	1
valid_sources[0x03]	3255	1			T3	1		T4	1		T8	1
valid_sources[0x04]	3315	1			T3	1		T4	3		T8	1
valid_sources[0x05]	3053	1			T3	2		T4	1		T5	15
valid_sources[0x06]	1917	1			T4	2		T11	1		T13	246
valid_sources[0x07]	3202	1			T3	3		T4	3		T10	2
valid_sources[0x08]	2621	1			T4	2		T10	1		T13	246
valid_sources[0x09]	1953	1			T3	2		T8	1		T10	4
valid_sources[0x0a]	2620	1			T3	4		T10	1		T64	2
valid_sources[0x0b]	1908	1			T3	1		T4	2		T7	10
valid_sources[0x0c]	2453	1			T3	1		T4	1		T9	1
valid_sources[0x0d]	2138	1			T3	2		T4	4		T10	1
valid_sources[0x0e]	2804	1			T1	5		T4	4		T7	1
valid_sources[0x0f]	1810	1			T3	2		T4	2		T13	265
valid_sources[0x10]	2067	1			T4	2		T9	3		T10	2
valid_sources[0x11]	3002	1			T3	1		T4	3		T7	1
valid_sources[0x12]	2139	1			T4	1		T11	1		T13	234
valid_sources[0x13]	4073	1			T3	4		T4	2		T10	1
valid_sources[0x14]	2734	1			T3	2		T4	1		T10	2
valid_sources[0x15]	2068	1			T3	1		T11	2		T13	237
valid_sources[0x16]	4426	1			T4	3		T7	3		T64	1
valid_sources[0x17]	1697	1			T4	1		T8	2		T10	3
valid_sources[0x18]	2276	1			T3	1		T4	2		T8	1
valid_sources[0x19]	2723	1			T3	2		T4	1		T8	1
valid_sources[0x1a]	3421	1			T3	2		T4	2		T23	1
valid_sources[0x1b]	3104	1			T13	223		T16	1		T57	2
valid_sources[0x1c]	2600	1			T4	1		T10	3		T11	1
valid_sources[0x1d]	3689	1			T3	1		T8	1		T10	1
valid_sources[0x1e]	4005	1			T3	1		T7	4		T10	1
valid_sources[0x1f]	1964	1			T3	1		T4	5		T8	1
valid_sources[0x20]	3864	1			T8	1		T9	5		T10	1
valid_sources[0x21]	3170	1			T3	8		T4	3		T13	257
valid_sources[0x22]	2499	1			T11	1		T64	1		T13	271
valid_sources[0x23]	3907	1			T3	7		T4	1		T10	2
valid_sources[0x24]	3936	1			T4	1		T10	2		T13	255
valid_sources[0x25]	3065	1			T3	1		T5	57		T10	1
valid_sources[0x26]	1754	1			T3	1		T4	2		T10	1
valid_sources[0x27]	3378	1			T3	1		T4	2		T7	1
valid_sources[0x28]	2752	1			T4	1		T10	1		T11	1
valid_sources[0x29]	2606	1			T3	1		T4	2		T10	3
valid_sources[0x2a]	3822	1			T3	1		T4	3		T10	2
valid_sources[0x2b]	4306	1			T3	3		T4	1		T9	3
valid_sources[0x2c]	1776	1			T10	1		T11	1		T13	248
valid_sources[0x2d]	5247	1			T3	1		T4	2		T10	1
valid_sources[0x2e]	3420	1			T3	3		T4	1		T7	1
valid_sources[0x2f]	2900	1			T1	4		T4	1		T10	3
valid_sources[0x30]	3875	1			T3	1		T4	2		T10	1
valid_sources[0x31]	3207	1			T3	2		T4	2		T9	1
valid_sources[0x32]	2850	1			T3	1		T10	2		T11	1
valid_sources[0x33]	2655	1			T3	1		T10	2		T11	2
valid_sources[0x34]	2423	1			T3	2		T4	2		T8	1
valid_sources[0x35]	3226	1			T4	4		T11	1		T13	251
valid_sources[0x36]	3658	1			T4	1		T13	254		T14	118
valid_sources[0x37]	2443	1			T3	1		T4	1		T9	1
valid_sources[0x38]	3315	1			T3	4		T4	2		T13	251
valid_sources[0x39]	2320	1			T3	1		T4	1		T10	1
valid_sources[0x3a]	4005	1			T3	1		T4	1		T7	2
valid_sources[0x3b]	2444	1			T1	4		T13	244		T14	127
valid_sources[0x3c]	2895	1			T1	11		T3	1		T7	2
valid_sources[0x3d]	2473	1			T3	4		T7	1		T11	1
valid_sources[0x3e]	3676	1			T4	1		T10	1		T13	236
valid_sources[0x3f]	1972	1			T3	1		T4	1		T7	3
valid_sources[0x40]	3136	1			T4	1		T8	1		T10	2
valid_sources[0x41]	2602	1			T1	4		T3	1		T4	1
valid_sources[0x42]	2967	1			T4	2		T7	1		T13	285
valid_sources[0x43]	1638	1			T3	3		T4	4		T10	1
valid_sources[0x44]	2905	1			T3	2		T10	2		T13	226
valid_sources[0x45]	2385	1			T4	3		T13	241		T14	125
valid_sources[0x46]	2822	1			T3	1		T4	1		T9	2
valid_sources[0x47]	3538	1			T3	1		T12	28		T64	1
valid_sources[0x48]	3951	1			T1	2		T3	4		T4	2
valid_sources[0x49]	3310	1			T4	1		T8	2		T10	1
valid_sources[0x4a]	3645	1			T9	1		T10	2		T13	278
valid_sources[0x4b]	2755	1			T10	1		T11	1		T13	269
valid_sources[0x4c]	1664	1			T3	3		T4	1		T9	2
valid_sources[0x4d]	3262	1			T4	3		T10	4		T11	1
valid_sources[0x4e]	1881	1			T3	1		T4	1		T13	274
valid_sources[0x4f]	3396	1			T3	2		T10	1		T11	2
valid_sources[0x50]	2509	1			T4	1		T10	1		T13	257
valid_sources[0x51]	2943	1			T8	1		T10	1		T64	2
valid_sources[0x52]	3808	1			T3	7		T4	1		T11	2
valid_sources[0x53]	2174	1			T10	1		T13	243		T16	2
valid_sources[0x54]	1792	1			T8	1		T11	1		T64	1
valid_sources[0x55]	2688	1			T1	11		T3	2		T4	1
valid_sources[0x56]	1960	1			T3	1		T10	1		T11	1
valid_sources[0x57]	2280	1			T8	1		T10	1		T11	1
valid_sources[0x58]	2960	1			T4	2		T13	260		T14	134
valid_sources[0x59]	2451	1			T4	2		T8	1		T10	3
valid_sources[0x5a]	2975	1			T4	1		T9	1		T10	1
valid_sources[0x5b]	2324	1			T3	1		T4	2		T8	1
valid_sources[0x5c]	3111	1			T3	2		T4	1		T10	1
valid_sources[0x5d]	2964	1			T4	1		T10	1		T13	235
valid_sources[0x5e]	2583	1			T4	1		T10	1		T11	3
valid_sources[0x5f]	2075	1			T4	2		T11	2		T64	1
valid_sources[0x60]	2344	1			T4	1		T8	1		T13	235
valid_sources[0x61]	3130	1			T3	1		T4	3		T11	1
valid_sources[0x62]	2416	1			T3	2		T10	4		T13	254
valid_sources[0x63]	3098	1			T3	2		T4	1		T9	1
valid_sources[0x64]	1917	1			T3	5		T4	2		T11	1
valid_sources[0x65]	2931	1			T3	1		T4	3		T8	1
valid_sources[0x66]	3270	1			T3	3		T4	4		T9	1
valid_sources[0x67]	1932	1			T3	2		T8	1		T10	1
valid_sources[0x68]	2153	1			T9	2		T10	1		T11	1
valid_sources[0x69]	2175	1			T3	1		T4	3		T10	2
valid_sources[0x6a]	3575	1			T4	1		T10	1		T11	1
valid_sources[0x6b]	1654	1			T4	2		T7	3		T10	2
valid_sources[0x6c]	2065	1			T3	1		T4	6		T10	3
valid_sources[0x6d]	2872	1			T3	2		T4	2		T10	1
valid_sources[0x6e]	3019	1			T3	2		T7	1		T13	265
valid_sources[0x6f]	2597	1			T11	1		T13	283		T16	2
valid_sources[0x70]	3432	1			T4	2		T7	8		T9	7
valid_sources[0x71]	2476	1			T3	2		T4	2		T11	1
valid_sources[0x72]	3111	1			T4	1		T10	3		T13	244
valid_sources[0x73]	2267	1			T3	5		T10	1		T13	214
valid_sources[0x74]	2754	1			T4	5		T8	2		T10	1
valid_sources[0x75]	4870	1			T3	4		T10	1		T64	1
valid_sources[0x76]	3452	1			T3	2		T5	11		T7	3
valid_sources[0x77]	2997	1			T3	1		T13	264		T16	1
valid_sources[0x78]	2712	1			T1	1		T3	1		T4	1
valid_sources[0x79]	1750	1			T4	2		T8	1		T9	3
valid_sources[0x7a]	3198	1			T4	4		T10	2		T11	1
valid_sources[0x7b]	1833	1			T3	1		T10	1		T13	240
valid_sources[0x7c]	2825	1			T3	1		T4	2		T10	1
valid_sources[0x7d]	2828	1			T3	1		T8	1		T11	3
valid_sources[0x7e]	2569	1			T3	1		T4	1		T10	1
valid_sources[0x7f]	2337	1			T1	6		T7	5		T9	2
valid_sources[0x80]	3111	1			T3	3		T4	3		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

172751

1

T1

10

T3

30

T4

39

values[0x0]

all_enables

biggest_size

254347

1

T13

22824

T14

11976

T15

36080

values[0x1]

all_enables

biggest_size

255144

1

T13

23084

T14

11985

T15

36033

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54703	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

521600

1

T2

1

T3

63

T5

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	147325	1			T2	1		T3	128		T5	64
values[0x0]	199476	1			T6	6		T31	8		T32	4
values[0x1]	229502	1			T6	5		T31	10		T32	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26158	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

550145

1

T2

1

T3

79

T5

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2586	1			T3	2		T13	220		T14	143
valid_sources[0x01]	2062	1			T13	285		T56	1		T14	88
valid_sources[0x02]	2013	1			T13	219		T14	87		T80	3
valid_sources[0x03]	2171	1			T3	1		T13	159		T14	94
valid_sources[0x04]	2058	1			T8	1		T13	196		T14	126
valid_sources[0x05]	2605	1			T12	1		T13	169		T14	106
valid_sources[0x06]	2315	1			T3	1		T13	340		T14	136
valid_sources[0x07]	2528	1			T13	243		T14	129		T115	1
valid_sources[0x08]	2060	1			T9	1		T13	197		T14	101
valid_sources[0x09]	2060	1			T13	176		T14	117		T115	1
valid_sources[0x0a]	2191	1			T13	189		T48	1		T14	132
valid_sources[0x0b]	2061	1			T9	1		T13	196		T14	136
valid_sources[0x0c]	2571	1			T12	17		T13	300		T14	113
valid_sources[0x0d]	1866	1			T3	3		T12	4		T13	148
valid_sources[0x0e]	1900	1			T3	1		T8	1		T12	3
valid_sources[0x0f]	1773	1			T24	3		T13	235		T14	101
valid_sources[0x10]	2817	1			T13	287		T14	93		T59	3
valid_sources[0x11]	2189	1			T12	5		T13	204		T14	111
valid_sources[0x12]	2189	1			T13	136		T48	1		T14	85
valid_sources[0x13]	1924	1			T3	1		T12	7		T46	1
valid_sources[0x14]	2309	1			T8	1		T17	1		T13	253
valid_sources[0x15]	2537	1			T46	3		T13	180		T14	92
valid_sources[0x16]	2322	1			T13	201		T14	114		T43	1
valid_sources[0x17]	2561	1			T3	2		T13	270		T14	136
valid_sources[0x18]	1599	1			T13	154		T14	114		T43	1
valid_sources[0x19]	1934	1			T13	172		T14	65		T15	285
valid_sources[0x1a]	2235	1			T13	207		T14	121		T67	1
valid_sources[0x1b]	2183	1			T13	178		T14	85		T44	1
valid_sources[0x1c]	2435	1			T3	2		T32	1		T13	265
valid_sources[0x1d]	2506	1			T8	1		T12	1		T13	270
valid_sources[0x1e]	2144	1			T13	172		T14	78		T115	1
valid_sources[0x1f]	1917	1			T26	1		T13	209		T14	93
valid_sources[0x20]	1896	1			T3	2		T13	160		T14	130
valid_sources[0x21]	2112	1			T13	167		T58	1		T14	100
valid_sources[0x22]	1631	1			T3	2		T13	179		T14	91
valid_sources[0x23]	2238	1			T13	247		T14	100		T115	1
valid_sources[0x24]	2089	1			T13	282		T14	128		T15	317
valid_sources[0x25]	2065	1			T3	1		T13	255		T14	95
valid_sources[0x26]	2017	1			T8	1		T13	196		T14	100
valid_sources[0x27]	2446	1			T13	205		T14	113		T15	276
valid_sources[0x28]	2096	1			T32	1		T13	266		T14	82
valid_sources[0x29]	2111	1			T13	249		T14	112		T115	2
valid_sources[0x2a]	2059	1			T3	3		T13	263		T14	85
valid_sources[0x2b]	1883	1			T8	3		T13	271		T14	136
valid_sources[0x2c]	1791	1			T3	3		T13	205		T14	144
valid_sources[0x2d]	1695	1			T3	1		T13	197		T14	120
valid_sources[0x2e]	2378	1			T3	3		T13	211		T48	1
valid_sources[0x2f]	1741	1			T13	359		T14	95		T81	2
valid_sources[0x30]	2255	1			T3	2		T13	165		T14	105
valid_sources[0x31]	2815	1			T13	247		T56	3		T14	108
valid_sources[0x32]	2060	1			T13	192		T14	60		T43	1
valid_sources[0x33]	2334	1			T13	240		T14	112		T43	1
valid_sources[0x34]	2127	1			T13	272		T14	109		T43	1
valid_sources[0x35]	2355	1			T13	169		T47	96		T14	135
valid_sources[0x36]	2258	1			T9	1		T13	242		T14	91
valid_sources[0x37]	2240	1			T31	18		T13	244		T14	102
valid_sources[0x38]	1738	1			T9	1		T13	281		T57	2
valid_sources[0x39]	2640	1			T8	2		T13	231		T14	104
valid_sources[0x3a]	2208	1			T13	223		T14	109		T15	302
valid_sources[0x3b]	2127	1			T3	1		T13	234		T57	1
valid_sources[0x3c]	2315	1			T13	304		T14	59		T15	273
valid_sources[0x3d]	2305	1			T9	1		T23	36		T13	266
valid_sources[0x3e]	2241	1			T32	1		T13	260		T14	89
valid_sources[0x3f]	3326	1			T13	226		T14	110		T115	1
valid_sources[0x40]	1906	1			T13	246		T14	158		T59	1
valid_sources[0x41]	2348	1			T3	1		T13	230		T14	96
valid_sources[0x42]	2565	1			T13	260		T14	69		T43	2
valid_sources[0x43]	2534	1			T13	282		T56	1		T14	70
valid_sources[0x44]	2415	1			T3	1		T13	200		T14	150
valid_sources[0x45]	2097	1			T8	2		T64	2		T13	248
valid_sources[0x46]	2674	1			T9	1		T13	178		T14	108
valid_sources[0x47]	2799	1			T13	201		T14	108		T81	7
valid_sources[0x48]	2291	1			T9	1		T13	252		T14	159
valid_sources[0x49]	1959	1			T9	1		T46	1		T13	213
valid_sources[0x4a]	2611	1			T13	230		T14	91		T15	299
valid_sources[0x4b]	2061	1			T13	202		T14	100		T15	303
valid_sources[0x4c]	2247	1			T3	4		T9	1		T13	231
valid_sources[0x4d]	2192	1			T3	3		T13	181		T14	101
valid_sources[0x4e]	2093	1			T8	1		T13	237		T57	1
valid_sources[0x4f]	2177	1			T8	2		T13	282		T56	1
valid_sources[0x50]	2245	1			T13	272		T14	89		T15	292
valid_sources[0x51]	2063	1			T13	292		T14	84		T44	1
valid_sources[0x52]	1788	1			T13	188		T14	138		T15	324
valid_sources[0x53]	2039	1			T24	13		T13	156		T14	105
valid_sources[0x54]	2575	1			T13	192		T14	128		T15	316
valid_sources[0x55]	2179	1			T13	219		T14	124		T115	1
valid_sources[0x56]	2565	1			T46	1		T13	257		T14	105
valid_sources[0x57]	1876	1			T13	215		T14	120		T59	1
valid_sources[0x58]	2554	1			T9	1		T13	217		T14	97
valid_sources[0x59]	2061	1			T13	196		T14	94		T15	279
valid_sources[0x5a]	2173	1			T13	193		T14	139		T15	285
valid_sources[0x5b]	1747	1			T9	2		T13	126		T14	92
valid_sources[0x5c]	2424	1			T3	1		T64	7		T13	173
valid_sources[0x5d]	2590	1			T13	255		T58	1		T14	116
valid_sources[0x5e]	2302	1			T3	1		T8	1		T46	1
valid_sources[0x5f]	2670	1			T32	1		T13	175		T14	86
valid_sources[0x60]	2047	1			T13	212		T14	108		T80	1
valid_sources[0x61]	2385	1			T13	197		T57	1		T14	112
valid_sources[0x62]	2358	1			T13	204		T48	1		T14	123
valid_sources[0x63]	2092	1			T3	1		T8	1		T13	190
valid_sources[0x64]	2184	1			T46	2		T13	213		T57	3
valid_sources[0x65]	1758	1			T2	1		T3	2		T64	2
valid_sources[0x66]	2271	1			T13	221		T57	1		T14	84
valid_sources[0x67]	2135	1			T3	1		T13	279		T14	91
valid_sources[0x68]	2250	1			T13	177		T14	105		T15	306
valid_sources[0x69]	2644	1			T3	4		T46	1		T13	210
valid_sources[0x6a]	2571	1			T64	1		T13	193		T48	1
valid_sources[0x6b]	2990	1			T8	1		T13	240		T57	1
valid_sources[0x6c]	2479	1			T6	4		T13	237		T57	2
valid_sources[0x6d]	2529	1			T6	2		T13	294		T48	1
valid_sources[0x6e]	2457	1			T6	2		T9	1		T13	208
valid_sources[0x6f]	2089	1			T13	232		T14	127		T15	303
valid_sources[0x70]	2343	1			T13	223		T57	1		T14	64
valid_sources[0x71]	2247	1			T3	1		T9	1		T13	267
valid_sources[0x72]	2435	1			T13	229		T57	1		T14	98
valid_sources[0x73]	1871	1			T13	204		T14	71		T80	1
valid_sources[0x74]	2738	1			T13	202		T14	98		T67	1
valid_sources[0x75]	2015	1			T46	1		T13	231		T14	110
valid_sources[0x76]	2169	1			T3	1		T8	1		T46	2
valid_sources[0x77]	2448	1			T13	197		T14	77		T15	307
valid_sources[0x78]	2398	1			T3	1		T13	256		T14	156
valid_sources[0x79]	2140	1			T3	2		T13	176		T14	153
valid_sources[0x7a]	1665	1			T13	197		T14	75		T59	1
valid_sources[0x7b]	2827	1			T13	151		T14	148		T67	1
valid_sources[0x7c]	2332	1			T13	212		T14	138		T43	1
valid_sources[0x7d]	2903	1			T3	1		T13	189		T14	120
valid_sources[0x7e]	2458	1			T12	4		T13	164		T14	95
valid_sources[0x7f]	2054	1			T13	239		T14	111		T59	1
valid_sources[0x80]	2172	1			T13	271		T14	114		T59	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

132500

1

T2

1

T3

63

T5

36

values[0x0]

all_enables

biggest_size

194983

1

T6

2

T31

1

T32

3

values[0x1]

all_enables

biggest_size

194117

1

T6

1

T31

1

T13

19123