Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1254455

1

T1

88

T3

277

T4

347

full_word

795940

1

T1

10

T3

30

T4

39

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2050115	1			T1	98		T3	307		T4	386
auto[TlIntgErrCmd]	101	1			T61	2		T62	2		T63	4
auto[TlIntgErrData]	79	1			T61	3		T62	4		T63	4
auto[TlIntgErrBoth]	100	1			T61	5		T62	4		T63	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

336861

1

T1

98

T3

307

T4

386

auto[1]

1713534

1

T13

160172

T14

82618

T15

243999

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	147547	1			T1	88		T3	277		T4	347
auto[TlIntgErrNone]	partial	auto[1]	1106652	1			T13	105061		T14	53979		T15	158223
auto[TlIntgErrNone]	full_word	auto[0]	189178	1			T1	10		T3	30		T4	39
auto[TlIntgErrNone]	full_word	auto[1]	606738	1			T13	55111		T14	28639		T15	85776
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T61	1		T62	1		T63	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T61	1		T62	1		T63	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T119	1		T123	1		T127	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T125	1		T126	1		T116	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T61	2		T62	3		T63	3
auto[TlIntgErrData]	partial	auto[1]	31	1			T61	1		T63	1		T125	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T62	1		T127	1		T128	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T126	2		T119	1		T129	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T61	2		T63	1		T126	5
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T61	2		T62	4		T63	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T130	1		T120	1		T123	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T61	1		T122	2		T118	2