Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1388607

1

T2

255

T3

164

T9

60

full_word

880691

1

T2

31

T3

14

T9

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2268998	1			T2	286		T3	178		T9	66
auto[TlIntgErrCmd]	97	1			T54	3		T61	4		T62	4
auto[TlIntgErrData]	97	1			T54	3		T61	1		T62	3
auto[TlIntgErrBoth]	106	1			T54	4		T61	5		T62	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

370957

1

T2

286

T3

178

T9

66

auto[1]

1898341

1

T20

154759

T21

482572

T22

43104

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	162349	1			T2	255		T3	164		T9	60
auto[TlIntgErrNone]	partial	auto[1]	1225984	1			T20	99510		T21	311181		T22	27357
auto[TlIntgErrNone]	full_word	auto[0]	208477	1			T2	31		T3	14		T9	6
auto[TlIntgErrNone]	full_word	auto[1]	672188	1			T20	55249		T21	171391		T22	15747
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T54	1		T61	1		T62	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T54	2		T61	2		T62	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T113	1		T121	1		T122	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T61	1		T113	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T54	1		T61	1		T62	2
auto[TlIntgErrData]	partial	auto[1]	38	1			T54	2		T62	1		T110	5
auto[TlIntgErrData]	full_word	auto[0]	3	1			T114	1		T115	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	8	1			T113	1		T123	2		T116	2
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T54	3		T61	2		T110	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T54	1		T61	3		T62	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T111	1		T115	1		T124	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T112	1		T123	1		T125	1