Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1765391

1

T1

126

T3

213

T7

225

full_word

1131768

1

T1

7

T2

2

T3

18

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2896819	1			T1	133		T2	2		T3	231
auto[TlIntgErrCmd]	113	1			T55	5		T62	7		T63	8
auto[TlIntgErrData]	111	1			T55	9		T62	7		T63	7
auto[TlIntgErrBoth]	116	1			T55	6		T62	6		T63	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

468626

1

T1

133

T2

2

T3

231

auto[1]

2428533

1

T17

148090

T18

466455

T19

97273

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	199775	1			T1	126		T3	213		T7	225
auto[TlIntgErrNone]	partial	auto[1]	1565301	1			T17	95772		T18	301964		T19	61902
auto[TlIntgErrNone]	full_word	auto[0]	268710	1			T1	7		T2	2		T3	18
auto[TlIntgErrNone]	full_word	auto[1]	863033	1			T17	52318		T18	164491		T19	35371
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T62	5		T63	5		T110	1
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T55	5		T62	2		T63	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T111	1		T112	1		T113	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T114	1		T115	1		T112	3
auto[TlIntgErrData]	partial	auto[0]	47	1			T55	3		T62	4		T63	2
auto[TlIntgErrData]	partial	auto[1]	52	1			T55	5		T62	2		T63	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T62	1		T116	1		T117	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T55	1		T111	1		T116	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T55	1		T62	1		T63	4
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T55	4		T62	4		T63	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T55	1		T62	1		T118	1