Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53643	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1073362

1

T1

21

T3

78477

T6

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	303400	1			T1	163		T3	20214		T6	182
values[0x0]	404863	1			T3	29864		T11	23571		T17	28129
values[0x1]	418742	1			T3	30607		T11	24610		T17	29022

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27173	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1099832

1

T1

101

T3

79454

T6

120

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4103	1			T3	333		T10	3		T11	282
valid_sources[0x01]	4358	1			T3	298		T11	256		T46	4
valid_sources[0x02]	4321	1			T3	330		T11	212		T47	1
valid_sources[0x03]	4322	1			T3	270		T15	1		T11	257
valid_sources[0x04]	4685	1			T3	356		T10	3		T15	9
valid_sources[0x05]	4316	1			T3	298		T13	2		T11	326
valid_sources[0x06]	4066	1			T3	303		T11	233		T48	1
valid_sources[0x07]	4324	1			T3	338		T15	7		T11	317
valid_sources[0x08]	4246	1			T3	312		T6	5		T10	2
valid_sources[0x09]	4401	1			T3	316		T15	2		T11	199
valid_sources[0x0a]	4546	1			T3	306		T15	4		T11	338
valid_sources[0x0b]	4203	1			T3	343		T11	314		T47	1
valid_sources[0x0c]	4320	1			T3	331		T6	4		T11	328
valid_sources[0x0d]	4092	1			T3	304		T11	274		T48	1
valid_sources[0x0e]	4292	1			T3	304		T11	276		T48	3
valid_sources[0x0f]	3991	1			T3	339		T11	227		T46	6
valid_sources[0x10]	4296	1			T3	312		T15	3		T11	231
valid_sources[0x11]	4559	1			T1	32		T3	307		T10	2
valid_sources[0x12]	4458	1			T3	290		T11	190		T48	5
valid_sources[0x13]	4216	1			T3	323		T11	223		T48	1
valid_sources[0x14]	4256	1			T3	322		T11	289		T16	5
valid_sources[0x15]	4533	1			T3	337		T11	275		T16	1
valid_sources[0x16]	4768	1			T3	286		T11	242		T119	1
valid_sources[0x17]	4230	1			T3	315		T11	327		T47	2
valid_sources[0x18]	5086	1			T3	316		T15	3		T11	286
valid_sources[0x19]	4282	1			T3	308		T15	1		T11	343
valid_sources[0x1a]	4495	1			T3	308		T11	249		T47	4
valid_sources[0x1b]	4204	1			T3	297		T13	1		T11	242
valid_sources[0x1c]	4294	1			T3	341		T11	241		T47	2
valid_sources[0x1d]	4271	1			T3	318		T10	1		T11	241
valid_sources[0x1e]	4771	1			T3	337		T14	19		T11	257
valid_sources[0x1f]	4531	1			T3	314		T10	7		T11	217
valid_sources[0x20]	4388	1			T3	318		T6	3		T11	260
valid_sources[0x21]	4461	1			T1	7		T3	306		T11	229
valid_sources[0x22]	4170	1			T3	279		T15	2		T11	257
valid_sources[0x23]	4419	1			T3	333		T11	230		T16	2
valid_sources[0x24]	4195	1			T3	307		T11	256		T47	1
valid_sources[0x25]	4736	1			T1	4		T3	346		T10	2
valid_sources[0x26]	4258	1			T3	319		T6	6		T11	252
valid_sources[0x27]	4375	1			T3	316		T11	352		T48	5
valid_sources[0x28]	4135	1			T3	317		T15	1		T11	182
valid_sources[0x29]	4736	1			T3	301		T13	4		T11	263
valid_sources[0x2a]	4576	1			T3	329		T11	268		T12	1
valid_sources[0x2b]	3989	1			T3	310		T11	267		T41	2
valid_sources[0x2c]	4441	1			T1	10		T3	310		T6	5
valid_sources[0x2d]	4288	1			T3	287		T6	1		T11	310
valid_sources[0x2e]	4033	1			T3	323		T10	2		T15	6
valid_sources[0x2f]	4214	1			T3	293		T14	21		T11	235
valid_sources[0x30]	4332	1			T3	316		T15	2		T11	206
valid_sources[0x31]	4478	1			T3	299		T15	2		T11	253
valid_sources[0x32]	4757	1			T3	304		T15	1		T11	210
valid_sources[0x33]	5192	1			T3	281		T6	5		T10	2
valid_sources[0x34]	4377	1			T3	284		T11	224		T26	3
valid_sources[0x35]	4245	1			T3	290		T15	1		T11	264
valid_sources[0x36]	4658	1			T3	340		T15	2		T11	301
valid_sources[0x37]	4186	1			T3	340		T11	320		T47	1
valid_sources[0x38]	4221	1			T3	305		T11	192		T46	2
valid_sources[0x39]	4141	1			T3	317		T11	212		T76	2
valid_sources[0x3a]	4419	1			T3	300		T6	1		T11	257
valid_sources[0x3b]	4223	1			T1	3		T3	326		T11	215
valid_sources[0x3c]	4356	1			T3	334		T10	3		T15	3
valid_sources[0x3d]	4197	1			T3	291		T15	1		T11	255
valid_sources[0x3e]	4511	1			T3	334		T11	223		T47	1
valid_sources[0x3f]	4222	1			T3	305		T15	2		T11	235
valid_sources[0x40]	4893	1			T3	307		T11	243		T12	1
valid_sources[0x41]	4058	1			T3	307		T13	7		T11	219
valid_sources[0x42]	4188	1			T3	301		T11	198		T16	1
valid_sources[0x43]	4205	1			T3	300		T11	308		T16	1
valid_sources[0x44]	4291	1			T3	341		T15	2		T11	214
valid_sources[0x45]	4379	1			T3	308		T15	1		T11	201
valid_sources[0x46]	4700	1			T3	309		T11	228		T16	3
valid_sources[0x47]	4166	1			T3	289		T11	213		T47	3
valid_sources[0x48]	4318	1			T3	326		T11	254		T46	4
valid_sources[0x49]	4391	1			T3	341		T10	3		T11	234
valid_sources[0x4a]	4637	1			T3	336		T11	233		T46	3
valid_sources[0x4b]	4344	1			T1	7		T3	291		T11	224
valid_sources[0x4c]	5652	1			T3	315		T6	5		T10	4
valid_sources[0x4d]	4809	1			T3	306		T11	307		T46	1
valid_sources[0x4e]	5160	1			T3	338		T11	275		T16	1
valid_sources[0x4f]	4101	1			T3	332		T11	214		T48	3
valid_sources[0x50]	4869	1			T3	320		T10	1		T11	303
valid_sources[0x51]	4513	1			T3	332		T11	295		T16	1
valid_sources[0x52]	4175	1			T3	307		T11	240		T16	1
valid_sources[0x53]	4078	1			T3	296		T11	249		T16	1
valid_sources[0x54]	4586	1			T3	337		T11	254		T48	2
valid_sources[0x55]	4254	1			T3	340		T15	1		T11	321
valid_sources[0x56]	4658	1			T3	324		T10	2		T15	4
valid_sources[0x57]	4329	1			T3	297		T11	230		T46	5
valid_sources[0x58]	4398	1			T3	328		T11	240		T47	2
valid_sources[0x59]	4402	1			T3	288		T11	251		T47	1
valid_sources[0x5a]	4436	1			T3	334		T10	5		T15	3
valid_sources[0x5b]	5047	1			T3	320		T11	194		T120	2
valid_sources[0x5c]	4244	1			T3	284		T11	284		T16	4
valid_sources[0x5d]	4364	1			T3	326		T11	203		T47	1
valid_sources[0x5e]	4195	1			T3	305		T13	4		T11	284
valid_sources[0x5f]	4370	1			T3	282		T11	256		T16	1
valid_sources[0x60]	4591	1			T3	299		T13	2		T11	280
valid_sources[0x61]	4317	1			T3	329		T11	228		T16	1
valid_sources[0x62]	4222	1			T3	334		T11	248		T48	1
valid_sources[0x63]	4333	1			T3	291		T15	1		T11	290
valid_sources[0x64]	4083	1			T3	305		T11	275		T46	1
valid_sources[0x65]	4154	1			T3	303		T11	217		T120	3
valid_sources[0x66]	4156	1			T1	17		T3	352		T11	314
valid_sources[0x67]	4383	1			T3	349		T10	1		T11	266
valid_sources[0x68]	4371	1			T3	340		T6	1		T11	286
valid_sources[0x69]	4463	1			T3	320		T11	280		T46	3
valid_sources[0x6a]	4507	1			T1	4		T3	343		T11	242
valid_sources[0x6b]	4237	1			T3	303		T6	3		T15	1
valid_sources[0x6c]	4289	1			T3	312		T11	321		T16	1
valid_sources[0x6d]	4090	1			T3	314		T11	245		T48	1
valid_sources[0x6e]	4574	1			T3	340		T6	3		T10	1
valid_sources[0x6f]	4225	1			T3	301		T11	239		T46	2
valid_sources[0x70]	4507	1			T3	350		T6	5		T11	225
valid_sources[0x71]	4312	1			T3	300		T11	186		T16	1
valid_sources[0x72]	5308	1			T3	326		T6	16		T13	1
valid_sources[0x73]	4319	1			T1	6		T3	308		T11	287
valid_sources[0x74]	4767	1			T3	311		T11	200		T48	3
valid_sources[0x75]	4355	1			T3	333		T6	3		T11	258
valid_sources[0x76]	5006	1			T3	305		T10	6		T15	3
valid_sources[0x77]	4367	1			T1	2		T3	343		T11	200
valid_sources[0x78]	4186	1			T3	304		T11	265		T16	1
valid_sources[0x79]	4421	1			T3	312		T10	3		T13	2
valid_sources[0x7a]	4703	1			T3	325		T11	219		T48	1
valid_sources[0x7b]	4337	1			T3	323		T15	1		T11	300
valid_sources[0x7c]	4291	1			T3	297		T13	1		T11	263
valid_sources[0x7d]	4553	1			T3	339		T10	1		T11	246
valid_sources[0x7e]	4184	1			T3	335		T15	5		T11	276
valid_sources[0x7f]	4426	1			T3	343		T6	7		T11	224
valid_sources[0x80]	4236	1			T3	309		T15	14		T11	191

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

271434

1

T1

21

T3

19670

T6

13

values[0x0]

all_enables

biggest_size

401314

1

T3

29599

T11

23353

T17

27888

values[0x1]

all_enables

biggest_size

400614

1

T3

29208

T11

23572

T17

27776

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	81633	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

818817

1

T1

43

T3

61197

T4

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	228400	1			T1	96		T2	1		T3	16374
values[0x0]	311891	1			T3	23414		T4	9		T8	5
values[0x1]	360159	1			T3	26483		T4	11		T8	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37826	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

862624

1

T1

49

T3

64134

T4

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3325	1			T3	285		T11	221		T46	64
valid_sources[0x01]	3250	1			T3	200		T11	146		T121	4
valid_sources[0x02]	3965	1			T3	172		T11	192		T122	1
valid_sources[0x03]	3537	1			T3	248		T11	181		T38	1
valid_sources[0x04]	3447	1			T3	294		T11	211		T12	1
valid_sources[0x05]	3429	1			T3	295		T11	199		T42	1
valid_sources[0x06]	3516	1			T3	259		T11	195		T12	1
valid_sources[0x07]	3514	1			T3	217		T6	9		T11	222
valid_sources[0x08]	3219	1			T1	1		T3	228		T7	1
valid_sources[0x09]	3574	1			T3	314		T11	216		T40	1
valid_sources[0x0a]	3461	1			T3	265		T7	1		T11	250
valid_sources[0x0b]	3445	1			T3	379		T33	2		T11	186
valid_sources[0x0c]	3643	1			T3	309		T4	1		T7	1
valid_sources[0x0d]	3301	1			T3	250		T11	196		T120	2
valid_sources[0x0e]	3730	1			T3	208		T11	205		T78	1
valid_sources[0x0f]	3399	1			T3	168		T7	1		T11	185
valid_sources[0x10]	3474	1			T3	319		T7	1		T11	157
valid_sources[0x11]	3745	1			T3	323		T11	171		T50	1
valid_sources[0x12]	3317	1			T3	193		T11	224		T30	1
valid_sources[0x13]	3594	1			T3	311		T11	241		T123	1
valid_sources[0x14]	3340	1			T3	288		T11	208		T121	3
valid_sources[0x15]	2941	1			T3	263		T11	188		T12	1
valid_sources[0x16]	3928	1			T3	325		T11	235		T77	1
valid_sources[0x17]	3237	1			T3	258		T6	1		T11	213
valid_sources[0x18]	3930	1			T3	239		T10	2		T11	214
valid_sources[0x19]	4059	1			T3	224		T11	173		T80	1
valid_sources[0x1a]	3297	1			T3	216		T10	3		T11	241
valid_sources[0x1b]	3572	1			T3	277		T11	186		T45	1
valid_sources[0x1c]	3393	1			T3	255		T7	2		T11	167
valid_sources[0x1d]	3040	1			T3	255		T11	170		T124	1
valid_sources[0x1e]	3937	1			T3	305		T11	181		T40	1
valid_sources[0x1f]	3070	1			T3	270		T4	1		T11	212
valid_sources[0x20]	3661	1			T1	1		T3	320		T11	220
valid_sources[0x21]	3529	1			T3	218		T4	2		T25	1
valid_sources[0x22]	3658	1			T3	286		T10	2		T11	169
valid_sources[0x23]	3221	1			T3	279		T10	1		T11	182
valid_sources[0x24]	3801	1			T1	2		T3	270		T10	1
valid_sources[0x25]	3360	1			T3	279		T11	165		T76	1
valid_sources[0x26]	3467	1			T3	280		T11	211		T12	1
valid_sources[0x27]	3286	1			T3	243		T11	181		T120	1
valid_sources[0x28]	3220	1			T3	212		T11	244		T125	1
valid_sources[0x29]	3664	1			T1	2		T3	262		T25	3
valid_sources[0x2a]	3186	1			T3	265		T6	9		T11	222
valid_sources[0x2b]	3243	1			T3	272		T7	1		T11	186
valid_sources[0x2c]	3331	1			T1	1		T3	284		T6	3
valid_sources[0x2d]	3479	1			T3	179		T14	3		T11	222
valid_sources[0x2e]	3733	1			T1	2		T3	264		T6	3
valid_sources[0x2f]	3298	1			T1	2		T3	269		T11	173
valid_sources[0x30]	3437	1			T3	265		T11	168		T66	1
valid_sources[0x31]	3508	1			T1	1		T3	273		T11	219
valid_sources[0x32]	3427	1			T1	1		T3	216		T11	188
valid_sources[0x33]	3422	1			T3	280		T11	203		T126	2
valid_sources[0x34]	4344	1			T3	329		T11	216		T47	27
valid_sources[0x35]	3131	1			T1	2		T3	184		T6	5
valid_sources[0x36]	3456	1			T3	248		T11	198		T64	2
valid_sources[0x37]	3682	1			T1	5		T3	317		T10	1
valid_sources[0x38]	3712	1			T3	246		T11	222		T12	1
valid_sources[0x39]	3603	1			T3	221		T11	173		T12	1
valid_sources[0x3a]	3863	1			T3	252		T11	235		T120	2
valid_sources[0x3b]	3105	1			T3	315		T14	1		T11	187
valid_sources[0x3c]	3506	1			T3	219		T11	212		T47	4
valid_sources[0x3d]	3139	1			T3	213		T6	1		T10	1
valid_sources[0x3e]	3590	1			T3	291		T11	228		T40	2
valid_sources[0x3f]	3435	1			T3	209		T11	191		T120	1
valid_sources[0x40]	3658	1			T3	226		T4	1		T10	1
valid_sources[0x41]	3643	1			T1	2		T3	320		T7	1
valid_sources[0x42]	3404	1			T3	267		T4	1		T6	5
valid_sources[0x43]	3472	1			T3	338		T11	205		T127	1
valid_sources[0x44]	3576	1			T1	2		T3	230		T11	240
valid_sources[0x45]	3252	1			T3	189		T11	156		T29	2
valid_sources[0x46]	2980	1			T3	273		T11	154		T120	2
valid_sources[0x47]	3389	1			T1	2		T3	295		T11	198
valid_sources[0x48]	3196	1			T3	220		T7	1		T11	180
valid_sources[0x49]	3589	1			T1	2		T3	294		T11	201
valid_sources[0x4a]	3512	1			T3	265		T7	1		T11	157
valid_sources[0x4b]	3389	1			T3	220		T11	160		T124	2
valid_sources[0x4c]	3635	1			T3	235		T11	233		T49	1
valid_sources[0x4d]	3467	1			T3	271		T4	1		T6	3
valid_sources[0x4e]	3802	1			T3	291		T11	196		T40	1
valid_sources[0x4f]	3416	1			T3	281		T11	242		T128	1
valid_sources[0x50]	3919	1			T3	314		T11	198		T120	1
valid_sources[0x51]	3648	1			T3	224		T7	1		T11	233
valid_sources[0x52]	3566	1			T3	204		T11	195		T76	1
valid_sources[0x53]	3178	1			T3	283		T11	209		T129	1
valid_sources[0x54]	3327	1			T3	270		T10	1		T11	195
valid_sources[0x55]	4075	1			T3	261		T11	218		T130	10
valid_sources[0x56]	3513	1			T3	263		T11	190		T12	1
valid_sources[0x57]	3350	1			T3	272		T6	4		T11	208
valid_sources[0x58]	3610	1			T3	233		T11	189		T12	2
valid_sources[0x59]	3277	1			T3	232		T7	1		T11	175
valid_sources[0x5a]	3639	1			T3	220		T10	1		T25	2
valid_sources[0x5b]	3281	1			T3	246		T11	209		T120	1
valid_sources[0x5c]	3606	1			T1	6		T3	303		T11	153
valid_sources[0x5d]	3343	1			T3	214		T10	1		T11	243
valid_sources[0x5e]	3589	1			T3	188		T11	183		T131	2
valid_sources[0x5f]	3674	1			T3	269		T4	2		T11	197
valid_sources[0x60]	4069	1			T3	308		T11	220		T120	1
valid_sources[0x61]	3180	1			T3	290		T10	2		T11	203
valid_sources[0x62]	3332	1			T3	241		T7	1		T11	193
valid_sources[0x63]	3280	1			T3	263		T11	159		T12	1
valid_sources[0x64]	3343	1			T3	217		T11	190		T78	1
valid_sources[0x65]	3580	1			T3	290		T7	1		T11	193
valid_sources[0x66]	3236	1			T3	268		T11	156		T12	1
valid_sources[0x67]	3379	1			T3	252		T11	214		T120	1
valid_sources[0x68]	3498	1			T3	309		T7	3		T25	1
valid_sources[0x69]	3813	1			T3	293		T11	183		T132	1
valid_sources[0x6a]	3193	1			T3	164		T11	156		T80	1
valid_sources[0x6b]	3179	1			T3	192		T13	32		T14	4
valid_sources[0x6c]	3694	1			T3	249		T7	2		T11	195
valid_sources[0x6d]	3634	1			T3	257		T7	1		T10	1
valid_sources[0x6e]	3243	1			T3	266		T11	184		T38	1
valid_sources[0x6f]	3396	1			T3	303		T10	1		T25	3
valid_sources[0x70]	3354	1			T3	272		T14	4		T11	186
valid_sources[0x71]	3491	1			T1	1		T3	333		T4	1
valid_sources[0x72]	3591	1			T3	266		T11	230		T17	69
valid_sources[0x73]	3136	1			T1	1		T3	202		T6	1
valid_sources[0x74]	3614	1			T1	1		T3	245		T33	1
valid_sources[0x75]	3562	1			T3	248		T14	1		T11	217
valid_sources[0x76]	3700	1			T3	264		T11	161		T76	1
valid_sources[0x77]	3299	1			T3	245		T7	1		T10	3
valid_sources[0x78]	3523	1			T3	237		T6	13		T11	220
valid_sources[0x79]	3579	1			T3	236		T6	1		T10	1
valid_sources[0x7a]	3688	1			T3	352		T6	5		T11	237
valid_sources[0x7b]	3408	1			T1	3		T3	244		T11	216
valid_sources[0x7c]	3453	1			T1	1		T3	206		T11	215
valid_sources[0x7d]	3371	1			T3	219		T11	173		T50	1
valid_sources[0x7e]	3886	1			T3	250		T11	190		T29	1
valid_sources[0x7f]	3504	1			T3	197		T7	1		T10	1
valid_sources[0x80]	3259	1			T3	208		T11	213		T42	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

207872

1

T1

43

T3

15415

T5

1

values[0x0]

all_enables

biggest_size

305547

1

T3

23019

T4

5

T8

3

values[0x1]

all_enables

biggest_size

305398

1

T3

22763

T4

2

T11

17116