Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1961649

1

T1

142

T3

149519

T6

169

full_word

1252782

1

T1

21

T3

92347

T6

13

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3214121	1			T1	163		T3	241866		T6	182
auto[TlIntgErrCmd]	108	1			T58	9		T59	4		T60	5
auto[TlIntgErrData]	97	1			T58	3		T59	1		T60	9
auto[TlIntgErrBoth]	105	1			T58	8		T59	5		T60	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

520186

1

T1

163

T3

37260

T6

182

auto[1]

2694245

1

T3

204606

T11

152515

T17

182598

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	222533	1			T1	142		T3	15504		T6	169
auto[TlIntgErrNone]	partial	auto[1]	1738831	1			T3	134015		T11	97023		T17	116800
auto[TlIntgErrNone]	full_word	auto[0]	297502	1			T1	21		T3	21756		T6	13
auto[TlIntgErrNone]	full_word	auto[1]	955255	1			T3	70591		T11	55492		T17	65798
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T58	4		T59	2		T60	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T58	5		T59	2		T60	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T108	2		T109	1		T106	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T105	1		T110	2		T111	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T58	2		T60	2		T104	4
auto[TlIntgErrData]	partial	auto[1]	45	1			T58	1		T59	1		T60	7
auto[TlIntgErrData]	full_word	auto[0]	3	1			T104	1		T109	1		T112	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T109	1		T113	1		T114	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T58	2		T59	3		T60	3
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T58	5		T59	2		T60	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T60	1		T115	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T58	1		T105	1		T116	1