Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 50108 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1031552 1 T1 6 T2 23 T3 11



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 289420 1 T1 83 T2 184 T3 88
values[0x0] 389154 1 T26 17627 T27 10048 T28 74272
values[0x1] 403086 1 T26 18202 T27 10150 T28 76725



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 25323 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1056337 1 T1 46 T2 110 T3 51



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 4075 1 T1 1 T2 1 T7 5
valid_sources[0x01] 3973 1 T7 3 T9 1 T107 2
valid_sources[0x02] 4124 1 T8 1 T9 1 T14 43
valid_sources[0x03] 4240 1 T107 1 T11 1 T89 2
valid_sources[0x04] 4067 1 T7 1 T9 1 T11 1
valid_sources[0x05] 4258 1 T2 1 T13 1 T107 4
valid_sources[0x06] 4152 1 T1 2 T2 1 T3 1
valid_sources[0x07] 4258 1 T1 3 T2 1 T4 1
valid_sources[0x08] 4282 1 T1 1 T7 3 T88 7
valid_sources[0x09] 4324 1 T2 1 T7 3 T9 1
valid_sources[0x0a] 4314 1 T2 1 T3 1 T7 1
valid_sources[0x0b] 4342 1 T1 1 T2 1 T7 3
valid_sources[0x0c] 4321 1 T2 1 T7 1 T9 1
valid_sources[0x0d] 4284 1 T2 2 T7 4 T107 10
valid_sources[0x0e] 4247 1 T1 1 T7 2 T107 2
valid_sources[0x0f] 4170 1 T1 1 T3 1 T7 3
valid_sources[0x10] 4119 1 T2 2 T7 3 T107 12
valid_sources[0x11] 4213 1 T1 1 T133 17 T90 2
valid_sources[0x12] 4483 1 T1 1 T7 3 T134 2
valid_sources[0x13] 4151 1 T2 1 T7 1 T135 3
valid_sources[0x14] 4045 1 T2 1 T3 1 T7 1
valid_sources[0x15] 4259 1 T2 1 T7 1 T91 1
valid_sources[0x16] 4441 1 T3 1 T7 2 T11 2
valid_sources[0x17] 4310 1 T7 2 T107 1 T136 19
valid_sources[0x18] 4395 1 T2 1 T7 3 T68 15
valid_sources[0x19] 4308 1 T7 2 T9 1 T134 1
valid_sources[0x1a] 4208 1 T1 1 T2 1 T3 2
valid_sources[0x1b] 4563 1 T3 1 T137 3 T135 1
valid_sources[0x1c] 4390 1 T68 40 T133 19 T134 1
valid_sources[0x1d] 4500 1 T1 2 T2 1 T7 1
valid_sources[0x1e] 4305 1 T7 2 T107 2 T11 1
valid_sources[0x1f] 4265 1 T2 1 T7 5 T107 1
valid_sources[0x20] 4188 1 T3 1 T7 1 T8 4
valid_sources[0x21] 4079 1 T3 1 T9 2 T11 1
valid_sources[0x22] 4257 1 T2 1 T7 2 T13 2
valid_sources[0x23] 4320 1 T2 1 T7 1 T13 1
valid_sources[0x24] 4243 1 T1 1 T7 1 T134 3
valid_sources[0x25] 4097 1 T1 1 T7 4 T9 1
valid_sources[0x26] 4143 1 T2 1 T7 1 T88 1
valid_sources[0x27] 4264 1 T7 1 T9 1 T107 5
valid_sources[0x28] 4340 1 T2 1 T3 1 T5 31
valid_sources[0x29] 4468 1 T7 2 T107 1 T134 1
valid_sources[0x2a] 4187 1 T1 1 T7 3 T14 25
valid_sources[0x2b] 4328 1 T7 4 T134 1 T138 4
valid_sources[0x2c] 4109 1 T2 1 T7 2 T13 4
valid_sources[0x2d] 4009 1 T7 2 T13 7 T107 1
valid_sources[0x2e] 4274 1 T2 2 T7 2 T91 2
valid_sources[0x2f] 4230 1 T1 1 T2 1 T4 1
valid_sources[0x30] 4209 1 T7 2 T107 1 T134 1
valid_sources[0x31] 4292 1 T2 1 T7 2 T107 3
valid_sources[0x32] 4180 1 T2 2 T3 1 T7 2
valid_sources[0x33] 4146 1 T2 2 T7 1 T88 8
valid_sources[0x34] 4252 1 T7 2 T13 7 T11 1
valid_sources[0x35] 4241 1 T3 2 T7 2 T107 1
valid_sources[0x36] 4053 1 T13 2 T88 6 T137 2
valid_sources[0x37] 4038 1 T11 1 T12 2 T134 3
valid_sources[0x38] 4329 1 T3 1 T7 1 T8 2
valid_sources[0x39] 3986 1 T2 1 T5 13 T9 1
valid_sources[0x3a] 4208 1 T3 1 T107 3 T11 3
valid_sources[0x3b] 4206 1 T1 1 T2 5 T3 1
valid_sources[0x3c] 4055 1 T3 3 T133 16 T134 1
valid_sources[0x3d] 4364 1 T1 1 T107 4 T11 2
valid_sources[0x3e] 4179 1 T2 3 T7 1 T109 34
valid_sources[0x3f] 4205 1 T2 2 T3 2 T7 2
valid_sources[0x40] 4360 1 T1 1 T2 2 T7 1
valid_sources[0x41] 3862 1 T7 3 T11 4 T90 1
valid_sources[0x42] 4336 1 T1 1 T2 1 T3 1
valid_sources[0x43] 4159 1 T1 1 T7 2 T107 4
valid_sources[0x44] 4395 1 T1 1 T2 3 T3 1
valid_sources[0x45] 4156 1 T2 1 T7 2 T13 1
valid_sources[0x46] 4161 1 T2 1 T3 2 T7 2
valid_sources[0x47] 4024 1 T2 1 T107 1 T134 1
valid_sources[0x48] 4261 1 T2 3 T3 1 T7 1
valid_sources[0x49] 4339 1 T2 1 T7 1 T107 3
valid_sources[0x4a] 4095 1 T1 3 T2 1 T3 1
valid_sources[0x4b] 4134 1 T2 1 T13 3 T11 4
valid_sources[0x4c] 4034 1 T3 1 T7 1 T11 1
valid_sources[0x4d] 4018 1 T7 3 T13 8 T107 3
valid_sources[0x4e] 4437 1 T1 1 T3 1 T13 2
valid_sources[0x4f] 4323 1 T7 1 T90 2 T137 2
valid_sources[0x50] 4336 1 T2 2 T3 2 T7 4
valid_sources[0x51] 4357 1 T7 3 T107 3 T88 2
valid_sources[0x52] 4169 1 T3 1 T23 2 T11 1
valid_sources[0x53] 4385 1 T1 1 T2 1 T7 1
valid_sources[0x54] 3967 1 T2 1 T7 1 T13 1
valid_sources[0x55] 4059 1 T7 2 T11 1 T134 2
valid_sources[0x56] 4265 1 T2 1 T7 1 T8 4
valid_sources[0x57] 4385 1 T107 1 T11 4 T134 2
valid_sources[0x58] 4227 1 T134 7 T137 6 T91 1
valid_sources[0x59] 4018 1 T11 1 T89 1 T137 2
valid_sources[0x5a] 4112 1 T3 1 T7 3 T13 3
valid_sources[0x5b] 4262 1 T1 1 T2 1 T3 2
valid_sources[0x5c] 4229 1 T7 3 T11 1 T134 1
valid_sources[0x5d] 4249 1 T2 1 T7 1 T11 1
valid_sources[0x5e] 4123 1 T7 2 T133 63 T134 1
valid_sources[0x5f] 4168 1 T7 1 T9 1 T134 2
valid_sources[0x60] 4172 1 T1 1 T7 1 T9 1
valid_sources[0x61] 3992 1 T2 2 T7 2 T11 1
valid_sources[0x62] 4021 1 T2 1 T7 1 T107 1
valid_sources[0x63] 4275 1 T1 2 T2 2 T7 1
valid_sources[0x64] 4112 1 T1 1 T2 1 T7 2
valid_sources[0x65] 4098 1 T7 4 T13 1 T107 3
valid_sources[0x66] 4299 1 T1 1 T2 1 T7 2
valid_sources[0x67] 4106 1 T2 2 T7 3 T8 3
valid_sources[0x68] 4190 1 T1 1 T7 2 T107 2
valid_sources[0x69] 4059 1 T1 1 T7 2 T8 2
valid_sources[0x6a] 4266 1 T2 1 T7 1 T11 1
valid_sources[0x6b] 4282 1 T2 1 T13 1 T11 1
valid_sources[0x6c] 4211 1 T2 3 T13 4 T134 2
valid_sources[0x6d] 4219 1 T2 3 T3 1 T11 3
valid_sources[0x6e] 4371 1 T3 1 T7 3 T107 9
valid_sources[0x6f] 4147 1 T107 1 T11 1 T134 2
valid_sources[0x70] 4027 1 T2 3 T7 1 T8 6
valid_sources[0x71] 4444 1 T13 4 T134 1 T139 7
valid_sources[0x72] 4123 1 T2 1 T7 3 T107 2
valid_sources[0x73] 4247 1 T13 1 T134 1 T140 3
valid_sources[0x74] 4145 1 T2 2 T7 1 T13 2
valid_sources[0x75] 4364 1 T1 1 T2 1 T3 1
valid_sources[0x76] 4569 1 T2 1 T7 3 T9 1
valid_sources[0x77] 4228 1 T1 1 T2 2 T7 1
valid_sources[0x78] 4324 1 T2 1 T7 1 T134 3
valid_sources[0x79] 3947 1 T7 3 T13 2 T134 1
valid_sources[0x7a] 3909 1 T7 1 T13 2 T107 1
valid_sources[0x7b] 4223 1 T3 2 T13 4 T107 1
valid_sources[0x7c] 4118 1 T2 1 T7 1 T8 1
valid_sources[0x7d] 4329 1 T7 2 T13 7 T107 3
valid_sources[0x7e] 4379 1 T2 1 T3 1 T107 4
valid_sources[0x7f] 4282 1 T1 1 T2 1 T3 1
valid_sources[0x80] 4605 1 T107 1 T11 1 T134 3



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 260238 1 T1 6 T2 23 T3 11
values[0x0] all_enables biggest_size 385705 1 T26 17495 T27 9990 T28 73649
values[0x1] all_enables biggest_size 385609 1 T26 17483 T27 9777 T28 73576


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 81294 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 796736 1 T1 22 T3 18 T4 14



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 221725 1 T1 32 T3 32 T4 26
values[0x0] 303573 1 T6 6 T10 10 T34 1
values[0x1] 352732 1 T6 4 T10 5 T35 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 37288 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 840742 1 T1 25 T3 22 T4 14



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3298 1 T25 1 T70 1 T39 1
valid_sources[0x01] 3164 1 T4 1 T141 1 T26 132
valid_sources[0x02] 3461 1 T11 3 T88 1 T75 2
valid_sources[0x03] 3177 1 T142 32 T143 1 T144 1
valid_sources[0x04] 3311 1 T88 2 T18 1 T91 2
valid_sources[0x05] 3245 1 T145 2 T141 3 T146 3
valid_sources[0x06] 3162 1 T11 1 T24 1 T77 2
valid_sources[0x07] 3216 1 T1 2 T143 1 T32 1
valid_sources[0x08] 3680 1 T1 1 T11 1 T47 2
valid_sources[0x09] 3625 1 T4 1 T11 2 T135 5
valid_sources[0x0a] 3563 1 T18 1 T147 2 T148 1
valid_sources[0x0b] 3068 1 T19 1 T149 1 T150 1
valid_sources[0x0c] 3223 1 T91 1 T135 9 T151 1
valid_sources[0x0d] 3439 1 T1 1 T8 11 T11 4
valid_sources[0x0e] 3180 1 T152 3 T143 1 T144 1
valid_sources[0x0f] 3383 1 T147 1 T39 1 T144 1
valid_sources[0x10] 3382 1 T49 1 T153 2 T154 1
valid_sources[0x11] 3631 1 T18 1 T155 1 T156 1
valid_sources[0x12] 3134 1 T143 1 T39 1 T140 1
valid_sources[0x13] 3257 1 T4 1 T157 32 T70 2
valid_sources[0x14] 3178 1 T26 136 T158 1 T27 65
valid_sources[0x15] 3530 1 T11 2 T25 2 T150 1
valid_sources[0x16] 3588 1 T1 1 T25 1 T49 1
valid_sources[0x17] 3250 1 T16 1 T143 1 T26 116
valid_sources[0x18] 3692 1 T156 1 T41 2 T151 2
valid_sources[0x19] 3527 1 T38 1 T159 1 T141 1
valid_sources[0x1a] 3373 1 T23 15 T24 1 T160 2
valid_sources[0x1b] 3551 1 T88 1 T147 1 T161 1
valid_sources[0x1c] 3183 1 T70 1 T162 32 T163 1
valid_sources[0x1d] 3058 1 T3 1 T4 1 T11 1
valid_sources[0x1e] 3609 1 T25 1 T146 4 T26 136
valid_sources[0x1f] 3786 1 T3 3 T11 1 T72 2
valid_sources[0x20] 3285 1 T11 1 T25 1 T164 1
valid_sources[0x21] 3215 1 T88 1 T165 1 T143 1
valid_sources[0x22] 3217 1 T166 1 T25 1 T143 1
valid_sources[0x23] 3454 1 T150 1 T156 2 T39 1
valid_sources[0x24] 3343 1 T24 1 T76 12 T70 3
valid_sources[0x25] 3492 1 T3 2 T25 1 T145 2
valid_sources[0x26] 3607 1 T25 1 T141 1 T26 169
valid_sources[0x27] 3466 1 T25 4 T143 1 T167 1
valid_sources[0x28] 3198 1 T164 2 T156 1 T168 3
valid_sources[0x29] 3429 1 T25 1 T91 1 T169 1
valid_sources[0x2a] 3320 1 T149 6 T26 131 T170 2
valid_sources[0x2b] 3556 1 T1 1 T143 2 T154 1
valid_sources[0x2c] 3848 1 T3 1 T145 2 T167 1
valid_sources[0x2d] 3737 1 T11 1 T165 1 T164 1
valid_sources[0x2e] 3718 1 T39 1 T140 1 T144 1
valid_sources[0x2f] 3507 1 T11 1 T88 1 T18 1
valid_sources[0x30] 3189 1 T165 1 T143 1 T171 4
valid_sources[0x31] 3889 1 T49 1 T70 1 T143 2
valid_sources[0x32] 3456 1 T18 3 T172 3 T26 192
valid_sources[0x33] 3679 1 T3 2 T144 4 T26 138
valid_sources[0x34] 3611 1 T4 1 T143 3 T173 1
valid_sources[0x35] 3182 1 T24 1 T25 1 T91 1
valid_sources[0x36] 3214 1 T4 1 T25 1 T143 1
valid_sources[0x37] 3297 1 T24 1 T148 1 T163 1
valid_sources[0x38] 3273 1 T1 2 T24 1 T174 1
valid_sources[0x39] 3090 1 T3 5 T24 1 T164 1
valid_sources[0x3a] 3358 1 T175 1 T140 1 T148 4
valid_sources[0x3b] 3411 1 T11 3 T19 1 T41 11
valid_sources[0x3c] 3306 1 T15 1 T25 1 T19 1
valid_sources[0x3d] 3250 1 T4 1 T25 1 T159 4
valid_sources[0x3e] 3418 1 T11 3 T18 1 T163 1
valid_sources[0x3f] 3179 1 T11 1 T176 1 T26 161
valid_sources[0x40] 3562 1 T9 5 T88 1 T25 1
valid_sources[0x41] 3172 1 T88 3 T143 1 T150 1
valid_sources[0x42] 3244 1 T69 2 T70 3 T143 1
valid_sources[0x43] 3596 1 T11 2 T165 2 T143 1
valid_sources[0x44] 3153 1 T135 5 T143 1 T172 1
valid_sources[0x45] 3305 1 T165 1 T172 1 T168 4
valid_sources[0x46] 3599 1 T165 1 T147 3 T140 2
valid_sources[0x47] 3255 1 T19 1 T152 1 T143 3
valid_sources[0x48] 3483 1 T11 1 T24 1 T173 1
valid_sources[0x49] 3208 1 T143 1 T145 3 T160 2
valid_sources[0x4a] 3238 1 T24 1 T164 1 T26 164
valid_sources[0x4b] 3426 1 T3 4 T9 3 T11 2
valid_sources[0x4c] 3385 1 T19 1 T177 15 T144 2
valid_sources[0x4d] 3308 1 T68 64 T154 1 T26 167
valid_sources[0x4e] 3143 1 T3 1 T178 1 T70 3
valid_sources[0x4f] 4096 1 T139 18 T47 2 T91 1
valid_sources[0x50] 3339 1 T143 1 T150 2 T179 2
valid_sources[0x51] 3734 1 T11 1 T25 1 T91 1
valid_sources[0x52] 3208 1 T19 1 T180 1 T151 1
valid_sources[0x53] 3517 1 T25 1 T91 1 T179 2
valid_sources[0x54] 3180 1 T19 2 T152 2 T164 1
valid_sources[0x55] 3219 1 T165 2 T156 1 T173 3
valid_sources[0x56] 3303 1 T3 1 T47 6 T149 2
valid_sources[0x57] 3595 1 T88 1 T143 1 T159 2
valid_sources[0x58] 3207 1 T4 1 T25 1 T178 1
valid_sources[0x59] 4295 1 T91 2 T143 1 T146 1
valid_sources[0x5a] 3210 1 T4 1 T6 7 T20 1
valid_sources[0x5b] 4025 1 T91 1 T150 1 T145 2
valid_sources[0x5c] 3138 1 T24 1 T69 4 T91 1
valid_sources[0x5d] 3464 1 T152 1 T181 1 T141 1
valid_sources[0x5e] 3948 1 T11 1 T77 3 T182 1
valid_sources[0x5f] 3294 1 T11 1 T25 1 T19 1
valid_sources[0x60] 3567 1 T47 3 T143 1 T151 2
valid_sources[0x61] 3280 1 T18 1 T25 1 T150 1
valid_sources[0x62] 4125 1 T91 1 T70 2 T161 1
valid_sources[0x63] 3658 1 T1 1 T150 1 T38 1
valid_sources[0x64] 2966 1 T4 1 T11 2 T179 10
valid_sources[0x65] 3674 1 T18 1 T25 2 T77 1
valid_sources[0x66] 3760 1 T18 2 T91 1 T143 1
valid_sources[0x67] 2949 1 T88 3 T183 1 T182 1
valid_sources[0x68] 3550 1 T88 2 T70 1 T153 2
valid_sources[0x69] 3439 1 T35 1 T25 2 T91 2
valid_sources[0x6a] 3180 1 T4 1 T24 1 T147 1
valid_sources[0x6b] 3180 1 T4 2 T156 1 T26 147
valid_sources[0x6c] 3028 1 T74 1 T143 2 T26 177
valid_sources[0x6d] 3253 1 T135 4 T38 1 T161 1
valid_sources[0x6e] 2996 1 T11 1 T25 1 T150 1
valid_sources[0x6f] 3330 1 T1 1 T11 1 T89 32
valid_sources[0x70] 3118 1 T9 4 T24 1 T165 2
valid_sources[0x71] 3472 1 T91 1 T141 1 T184 1
valid_sources[0x72] 3378 1 T143 1 T160 6 T146 2
valid_sources[0x73] 3529 1 T165 1 T145 1 T26 160
valid_sources[0x74] 3716 1 T11 1 T156 4 T153 1
valid_sources[0x75] 3107 1 T11 1 T143 3 T146 1
valid_sources[0x76] 3360 1 T3 6 T25 1 T156 2
valid_sources[0x77] 3565 1 T24 1 T18 1 T77 1
valid_sources[0x78] 3191 1 T1 1 T91 1 T160 2
valid_sources[0x79] 3966 1 T1 1 T41 1 T151 2
valid_sources[0x7a] 3226 1 T165 1 T143 2 T144 2
valid_sources[0x7b] 3439 1 T18 1 T143 1 T171 3
valid_sources[0x7c] 5158 1 T88 1 T73 1 T143 1
valid_sources[0x7d] 3239 1 T1 1 T88 1 T165 1
valid_sources[0x7e] 3467 1 T3 1 T143 1 T141 1
valid_sources[0x7f] 3334 1 T11 3 T185 1 T18 2
valid_sources[0x80] 3324 1 T11 4 T88 1 T143 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 202192 1 T1 22 T3 18 T4 14
values[0x0] all_enables biggest_size 297027 1 T6 1 T10 2 T35 3
values[0x1] all_enables biggest_size 297517 1 T77 1 T186 1 T42 3

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