Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1893716

1

T1

77

T2

161

T3

77

full_word

1204636

1

T1

6

T2

23

T3

11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3098052	1			T1	83		T2	184		T3	88
auto[TlIntgErrCmd]	100	1			T65	8		T66	6		T67	3
auto[TlIntgErrData]	93	1			T65	4		T66	6		T67	5
auto[TlIntgErrBoth]	107	1			T65	8		T66	8		T67	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

501056

1

T1

83

T2

184

T3

88

auto[1]

2597296

1

T26

118791

T27

61753

T28

484693

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	215146	1			T1	77		T2	161		T3	77
auto[TlIntgErrNone]	partial	auto[1]	1678293	1			T26	77159		T27	38538		T28	310249
auto[TlIntgErrNone]	full_word	auto[0]	285768	1			T1	6		T2	23		T3	11
auto[TlIntgErrNone]	full_word	auto[1]	918845	1			T26	41632		T27	23215		T28	174444
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T65	4		T66	3		T67	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T65	4		T66	3		T67	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T124	1		T125	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T126	1		T127	1		T123	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T66	3		T67	4		T119	2
auto[TlIntgErrData]	partial	auto[1]	38	1			T65	3		T66	2		T67	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T65	1		T128	1		T129	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T66	1		T130	1		T129	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T65	4		T66	4		T119	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T65	4		T66	4		T67	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T119	1		T121	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T122	1		T125	1		T131	1