Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55893	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1215791

1

T1

15

T2

22

T4

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	336907	1			T1	206		T2	285		T4	79
values[0x0]	459482	1			T6	56750		T16	20588		T17	25582
values[0x1]	475295	1			T6	59223		T16	21260		T17	26357

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28489	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1243195

1

T1

119

T2

177

T4

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4501	1			T4	1		T6	424		T47	1
valid_sources[0x01]	4298	1			T6	292		T46	1		T74	2
valid_sources[0x02]	5166	1			T6	1154		T94	5		T16	249
valid_sources[0x03]	6754	1			T6	760		T12	1		T72	11
valid_sources[0x04]	3936	1			T93	1		T96	2		T110	3
valid_sources[0x05]	3881	1			T1	1		T6	24		T11	8
valid_sources[0x06]	4970	1			T1	1		T6	583		T15	2
valid_sources[0x07]	3844	1			T1	2		T4	2		T6	144
valid_sources[0x08]	5576	1			T6	301		T14	10		T47	1
valid_sources[0x09]	4477	1			T1	1		T6	517		T46	1
valid_sources[0x0a]	4982	1			T1	1		T6	353		T47	2
valid_sources[0x0b]	4567	1			T1	1		T6	208		T47	1
valid_sources[0x0c]	4863	1			T1	1		T6	501		T110	1
valid_sources[0x0d]	5712	1			T1	1		T6	268		T72	3
valid_sources[0x0e]	4012	1			T1	1		T5	1		T6	355
valid_sources[0x0f]	5802	1			T6	1186		T72	1		T73	1
valid_sources[0x10]	4629	1			T1	1		T6	823		T93	2
valid_sources[0x11]	4479	1			T6	168		T46	2		T47	2
valid_sources[0x12]	5155	1			T1	1		T6	128		T46	1
valid_sources[0x13]	4506	1			T1	1		T6	780		T47	2
valid_sources[0x14]	5622	1			T6	93		T46	1		T15	1
valid_sources[0x15]	4690	1			T1	2		T5	1		T6	1122
valid_sources[0x16]	4057	1			T5	1		T6	285		T94	1
valid_sources[0x17]	5996	1			T1	1		T6	1287		T73	1
valid_sources[0x18]	4464	1			T1	3		T6	440		T47	1
valid_sources[0x19]	5379	1			T6	351		T11	6		T12	1
valid_sources[0x1a]	4270	1			T1	1		T6	399		T46	2
valid_sources[0x1b]	4402	1			T1	2		T2	34		T6	129
valid_sources[0x1c]	4646	1			T1	2		T6	598		T12	3
valid_sources[0x1d]	5784	1			T1	1		T6	1148		T46	1
valid_sources[0x1e]	4715	1			T1	2		T6	282		T11	2
valid_sources[0x1f]	4053	1			T1	1		T2	35		T5	2
valid_sources[0x20]	4624	1			T1	2		T5	1		T6	590
valid_sources[0x21]	4709	1			T1	1		T6	539		T94	1
valid_sources[0x22]	4873	1			T6	1259		T14	21		T47	1
valid_sources[0x23]	4852	1			T6	190		T47	4		T15	2
valid_sources[0x24]	5836	1			T1	3		T4	4		T5	1
valid_sources[0x25]	4160	1			T5	1		T6	661		T47	3
valid_sources[0x26]	4155	1			T5	2		T6	379		T94	3
valid_sources[0x27]	3744	1			T4	17		T5	1		T6	173
valid_sources[0x28]	5946	1			T1	1		T5	1		T6	906
valid_sources[0x29]	4624	1			T5	1		T6	354		T11	1
valid_sources[0x2a]	5712	1			T6	1674		T47	1		T15	4
valid_sources[0x2b]	4535	1			T4	2		T5	1		T6	187
valid_sources[0x2c]	4943	1			T1	1		T5	1		T6	498
valid_sources[0x2d]	4346	1			T6	266		T111	2		T112	4
valid_sources[0x2e]	4838	1			T1	1		T5	1		T6	87
valid_sources[0x2f]	4302	1			T47	1		T73	1		T93	2
valid_sources[0x30]	6367	1			T1	1		T6	1536		T11	3
valid_sources[0x31]	4924	1			T1	3		T4	2		T6	1086
valid_sources[0x32]	4946	1			T1	2		T5	3		T6	369
valid_sources[0x33]	5026	1			T5	1		T6	24		T46	1
valid_sources[0x34]	4063	1			T1	1		T5	1		T6	116
valid_sources[0x35]	4891	1			T1	1		T6	661		T47	1
valid_sources[0x36]	6429	1			T1	1		T6	1853		T11	3
valid_sources[0x37]	6263	1			T1	1		T5	1		T6	2033
valid_sources[0x38]	4463	1			T1	3		T4	3		T5	1
valid_sources[0x39]	5812	1			T1	2		T6	1050		T47	1
valid_sources[0x3a]	5768	1			T6	563		T47	1		T96	6
valid_sources[0x3b]	3751	1			T47	3		T94	3		T113	2
valid_sources[0x3c]	4544	1			T1	3		T5	3		T6	211
valid_sources[0x3d]	3944	1			T1	2		T93	1		T94	2
valid_sources[0x3e]	4255	1			T6	198		T93	1		T94	2
valid_sources[0x3f]	5813	1			T6	234		T46	1		T47	1
valid_sources[0x40]	4608	1			T1	2		T5	1		T6	483
valid_sources[0x41]	4833	1			T6	1026		T15	1		T73	1
valid_sources[0x42]	4246	1			T1	1		T4	6		T6	153
valid_sources[0x43]	7296	1			T6	1420		T47	1		T73	1
valid_sources[0x44]	5398	1			T1	1		T5	1		T6	699
valid_sources[0x45]	5416	1			T6	372		T93	3		T94	1
valid_sources[0x46]	4066	1			T2	30		T5	2		T6	96
valid_sources[0x47]	4917	1			T1	2		T4	2		T6	564
valid_sources[0x48]	5660	1			T1	1		T5	1		T6	803
valid_sources[0x49]	4980	1			T1	2		T4	4		T6	536
valid_sources[0x4a]	6192	1			T1	1		T5	1		T6	278
valid_sources[0x4b]	5065	1			T1	2		T6	1188		T72	3
valid_sources[0x4c]	4947	1			T1	1		T4	1		T6	643
valid_sources[0x4d]	3904	1			T1	1		T5	1		T6	4
valid_sources[0x4e]	5544	1			T6	1137		T15	1		T94	1
valid_sources[0x4f]	5007	1			T1	1		T5	1		T6	1054
valid_sources[0x50]	5724	1			T6	266		T11	1		T93	1
valid_sources[0x51]	4498	1			T6	220		T15	1		T73	3
valid_sources[0x52]	4957	1			T1	3		T5	1		T6	742
valid_sources[0x53]	4596	1			T1	1		T5	1		T46	1
valid_sources[0x54]	4647	1			T6	757		T11	2		T15	4
valid_sources[0x55]	3831	1			T1	1		T5	1		T6	176
valid_sources[0x56]	4698	1			T1	2		T6	794		T35	26
valid_sources[0x57]	5512	1			T6	1631		T9	3		T12	3
valid_sources[0x58]	5387	1			T1	2		T6	1600		T46	1
valid_sources[0x59]	3647	1			T1	1		T5	2		T6	116
valid_sources[0x5a]	4692	1			T6	465		T11	7		T94	1
valid_sources[0x5b]	4327	1			T1	1		T5	1		T94	1
valid_sources[0x5c]	3943	1			T1	1		T5	2		T6	356
valid_sources[0x5d]	4914	1			T4	1		T6	283		T15	1
valid_sources[0x5e]	4683	1			T1	1		T5	1		T6	275
valid_sources[0x5f]	4818	1			T6	506		T94	1		T110	3
valid_sources[0x60]	4415	1			T6	468		T94	1		T110	1
valid_sources[0x61]	6575	1			T1	2		T6	979		T94	1
valid_sources[0x62]	4482	1			T1	1		T6	407		T46	1
valid_sources[0x63]	5406	1			T1	2		T6	502		T46	2
valid_sources[0x64]	3790	1			T1	1		T4	4		T5	1
valid_sources[0x65]	5511	1			T1	1		T6	861		T12	1
valid_sources[0x66]	5114	1			T1	1		T47	1		T12	1
valid_sources[0x67]	4268	1			T1	1		T6	236		T15	2
valid_sources[0x68]	5657	1			T4	1		T6	922		T12	1
valid_sources[0x69]	5576	1			T1	2		T6	694		T46	3
valid_sources[0x6a]	4563	1			T1	1		T2	24		T5	1
valid_sources[0x6b]	5265	1			T6	205		T12	1		T72	7
valid_sources[0x6c]	4267	1			T1	1		T5	2		T6	402
valid_sources[0x6d]	4516	1			T1	1		T5	1		T6	672
valid_sources[0x6e]	5153	1			T5	1		T6	242		T46	4
valid_sources[0x6f]	5262	1			T1	1		T6	1295		T47	3
valid_sources[0x70]	5048	1			T5	1		T6	532		T47	2
valid_sources[0x71]	5756	1			T1	4		T5	2		T6	2055
valid_sources[0x72]	4511	1			T5	1		T6	584		T95	12
valid_sources[0x73]	5179	1			T1	1		T2	40		T6	1372
valid_sources[0x74]	4306	1			T5	1		T6	93		T15	1
valid_sources[0x75]	4717	1			T6	568		T15	4		T113	1
valid_sources[0x76]	5317	1			T1	1		T5	2		T6	1877
valid_sources[0x77]	4885	1			T5	1		T6	301		T46	1
valid_sources[0x78]	4816	1			T1	1		T46	1		T94	2
valid_sources[0x79]	7980	1			T4	1		T5	1		T6	828
valid_sources[0x7a]	4021	1			T1	2		T6	443		T12	2
valid_sources[0x7b]	5048	1			T5	1		T6	981		T112	3
valid_sources[0x7c]	3947	1			T1	1		T6	261		T46	1
valid_sources[0x7d]	4330	1			T1	1		T5	1		T12	1
valid_sources[0x7e]	5300	1			T1	1		T6	883		T46	1
valid_sources[0x7f]	4681	1			T6	376		T12	2		T73	2
valid_sources[0x80]	5354	1			T1	1		T6	370		T46	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

305890

1

T1

15

T2

22

T4

7

values[0x0]

all_enables

biggest_size

455398

1

T6

56220

T16

20408

T17

25349

values[0x1]

all_enables

biggest_size

454503

1

T6

56625

T16

20348

T17

25195

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	92724	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

940388

1

T4

13

T5

29

T6

112787

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	260310	1			T3	1		T4	32		T5	64
values[0x0]	357603	1			T6	43018		T7	2		T8	4
values[0x1]	415199	1			T6	49876		T7	1		T8	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42642	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

990470

1

T4

19

T5

33

T6

118738

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4050	1			T6	485		T31	2		T94	1
valid_sources[0x01]	4293	1			T6	498		T32	1		T46	1
valid_sources[0x02]	3665	1			T6	389		T14	1		T112	3
valid_sources[0x03]	4424	1			T6	622		T94	2		T112	3
valid_sources[0x04]	3769	1			T6	551		T113	1		T40	1
valid_sources[0x05]	3715	1			T6	219		T46	1		T16	273
valid_sources[0x06]	3882	1			T6	394		T31	1		T112	5
valid_sources[0x07]	3742	1			T6	529		T14	3		T16	193
valid_sources[0x08]	3929	1			T6	604		T35	64		T37	1
valid_sources[0x09]	4503	1			T6	410		T73	3		T39	1
valid_sources[0x0a]	3436	1			T6	383		T94	1		T113	1
valid_sources[0x0b]	4580	1			T6	704		T46	1		T113	1
valid_sources[0x0c]	3976	1			T6	507		T39	1		T16	130
valid_sources[0x0d]	3962	1			T6	370		T16	198		T17	210
valid_sources[0x0e]	4337	1			T6	374		T8	1		T16	413
valid_sources[0x0f]	3564	1			T6	262		T94	2		T16	84
valid_sources[0x10]	3959	1			T6	246		T94	1		T16	20
valid_sources[0x11]	4016	1			T6	405		T39	1		T16	144
valid_sources[0x12]	3508	1			T6	222		T39	1		T16	219
valid_sources[0x13]	4511	1			T6	383		T14	29		T42	25
valid_sources[0x14]	4055	1			T6	749		T16	35		T45	1
valid_sources[0x15]	3559	1			T6	342		T47	96		T16	47
valid_sources[0x16]	4128	1			T6	448		T60	1		T94	2
valid_sources[0x17]	3938	1			T6	445		T94	2		T16	100
valid_sources[0x18]	4668	1			T6	1100		T74	1		T112	2
valid_sources[0x19]	4568	1			T6	882		T94	1		T16	8
valid_sources[0x1a]	3817	1			T6	540		T16	149		T45	1
valid_sources[0x1b]	4367	1			T6	618		T31	3		T94	1
valid_sources[0x1c]	3965	1			T6	633		T94	1		T25	1
valid_sources[0x1d]	4010	1			T5	1		T6	382		T10	1
valid_sources[0x1e]	4405	1			T6	242		T7	2		T94	2
valid_sources[0x1f]	4065	1			T5	1		T6	603		T94	3
valid_sources[0x20]	3677	1			T6	287		T72	3		T94	1
valid_sources[0x21]	4117	1			T6	522		T16	133		T44	2
valid_sources[0x22]	3874	1			T6	389		T94	3		T111	25
valid_sources[0x23]	3791	1			T6	451		T113	1		T16	208
valid_sources[0x24]	3892	1			T6	311		T74	5		T16	459
valid_sources[0x25]	3767	1			T6	646		T37	1		T16	33
valid_sources[0x26]	3910	1			T6	787		T9	1		T16	11
valid_sources[0x27]	3585	1			T6	329		T74	1		T39	1
valid_sources[0x28]	4077	1			T4	32		T6	560		T39	1
valid_sources[0x29]	4293	1			T6	628		T25	1		T16	126
valid_sources[0x2a]	3980	1			T6	198		T46	1		T16	87
valid_sources[0x2b]	4024	1			T5	1		T6	624		T16	223
valid_sources[0x2c]	3709	1			T6	384		T16	91		T17	204
valid_sources[0x2d]	3896	1			T6	591		T112	1		T16	5
valid_sources[0x2e]	3653	1			T6	425		T10	1		T74	1
valid_sources[0x2f]	3821	1			T6	356		T8	1		T74	1
valid_sources[0x30]	3869	1			T6	416		T20	1		T25	1
valid_sources[0x31]	3831	1			T5	1		T6	529		T16	102
valid_sources[0x32]	4008	1			T6	654		T16	14		T27	1
valid_sources[0x33]	3818	1			T6	663		T39	1		T16	31
valid_sources[0x34]	3524	1			T5	3		T6	356		T46	1
valid_sources[0x35]	4624	1			T6	384		T112	2		T25	1
valid_sources[0x36]	4641	1			T6	456		T73	1		T16	322
valid_sources[0x37]	3898	1			T6	402		T9	2		T94	2
valid_sources[0x38]	4178	1			T6	364		T94	3		T74	1
valid_sources[0x39]	4571	1			T6	494		T74	1		T16	265
valid_sources[0x3a]	4105	1			T6	535		T113	1		T16	171
valid_sources[0x3b]	4794	1			T6	703		T39	1		T16	700
valid_sources[0x3c]	3985	1			T6	572		T72	1		T16	156
valid_sources[0x3d]	4218	1			T6	332		T73	3		T36	2
valid_sources[0x3e]	3739	1			T6	258		T46	3		T25	1
valid_sources[0x3f]	3905	1			T6	335		T46	1		T112	1
valid_sources[0x40]	3898	1			T6	325		T16	176		T114	1
valid_sources[0x41]	3887	1			T6	398		T73	3		T25	1
valid_sources[0x42]	4115	1			T6	339		T14	4		T16	337
valid_sources[0x43]	3942	1			T6	411		T113	1		T16	211
valid_sources[0x44]	4291	1			T6	713		T16	146		T44	1
valid_sources[0x45]	4010	1			T6	620		T26	10		T16	177
valid_sources[0x46]	4476	1			T6	430		T14	7		T16	452
valid_sources[0x47]	4362	1			T5	4		T6	755		T16	135
valid_sources[0x48]	3689	1			T6	419		T72	3		T37	2
valid_sources[0x49]	3486	1			T6	254		T16	10		T17	218
valid_sources[0x4a]	4416	1			T6	385		T112	1		T39	1
valid_sources[0x4b]	4117	1			T6	586		T46	1		T74	1
valid_sources[0x4c]	3580	1			T6	539		T16	111		T115	1
valid_sources[0x4d]	3949	1			T6	299		T16	322		T116	2
valid_sources[0x4e]	3593	1			T6	275		T94	1		T26	1
valid_sources[0x4f]	4123	1			T6	569		T16	21		T114	1
valid_sources[0x50]	3865	1			T6	360		T94	1		T74	1
valid_sources[0x51]	4028	1			T6	519		T94	1		T16	176
valid_sources[0x52]	3873	1			T6	551		T113	1		T74	1
valid_sources[0x53]	3540	1			T6	351		T16	155		T114	1
valid_sources[0x54]	3766	1			T6	364		T36	1		T16	103
valid_sources[0x55]	3924	1			T6	256		T8	1		T61	1
valid_sources[0x56]	4069	1			T6	298		T46	1		T16	206
valid_sources[0x57]	4898	1			T6	435		T9	1		T94	2
valid_sources[0x58]	4000	1			T6	444		T16	13		T116	2
valid_sources[0x59]	4076	1			T6	355		T113	1		T36	1
valid_sources[0x5a]	3939	1			T6	506		T16	92		T116	2
valid_sources[0x5b]	3515	1			T6	293		T113	1		T112	1
valid_sources[0x5c]	3989	1			T6	543		T113	1		T112	3
valid_sources[0x5d]	4195	1			T6	505		T14	5		T16	95
valid_sources[0x5e]	4108	1			T6	674		T16	8		T114	1
valid_sources[0x5f]	4247	1			T6	579		T16	8		T44	1
valid_sources[0x60]	4326	1			T5	3		T6	535		T16	90
valid_sources[0x61]	4108	1			T6	469		T16	271		T17	240
valid_sources[0x62]	4402	1			T6	368		T39	1		T16	142
valid_sources[0x63]	4187	1			T6	556		T10	1		T94	1
valid_sources[0x64]	3728	1			T6	281		T113	1		T16	265
valid_sources[0x65]	4217	1			T6	225		T113	1		T39	1
valid_sources[0x66]	4097	1			T6	656		T9	1		T16	290
valid_sources[0x67]	4071	1			T6	424		T16	262		T17	246
valid_sources[0x68]	4136	1			T6	587		T113	1		T25	1
valid_sources[0x69]	4136	1			T6	401		T46	3		T72	2
valid_sources[0x6a]	3708	1			T6	366		T39	1		T16	12
valid_sources[0x6b]	4412	1			T6	470		T16	362		T117	1
valid_sources[0x6c]	4262	1			T6	380		T16	96		T27	1
valid_sources[0x6d]	3650	1			T6	488		T16	165		T43	1
valid_sources[0x6e]	4362	1			T5	1		T6	453		T73	1
valid_sources[0x6f]	3931	1			T6	399		T37	2		T16	316
valid_sources[0x70]	4649	1			T6	852		T94	2		T113	2
valid_sources[0x71]	3640	1			T6	415		T16	175		T116	3
valid_sources[0x72]	4456	1			T6	715		T16	286		T45	1
valid_sources[0x73]	4305	1			T6	551		T112	2		T16	44
valid_sources[0x74]	4174	1			T5	6		T6	532		T39	1
valid_sources[0x75]	3834	1			T6	496		T13	20		T16	11
valid_sources[0x76]	4291	1			T5	3		T6	547		T16	637
valid_sources[0x77]	3679	1			T6	388		T73	3		T25	1
valid_sources[0x78]	4255	1			T6	416		T16	144		T17	207
valid_sources[0x79]	3435	1			T6	308		T46	1		T113	1
valid_sources[0x7a]	4073	1			T6	359		T16	371		T17	212
valid_sources[0x7b]	4266	1			T6	492		T9	1		T14	1
valid_sources[0x7c]	3942	1			T6	486		T16	79		T115	1
valid_sources[0x7d]	4144	1			T6	453		T46	2		T16	154
valid_sources[0x7e]	4277	1			T5	4		T6	792		T9	1
valid_sources[0x7f]	3919	1			T6	392		T94	5		T39	1
valid_sources[0x80]	3998	1			T6	493		T94	4		T111	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

238563

1

T4

13

T5

29

T6

28395

values[0x0]

all_enables

biggest_size

350103

1

T6

42199

T7

1

T8

3

values[0x1]

all_enables

biggest_size

351722

1

T6

42193

T8

1

T31

1