Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2215487

1

T1

191

T2

263

T4

72

full_word

1417191

1

T1

15

T2

22

T4

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3632408	1			T1	206		T2	285		T4	79
auto[TlIntgErrCmd]	92	1			T54	3		T55	3		T56	9
auto[TlIntgErrData]	84	1			T54	7		T55	6		T56	3
auto[TlIntgErrBoth]	94	1			T54	10		T55	1		T56	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

582809

1

T1

206

T2

285

T4

79

auto[1]

3049869

1

T6

379908

T16

134709

T17

169826

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	247528	1			T1	191		T2	263		T4	72
auto[TlIntgErrNone]	partial	auto[1]	1967709	1			T6	245714		T16	86445		T17	109639
auto[TlIntgErrNone]	full_word	auto[0]	335165	1			T1	15		T2	22		T4	7
auto[TlIntgErrNone]	full_word	auto[1]	1082006	1			T6	134194		T16	48264		T17	60187
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T54	1		T55	2		T56	3
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T54	2		T55	1		T56	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T101	1		T102	1		T106	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T98	1		T107	1		T108	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T54	3		T55	2		T56	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T54	4		T55	3		T56	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T105	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T55	1		T103	1		T109	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T54	5		T56	4		T100	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T54	5		T55	1		T56	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T98	1		T101	1		T103	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T98	1		T102	2		T107	1