Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.38	96.97	93.01	97.88	100.00	98.37	98.03

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	95.92	100.00	96.30	90.00	100.00	98.31	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	94.22	91.60	85.14	99.07		95.29	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	438	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
208	1	1
254	1	1
309	1	1
410	8	8
411	8	8
413	8	8
414	8	8
416	8	8
417	8	8
421	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
434	1	1
438	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       254
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T13
1	1	Covered	T1,T2,T4

 LINE       414
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       421
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T28,T29,T30
1	0	Not Covered

 LINE       423
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T13
1	0	Covered	T3,T9,T10

 LINE       434
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T31
1	0	Covered	T4,T5,T6
1	1	Covered	T7,T8,T32

 LINE       438
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T9,T10,T13
0	1	0	Covered	T3,T9,T10
1	0	0	Covered	T28,T29,T30

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T6,T16,T17	Yes	T6,T16,T17	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T6,*T16,*T17	Yes	T6,T16,T17	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T2,T4,T5	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T5,T6	Yes	T5,T6,T7	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T5,T6,T8	Yes	T5,T6,T7	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
regs_tl_i.a_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
regs_tl_o.a_ready	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_error	Yes	Yes	T6,T16,T17	Yes	T6,T16,T17	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T4,*T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T5,T6,T8	Yes	T5,T6,T7	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
keymgr_data_o.valid	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T5,T6,T9	Yes	T2,T5,T6	OUTPUT
kmac_data_i.error	No	Yes	T3,T23,T24	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T5,T6,T9	Yes	T4,T6,T9	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T6,T9,T10	Yes	T4,T5,T6	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	208	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	208	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	312034316	311867096	0	0
BusRomIndicesMatch_A	312023050	311862536	0	0
FpvSecCmFifoRptrCheck_A	312034316	0	0	0
FpvSecCmFifoWptrCheck_A	312034316	0	0	0
FpvSecCmRegWeOnehotCheck_A	312034316	70	0	0
KeymgrDataODataKnown_A	312034316	52778063	0	0
KeymgrDataODataKnown_AKnownEnable	312034316	311867096	0	0
KeymgrDataOValidKnown_A	312034316	311867096	0	0
KeymgrValidChk_A	312034316	0	0	315
KmacDataODataKnown_A	312034316	258972979	0	0
KmacDataODataKnown_AKnownEnable	312034316	311867096	0	0
KmacDataOValidKnown_A	312034316	311867096	0	0
PwrmgrDataChk_A	312034316	0	0	315
PwrmgrDataOKnown_A	312034316	311867096	0	0
RegsTlOAReadyKnown_A	312034316	311867096	0	0
RegsTlODDataKnown_A	312034316	11241915	0	0
RegsTlODDataKnown_AKnownEnable	312034316	311867096	0	0
RegsTlODValidKnown_A	312034316	311867096	0	0
RomTlOAReadyKnown_A	312034316	311867096	0	0
RomTlODDataKnown_A	312034316	9794037	0	0
RomTlODDataKnown_AKnownEnable	312034316	311867096	0	0
RomTlODValidKnown_A	312034316	311867096	0	0
StabilityChkKmac_A	312034316	258970695	0	0
StabilityChkkeymgr_A	312034316	52776964	0	0
TlAccessChk_A	312034316	259089033	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	312034316	70	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	312034316	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	312034316	464	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	312034316	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	311867096	0	0
T1	196914	196856	0	0
T2	172806	172707	0	0
T3	693129	692990	0	0
T4	443397	443266	0	0
T5	592954	592667	0	0
T6	657348	657282	0	0
T7	164126	164074	0	0
T8	16746	16673	0	0
T9	119283	119027	0	0
T10	271454	271336	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312023050	311862536	0	0
T1	196914	196856	0	0
T2	172806	172707	0	0
T3	693129	692990	0	0
T4	443397	443266	0	0
T5	592954	592667	0	0
T6	657348	657282	0	0
T7	164126	164074	0	0
T8	16746	16673	0	0
T9	119272	119024	0	0
T10	271405	271314	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	70	0	0
T16	261353	0	0	0
T25	424187	0	0	0
T28	162482	20	0	0
T29	0	10	0	0
T30	0	20	0	0
T33	0	10	0	0
T34	0	10	0	0
T35	135936	0	0	0
T36	670924	0	0	0
T37	772300	0	0	0
T38	733973	0	0	0
T39	52216	0	0	0
T40	90041	0	0	0
T41	752104	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	52778063	0	0
T1	196914	1384	0	0
T2	172806	849	0	0
T3	693129	4	0	0
T4	443397	1669	0	0
T5	592954	2143	0	0
T6	657348	647444	0	0
T7	164126	103	0	0
T8	16746	276	0	0
T9	119283	3090	0	0
T10	271454	7637	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	311867096	0	0
T1	196914	196856	0	0
T2	172806	172707	0	0
T3	693129	692990	0	0
T4	443397	443266	0	0
T5	592954	592667	0	0
T6	657348	657282	0	0
T7	164126	164074	0	0
T8	16746	16673	0	0
T9	119283	119027	0	0
T10	271454	271336	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	311867096	0	0
T1	196914	196856	0	0
T2	172806	172707	0	0
T3	693129	692990	0	0
T4	443397	443266	0	0
T5	592954	592667	0	0
T6	657348	657282	0	0
T7	164126	164074	0	0
T8	16746	16673	0	0
T9	119283	119027	0	0
T10	271454	271336	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	0	0	315

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	258972979	0	0
T1	196914	195400	0	0
T2	172806	171834	0	0
T3	693129	692770	0	0
T4	443397	441439	0	0
T5	592954	590271	0	0
T6	657348	98256	0	0
T7	164126	163896	0	0
T8	16746	16376	0	0
T9	119283	118564	0	0
T10	271454	270481	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	311867096	0	0
T1	196914	196856	0	0
T2	172806	172707	0	0
T3	693129	692990	0	0
T4	443397	443266	0	0
T5	592954	592667	0	0
T6	657348	657282	0	0
T7	164126	164074	0	0
T8	16746	16673	0	0
T9	119283	119027	0	0
T10	271454	271336	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	311867096	0	0
T1	196914	196856	0	0
T2	172806	172707	0	0
T3	693129	692990	0	0
T4	443397	443266	0	0
T5	592954	592667	0	0
T6	657348	657282	0	0
T7	164126	164074	0	0
T8	16746	16673	0	0
T9	119283	119027	0	0
T10	271454	271336	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	0	0	315

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	311867096	0	0
T1	196914	196856	0	0
T2	172806	172707	0	0
T3	693129	692990	0	0
T4	443397	443266	0	0
T5	592954	592667	0	0
T6	657348	657282	0	0
T7	164126	164074	0	0
T8	16746	16673	0	0
T9	119283	119027	0	0
T10	271454	271336	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	311867096	0	0
T1	196914	196856	0	0
T2	172806	172707	0	0
T3	693129	692990	0	0
T4	443397	443266	0	0
T5	592954	592667	0	0
T6	657348	657282	0	0
T7	164126	164074	0	0
T8	16746	16673	0	0
T9	119283	119027	0	0
T10	271454	271336	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	11241915	0	0
T3	693129	1	0	0
T4	443397	32	0	0
T5	592954	64	0	0
T6	657348	176671	0	0
T7	164126	3	0	0
T8	16746	38	0	0
T9	119283	28	0	0
T10	271454	11	0	0
T11	690986	121	0	0
T14	564148	96	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	311867096	0	0
T1	196914	196856	0	0
T2	172806	172707	0	0
T3	693129	692990	0	0
T4	443397	443266	0	0
T5	592954	592667	0	0
T6	657348	657282	0	0
T7	164126	164074	0	0
T8	16746	16673	0	0
T9	119283	119027	0	0
T10	271454	271336	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	311867096	0	0
T1	196914	196856	0	0
T2	172806	172707	0	0
T3	693129	692990	0	0
T4	443397	443266	0	0
T5	592954	592667	0	0
T6	657348	657282	0	0
T7	164126	164074	0	0
T8	16746	16673	0	0
T9	119283	119027	0	0
T10	271454	271336	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	311867096	0	0
T1	196914	196856	0	0
T2	172806	172707	0	0
T3	693129	692990	0	0
T4	443397	443266	0	0
T5	592954	592667	0	0
T6	657348	657282	0	0
T7	164126	164074	0	0
T8	16746	16673	0	0
T9	119283	119027	0	0
T10	271454	271336	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	9794037	0	0
T1	196914	206	0	0
T2	172806	285	0	0
T3	693129	0	0	0
T4	443397	79	0	0
T5	592954	601	0	0
T6	657348	448181	0	0
T7	164126	0	0	0
T8	16746	0	0	0
T9	119283	3	0	0
T10	271454	9	0	0
T11	0	360	0	0
T13	0	47	0	0
T14	0	188	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	311867096	0	0
T1	196914	196856	0	0
T2	172806	172707	0	0
T3	693129	692990	0	0
T4	443397	443266	0	0
T5	592954	592667	0	0
T6	657348	657282	0	0
T7	164126	164074	0	0
T8	16746	16673	0	0
T9	119283	119027	0	0
T10	271454	271336	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	311867096	0	0
T1	196914	196856	0	0
T2	172806	172707	0	0
T3	693129	692990	0	0
T4	443397	443266	0	0
T5	592954	592667	0	0
T6	657348	657282	0	0
T7	164126	164074	0	0
T8	16746	16673	0	0
T9	119283	119027	0	0
T10	271454	271336	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	258970695	0	0
T1	196914	195399	0	0
T2	172806	171833	0	0
T3	693129	692768	0	0
T4	443397	441437	0	0
T5	592954	590267	0	0
T6	657348	98250	0	0
T7	164126	163895	0	0
T8	16746	16375	0	0
T9	119283	118561	0	0
T10	271454	270479	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	52776964	0	0
T1	196914	1383	0	0
T2	172806	848	0	0
T3	693129	3	0	0
T4	443397	1667	0	0
T5	592954	2140	0	0
T6	657348	647443	0	0
T7	164126	102	0	0
T8	16746	275	0	0
T9	119283	3079	0	0
T10	271454	7627	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	259089033	0	0
T1	196914	195472	0	0
T2	172806	171858	0	0
T3	693129	692986	0	0
T4	443397	441597	0	0
T5	592954	590524	0	0
T6	657348	98382	0	0
T7	164126	163971	0	0
T8	16746	16397	0	0
T9	119283	118718	0	0
T10	271454	270572	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	70	0	0
T16	261353	0	0	0
T25	424187	0	0	0
T28	162482	20	0	0
T29	0	10	0	0
T30	0	20	0	0
T33	0	10	0	0
T34	0	10	0	0
T35	135936	0	0	0
T36	670924	0	0	0
T37	772300	0	0	0
T38	733973	0	0	0
T39	52216	0	0	0
T40	90041	0	0	0
T41	752104	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	464	0	0
T9	119283	11	0	0
T10	271454	0	0	0
T11	690986	0	0	0
T13	651773	5	0	0
T14	564148	0	0	0
T23	555120	0	0	0
T24	98986	0	0	0
T25	0	5	0	0
T26	0	16	0	0
T27	0	5	0	0
T28	0	20	0	0
T32	16720	0	0	0
T42	0	5	0	0
T43	0	10	0	0
T44	0	5	0	0
T45	0	10	0	0
T46	706134	0	0	0
T47	221512	0	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312034316	0	0	0