Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3036791

1

T2

290

T4

61

T5

123

full_word

1959263

1

T2

33

T4

8

T5

13

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4995784	1			T2	323		T4	69		T5	136
auto[TlIntgErrCmd]	104	1			T55	2		T56	10		T57	2
auto[TlIntgErrData]	72	1			T55	3		T56	3		T57	3
auto[TlIntgErrBoth]	94	1			T55	5		T56	7		T57	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

800233

1

T2

323

T4

69

T5

136

auto[1]

4195821

1

T26

403928

T27

143653

T28

94532

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	336227	1			T2	290		T4	61		T5	123
auto[TlIntgErrNone]	partial	auto[1]	2700315	1			T26	260376		T27	92150		T28	59540
auto[TlIntgErrNone]	full_word	auto[0]	463892	1			T2	33		T4	8		T5	13
auto[TlIntgErrNone]	full_word	auto[1]	1495350	1			T26	143552		T27	51503		T28	34992
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T55	1		T56	1		T57	1
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T55	1		T56	9		T57	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T99	1		T105	1		T106	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T107	1		T104	1		T108	1
auto[TlIntgErrData]	partial	auto[0]	31	1			T55	1		T56	2		T57	1
auto[TlIntgErrData]	partial	auto[1]	36	1			T55	2		T56	1		T57	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T109	1		T110	1		T111	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T105	1		T101	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T55	2		T56	1		T57	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T55	3		T56	4		T57	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T105	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T56	2		T100	1		T102	1