Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35864	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

520367

1

T3

54581

T4

6

T5

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	157782	1			T3	14030		T4	55		T5	78
values[0x0]	195605	1			T3	20624		T16	75355		T17	15688
values[0x1]	202844	1			T3	21388		T16	78225		T17	16290

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17433	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

538798

1

T3

55249

T4

37

T5

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1943	1			T3	198		T13	1		T45	2
valid_sources[0x01]	1884	1			T3	165		T10	3		T13	5
valid_sources[0x02]	1926	1			T3	208		T14	1		T45	2
valid_sources[0x03]	2129	1			T3	213		T13	5		T94	3
valid_sources[0x04]	2018	1			T3	221		T4	16		T45	2
valid_sources[0x05]	2075	1			T3	176		T5	3		T11	1
valid_sources[0x06]	2252	1			T3	169		T13	1		T14	6
valid_sources[0x07]	1992	1			T3	225		T11	2		T13	2
valid_sources[0x08]	2480	1			T3	203		T13	4		T45	1
valid_sources[0x09]	2071	1			T3	211		T45	2		T66	11
valid_sources[0x0a]	1958	1			T3	207		T10	2		T45	2
valid_sources[0x0b]	2086	1			T3	191		T5	2		T11	3
valid_sources[0x0c]	2450	1			T3	216		T13	2		T45	4
valid_sources[0x0d]	1957	1			T3	171		T5	1		T93	2
valid_sources[0x0e]	2099	1			T3	230		T5	1		T13	1
valid_sources[0x0f]	2015	1			T3	227		T13	1		T14	19
valid_sources[0x10]	2123	1			T3	268		T4	28		T7	8
valid_sources[0x11]	1974	1			T3	253		T13	1		T45	1
valid_sources[0x12]	2039	1			T3	226		T14	2		T63	27
valid_sources[0x13]	2170	1			T3	211		T7	2		T13	1
valid_sources[0x14]	1962	1			T3	250		T5	1		T10	5
valid_sources[0x15]	2045	1			T3	198		T5	1		T13	1
valid_sources[0x16]	2362	1			T3	198		T13	1		T45	1
valid_sources[0x17]	1996	1			T3	240		T45	2		T46	1
valid_sources[0x18]	2116	1			T3	244		T10	1		T13	1
valid_sources[0x19]	2876	1			T3	224		T14	8		T45	1
valid_sources[0x1a]	2031	1			T3	216		T13	5		T66	1
valid_sources[0x1b]	2256	1			T3	270		T10	9		T13	1
valid_sources[0x1c]	2479	1			T3	186		T13	1		T45	1
valid_sources[0x1d]	3265	1			T3	213		T5	1		T13	4
valid_sources[0x1e]	1878	1			T3	159		T10	2		T13	10
valid_sources[0x1f]	2620	1			T3	204		T7	6		T13	3
valid_sources[0x20]	1970	1			T3	220		T5	1		T45	3
valid_sources[0x21]	2046	1			T3	248		T5	1		T13	1
valid_sources[0x22]	2348	1			T3	197		T13	3		T45	2
valid_sources[0x23]	2031	1			T3	246		T5	2		T13	1
valid_sources[0x24]	2081	1			T3	233		T10	2		T13	5
valid_sources[0x25]	2713	1			T3	199		T16	831		T117	3
valid_sources[0x26]	2466	1			T3	225		T45	2		T46	1
valid_sources[0x27]	2008	1			T3	214		T93	2		T16	833
valid_sources[0x28]	2750	1			T3	229		T5	2		T13	4
valid_sources[0x29]	1904	1			T3	204		T45	2		T118	1
valid_sources[0x2a]	2438	1			T3	222		T13	1		T45	1
valid_sources[0x2b]	2798	1			T3	209		T11	1		T13	1
valid_sources[0x2c]	2171	1			T3	215		T46	2		T118	2
valid_sources[0x2d]	2096	1			T3	190		T10	6		T119	17
valid_sources[0x2e]	1851	1			T3	178		T5	2		T10	5
valid_sources[0x2f]	1958	1			T3	217		T10	13		T13	1
valid_sources[0x30]	2091	1			T3	253		T13	1		T14	3
valid_sources[0x31]	2505	1			T3	259		T46	1		T94	3
valid_sources[0x32]	2339	1			T3	208		T13	1		T63	24
valid_sources[0x33]	1956	1			T3	147		T10	21		T45	1
valid_sources[0x34]	1921	1			T3	188		T10	1		T14	13
valid_sources[0x35]	2143	1			T3	223		T10	1		T11	6
valid_sources[0x36]	2037	1			T3	271		T11	2		T118	1
valid_sources[0x37]	2233	1			T3	243		T45	1		T46	7
valid_sources[0x38]	2068	1			T3	253		T45	1		T93	4
valid_sources[0x39]	2081	1			T3	176		T13	1		T16	892
valid_sources[0x3a]	2111	1			T3	191		T5	1		T10	5
valid_sources[0x3b]	2186	1			T3	247		T13	3		T46	5
valid_sources[0x3c]	2015	1			T3	197		T12	1		T15	2
valid_sources[0x3d]	2078	1			T3	266		T13	3		T26	2
valid_sources[0x3e]	1992	1			T3	222		T5	1		T94	1
valid_sources[0x3f]	1995	1			T3	206		T13	1		T14	7
valid_sources[0x40]	2586	1			T3	256		T5	1		T10	4
valid_sources[0x41]	2271	1			T3	194		T13	1		T94	1
valid_sources[0x42]	2175	1			T3	175		T93	2		T16	758
valid_sources[0x43]	2190	1			T3	255		T5	1		T10	7
valid_sources[0x44]	2073	1			T3	242		T37	18		T93	1
valid_sources[0x45]	2171	1			T3	210		T7	3		T13	2
valid_sources[0x46]	2464	1			T3	216		T10	9		T13	2
valid_sources[0x47]	1943	1			T3	180		T5	2		T11	1
valid_sources[0x48]	1894	1			T3	172		T13	1		T45	1
valid_sources[0x49]	2140	1			T3	188		T13	1		T118	2
valid_sources[0x4a]	2115	1			T3	182		T13	3		T45	1
valid_sources[0x4b]	2019	1			T3	211		T5	1		T11	2
valid_sources[0x4c]	2008	1			T3	220		T11	1		T14	1
valid_sources[0x4d]	2320	1			T3	194		T10	6		T13	3
valid_sources[0x4e]	2864	1			T3	233		T10	8		T11	1
valid_sources[0x4f]	1867	1			T3	214		T13	2		T45	1
valid_sources[0x50]	1876	1			T3	189		T13	1		T94	2
valid_sources[0x51]	1966	1			T3	221		T11	1		T13	1
valid_sources[0x52]	2536	1			T3	193		T7	5		T13	4
valid_sources[0x53]	2312	1			T3	254		T10	1		T13	2
valid_sources[0x54]	2301	1			T3	240		T63	1		T36	1
valid_sources[0x55]	2405	1			T3	258		T13	2		T45	2
valid_sources[0x56]	2798	1			T3	219		T45	1		T47	12
valid_sources[0x57]	2207	1			T3	241		T13	1		T92	6
valid_sources[0x58]	1986	1			T3	272		T13	1		T118	1
valid_sources[0x59]	2039	1			T3	181		T14	4		T45	2
valid_sources[0x5a]	1963	1			T3	231		T13	1		T45	1
valid_sources[0x5b]	2061	1			T3	231		T35	1		T16	790
valid_sources[0x5c]	2092	1			T3	283		T5	1		T45	1
valid_sources[0x5d]	1965	1			T3	234		T5	2		T45	2
valid_sources[0x5e]	2053	1			T3	214		T5	1		T13	2
valid_sources[0x5f]	2123	1			T3	228		T5	2		T13	4
valid_sources[0x60]	2044	1			T3	223		T11	1		T27	2
valid_sources[0x61]	2028	1			T3	250		T14	5		T66	18
valid_sources[0x62]	2219	1			T3	190		T13	2		T14	8
valid_sources[0x63]	2823	1			T3	217		T5	1		T14	7
valid_sources[0x64]	2006	1			T3	205		T4	11		T5	2
valid_sources[0x65]	2185	1			T3	255		T5	1		T10	4
valid_sources[0x66]	1954	1			T3	171		T10	6		T14	4
valid_sources[0x67]	2323	1			T3	187		T45	5		T46	7
valid_sources[0x68]	1990	1			T3	208		T64	16		T93	1
valid_sources[0x69]	2123	1			T3	181		T13	1		T45	1
valid_sources[0x6a]	2048	1			T3	225		T13	1		T45	1
valid_sources[0x6b]	2249	1			T3	195		T10	2		T13	1
valid_sources[0x6c]	2021	1			T3	234		T11	2		T65	39
valid_sources[0x6d]	2265	1			T3	219		T14	5		T45	1
valid_sources[0x6e]	2072	1			T3	220		T13	2		T14	8
valid_sources[0x6f]	2202	1			T3	265		T11	1		T13	2
valid_sources[0x70]	2055	1			T3	227		T10	3		T45	1
valid_sources[0x71]	2004	1			T3	240		T14	10		T45	1
valid_sources[0x72]	2019	1			T3	202		T10	2		T45	4
valid_sources[0x73]	1992	1			T3	191		T11	2		T118	1
valid_sources[0x74]	1925	1			T3	183		T11	2		T13	1
valid_sources[0x75]	2076	1			T3	190		T10	2		T13	2
valid_sources[0x76]	1961	1			T3	214		T47	13		T93	1
valid_sources[0x77]	2508	1			T3	168		T13	1		T118	1
valid_sources[0x78]	2206	1			T3	226		T10	3		T13	2
valid_sources[0x79]	2450	1			T3	253		T5	1		T13	1
valid_sources[0x7a]	2314	1			T3	261		T27	1		T41	23
valid_sources[0x7b]	2230	1			T3	180		T5	2		T13	1
valid_sources[0x7c]	2059	1			T3	263		T13	1		T45	1
valid_sources[0x7d]	1831	1			T3	189		T5	1		T11	1
valid_sources[0x7e]	1990	1			T3	233		T40	1		T93	2
valid_sources[0x7f]	2431	1			T3	243		T5	1		T13	4
valid_sources[0x80]	2167	1			T3	215		T36	1		T93	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

132256

1

T3

13566

T4

6

T5

5

values[0x0]

all_enables

biggest_size

193978

1

T3

20481

T16

74717

T17

15552

values[0x1]

all_enables

biggest_size

194133

1

T3

20534

T16

74839

T17

15654

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44201	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

404076

1

T1

1

T2

1

T3

38893

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	115457	1			T3	10476		T4	32		T6	1
values[0x0]	154132	1			T1	3		T2	5		T3	14798
values[0x1]	178688	1			T1	8		T2	6		T3	17203

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21674	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

426603

1

T1

4

T2

4

T3

40933

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1496	1			T3	162		T118	1		T29	1
valid_sources[0x01]	1200	1			T3	163		T14	1		T67	1
valid_sources[0x02]	1599	1			T3	176		T120	1		T16	725
valid_sources[0x03]	2190	1			T3	158		T14	2		T46	1
valid_sources[0x04]	1507	1			T3	168		T4	1		T64	1
valid_sources[0x05]	1620	1			T3	156		T10	1		T59	1
valid_sources[0x06]	1387	1			T3	163		T67	1		T118	1
valid_sources[0x07]	1617	1			T3	179		T4	1		T10	1
valid_sources[0x08]	1721	1			T3	166		T7	1		T14	1
valid_sources[0x09]	1886	1			T3	157		T14	1		T16	681
valid_sources[0x0a]	1776	1			T3	155		T10	1		T64	1
valid_sources[0x0b]	1909	1			T3	165		T15	4		T64	2
valid_sources[0x0c]	1983	1			T3	181		T12	16		T67	2
valid_sources[0x0d]	1838	1			T3	133		T7	1		T46	1
valid_sources[0x0e]	1632	1			T3	136		T10	1		T14	2
valid_sources[0x0f]	1686	1			T3	156		T120	2		T92	3
valid_sources[0x10]	1512	1			T3	187		T4	1		T46	1
valid_sources[0x11]	1499	1			T3	160		T64	1		T27	2
valid_sources[0x12]	1500	1			T3	186		T15	1		T26	1
valid_sources[0x13]	1825	1			T3	177		T12	2		T46	1
valid_sources[0x14]	1905	1			T3	146		T64	1		T16	686
valid_sources[0x15]	1853	1			T3	183		T26	1		T67	1
valid_sources[0x16]	2120	1			T3	175		T4	1		T10	1
valid_sources[0x17]	2054	1			T3	156		T46	2		T67	1
valid_sources[0x18]	2313	1			T3	161		T10	1		T14	2
valid_sources[0x19]	1433	1			T3	151		T14	1		T26	1
valid_sources[0x1a]	1576	1			T3	146		T66	1		T67	1
valid_sources[0x1b]	1192	1			T3	176		T118	1		T42	1
valid_sources[0x1c]	2046	1			T3	147		T14	1		T26	1
valid_sources[0x1d]	1708	1			T2	1		T3	135		T10	1
valid_sources[0x1e]	2071	1			T3	166		T14	1		T67	1
valid_sources[0x1f]	1845	1			T3	180		T7	4		T118	1
valid_sources[0x20]	1720	1			T3	189		T10	1		T14	1
valid_sources[0x21]	1761	1			T3	171		T14	3		T118	1
valid_sources[0x22]	1638	1			T3	144		T64	1		T56	1
valid_sources[0x23]	2063	1			T3	149		T10	1		T36	4
valid_sources[0x24]	2073	1			T3	155		T14	2		T46	1
valid_sources[0x25]	1613	1			T3	165		T7	1		T10	1
valid_sources[0x26]	1579	1			T3	171		T14	2		T66	2
valid_sources[0x27]	1990	1			T3	163		T4	1		T67	1
valid_sources[0x28]	1652	1			T3	159		T14	1		T64	1
valid_sources[0x29]	1870	1			T3	194		T7	1		T40	2
valid_sources[0x2a]	1654	1			T3	148		T7	1		T14	1
valid_sources[0x2b]	1362	1			T3	135		T10	1		T14	1
valid_sources[0x2c]	1638	1			T3	176		T4	1		T9	2
valid_sources[0x2d]	1710	1			T3	159		T10	1		T14	1
valid_sources[0x2e]	1406	1			T3	171		T14	1		T118	2
valid_sources[0x2f]	1577	1			T3	147		T16	542		T48	312
valid_sources[0x30]	1688	1			T3	156		T11	4		T14	1
valid_sources[0x31]	1282	1			T3	179		T29	1		T16	351
valid_sources[0x32]	1904	1			T3	151		T14	2		T15	1
valid_sources[0x33]	1856	1			T3	150		T10	2		T14	1
valid_sources[0x34]	1283	1			T3	161		T10	6		T95	1
valid_sources[0x35]	1628	1			T3	125		T4	1		T10	1
valid_sources[0x36]	1723	1			T3	179		T14	2		T64	1
valid_sources[0x37]	1387	1			T3	166		T10	2		T64	1
valid_sources[0x38]	2149	1			T3	160		T10	3		T46	1
valid_sources[0x39]	1780	1			T3	160		T16	794		T48	382
valid_sources[0x3a]	1886	1			T3	163		T7	2		T10	1
valid_sources[0x3b]	1940	1			T3	139		T10	1		T64	2
valid_sources[0x3c]	2277	1			T3	185		T10	2		T120	1
valid_sources[0x3d]	1447	1			T3	144		T64	1		T95	4
valid_sources[0x3e]	2109	1			T3	167		T64	1		T67	3
valid_sources[0x3f]	1766	1			T3	164		T6	1		T36	6
valid_sources[0x40]	1948	1			T3	143		T66	1		T34	1
valid_sources[0x41]	1278	1			T3	174		T67	1		T16	396
valid_sources[0x42]	1525	1			T3	155		T7	2		T10	3
valid_sources[0x43]	1415	1			T3	158		T64	1		T27	1
valid_sources[0x44]	1796	1			T3	160		T14	1		T66	1
valid_sources[0x45]	1384	1			T3	196		T14	1		T67	1
valid_sources[0x46]	1646	1			T3	177		T34	1		T16	551
valid_sources[0x47]	1913	1			T3	184		T26	3		T67	1
valid_sources[0x48]	1786	1			T3	179		T4	1		T34	1
valid_sources[0x49]	1649	1			T3	150		T14	1		T64	1
valid_sources[0x4a]	1550	1			T3	173		T10	1		T27	1
valid_sources[0x4b]	1699	1			T3	168		T10	1		T27	4
valid_sources[0x4c]	1983	1			T2	1		T3	142		T10	1
valid_sources[0x4d]	1402	1			T3	164		T10	2		T64	1
valid_sources[0x4e]	1736	1			T3	162		T64	1		T16	582
valid_sources[0x4f]	1397	1			T3	180		T10	3		T64	1
valid_sources[0x50]	1792	1			T3	164		T11	2		T26	1
valid_sources[0x51]	1657	1			T3	174		T4	1		T46	2
valid_sources[0x52]	2280	1			T3	162		T7	1		T10	1
valid_sources[0x53]	1670	1			T3	154		T66	1		T16	666
valid_sources[0x54]	1302	1			T3	167		T15	2		T92	1
valid_sources[0x55]	1585	1			T3	175		T4	1		T12	3
valid_sources[0x56]	1752	1			T3	172		T14	2		T46	1
valid_sources[0x57]	1756	1			T3	144		T10	1		T12	1
valid_sources[0x58]	1736	1			T2	1		T3	170		T4	1
valid_sources[0x59]	1375	1			T3	160		T10	1		T46	1
valid_sources[0x5a]	2374	1			T3	150		T10	2		T27	2
valid_sources[0x5b]	1671	1			T3	174		T66	1		T40	8
valid_sources[0x5c]	2222	1			T3	141		T14	1		T15	1
valid_sources[0x5d]	1842	1			T3	175		T118	1		T120	2
valid_sources[0x5e]	1424	1			T3	147		T7	1		T10	2
valid_sources[0x5f]	1240	1			T3	152		T35	1		T16	503
valid_sources[0x60]	1529	1			T3	166		T14	1		T64	1
valid_sources[0x61]	1408	1			T3	175		T46	1		T67	2
valid_sources[0x62]	1759	1			T3	161		T10	1		T16	729
valid_sources[0x63]	1810	1			T3	146		T10	3		T26	1
valid_sources[0x64]	1568	1			T3	145		T92	2		T16	560
valid_sources[0x65]	1783	1			T3	142		T10	1		T64	1
valid_sources[0x66]	1490	1			T3	169		T7	1		T10	2
valid_sources[0x67]	2402	1			T3	160		T14	1		T64	2
valid_sources[0x68]	1659	1			T3	176		T10	1		T64	1
valid_sources[0x69]	1892	1			T3	172		T16	716		T17	317
valid_sources[0x6a]	1843	1			T3	153		T10	1		T39	1
valid_sources[0x6b]	2577	1			T3	158		T14	3		T27	1
valid_sources[0x6c]	1799	1			T3	171		T10	1		T15	1
valid_sources[0x6d]	2426	1			T3	169		T15	1		T64	2
valid_sources[0x6e]	2022	1			T3	155		T10	2		T14	1
valid_sources[0x6f]	1792	1			T3	177		T14	2		T64	1
valid_sources[0x70]	1970	1			T3	214		T26	2		T120	2
valid_sources[0x71]	1369	1			T3	174		T10	1		T64	1
valid_sources[0x72]	2176	1			T3	143		T10	1		T12	19
valid_sources[0x73]	1938	1			T3	179		T8	1		T10	1
valid_sources[0x74]	1698	1			T3	184		T16	668		T48	328
valid_sources[0x75]	1839	1			T3	178		T10	1		T16	922
valid_sources[0x76]	1567	1			T3	154		T27	1		T56	1
valid_sources[0x77]	1308	1			T3	169		T14	1		T64	1
valid_sources[0x78]	2007	1			T3	152		T7	1		T64	1
valid_sources[0x79]	1341	1			T3	186		T64	1		T16	460
valid_sources[0x7a]	1554	1			T3	168		T10	2		T34	1
valid_sources[0x7b]	1645	1			T3	169		T14	3		T35	1
valid_sources[0x7c]	2060	1			T3	173		T14	3		T64	1
valid_sources[0x7d]	1847	1			T3	177		T42	1		T16	628
valid_sources[0x7e]	2159	1			T3	180		T7	2		T10	2
valid_sources[0x7f]	1721	1			T3	166		T10	2		T46	1
valid_sources[0x80]	1808	1			T3	171		T66	1		T120	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

102612

1

T3

9788

T4

20

T7

18

values[0x0]

all_enables

biggest_size

150507

1

T2

1

T3

14532

T9

1

values[0x1]

all_enables

biggest_size

150957

1

T1

1

T3

14573

T56

1